Scribd
Upload
3K views1 page

Armv4T: Feature Arm7 Arm9E Arm11 Comparison of Arm7, Arm9 & Arm11 Architectures

The document compares key features of the ARM7, ARM9, and ARM11 processor architectures. The ARM11 has the most advanced architecture with an 8-stage pipeline, support for Java byte code decoding and SIMD instructions, static branch prediction, an independent load-store unit, and out-of-order completion. It also has the highest MIPS/MHz rating and smallest process size compared to the ARM7 and ARM9.

Uploaded by

guddu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
3K views1 page

Armv4T: Feature Arm7 Arm9E Arm11 Comparison of Arm7, Arm9 & Arm11 Architectures

The document compares key features of the ARM7, ARM9, and ARM11 processor architectures. The ARM11 has the most advanced architecture with an 8-stage pipeline, support for Java byte code decoding and SIMD instructions, static branch prediction, an independent load-store unit, and out-of-order completion. It also has the highest MIPS/MHz rating and smallest process size compared to the ARM7 and ARM9.

Uploaded by

guddu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Comparison of ARM7, ARM9 & ARM11 architectures

Feature ARM7 ARM9E ARM11


Architecture ARMv4T ARMv5TE(J) ARMv6
Pipeline Length 3 5 8
8 bit JAVA byte code
Java Decode used in Jazelle state (ARM926EJ) Yes
V6 SIMD Instructions No No Yes
Available as
MIA Instructions Yes No coprocessor
Branch Prediction No No Static
Independent Load-Store
Unit No No Yes
Instruction Issue Scalar, in-order Scalar, in-order
Concurrency None None ALU/MAC, LSU
Out-of-order completion No No Yes
Synthesizable and
Target Implementation Synthesizable Synthesizable Hard macro
Von Neumann
General Architecture Von Neumann Harvard architecture /Harvard
Process 0.35 m 0.25 m 0.13 m
MIPS/MHz 0.9 1.1 1.2

You might also like