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CourseOutline VLSI - 2

This document provides information about the EE405 VLSI Design course offered in the Fall 2017 semester at the International Islamic University. The course is a 3+1 credit hour course taught by Dr. Muhammad Sohail and introduces CMOS VLSI design methodologies with a focus on full-custom chip design. Students will use CAD tools to design, simulate, and verify IC layouts. The course covers techniques for designing high-speed, low-power, and easily testable circuits. It will include lectures on topics like the manufacturing process, CMOS devices, combinational and sequential logic design, and implementation strategies. Student performance will be evaluated through quizzes, assignments, midterm and final exams.

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FaHeem Khan
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76 views

CourseOutline VLSI - 2

This document provides information about the EE405 VLSI Design course offered in the Fall 2017 semester at the International Islamic University. The course is a 3+1 credit hour course taught by Dr. Muhammad Sohail and introduces CMOS VLSI design methodologies with a focus on full-custom chip design. Students will use CAD tools to design, simulate, and verify IC layouts. The course covers techniques for designing high-speed, low-power, and easily testable circuits. It will include lectures on topics like the manufacturing process, CMOS devices, combinational and sequential logic design, and implementation strategies. Student performance will be evaluated through quizzes, assignments, midterm and final exams.

Uploaded by

FaHeem Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FACULTY OF ENGINEERING & TECHNOLOGY

DEPARTMENT OF ELECTRICAL ENGINEERING INTERNATIONAL ISLAMIC UNIVERSITY

EE405 VLSI Design (Fall 2017) Credit Hrs:3+1=4

Instructor: Dr. Muhammad Sohail Designation: Assistant Professor (BPS-19) , DEE


Email: [email protected] Room: A-002 Block II Ext.: 2469
Office Hours: 1:30pm 4:30pm(Tue & Wed)

Prerequisites: i) EE-202 ECD-1 ii) EE-203 ECD-2 iii) EE-210 DLD

Course Objectives:
To introduce students to CMOS VLSI design methodologies with emphasis on full-custom chip
design. Students will make extensive use of CAD tools for IC design, simulation, and layout
verification. Specific techniques for designing high-speed, low-power, and easily-testable
circuits will also be covered.

Text Book:

Digital Integrated Circuits, A Design Perspective, 2nd Edition, By Jan M. Rabaey, Anthana
Chandrakasan, Borivoje Nikolic

Reference Books:

Modern VLSI Design: IP-Based Design, 4th Edition By Wayne Wolf, Prentice Hall
CMOS Integrated Circuits, Analysis and Design, By Sung- Mo Kang, Yusuf Leblebici
Introduction to VLSI circuits and systems By John P. Uyemura

Grading Policy:

Quizzes (Announced + Surprise) 20%


Assignments 05%
Mid-term exam 25%
Final Exam 50%

Attendance Policy:
Minimum 75% attendance is necessary to appear in the final exam.
Any approved leave will not be counted towards the attendance.

Instructions:
No late submission of assignments.
No makeup quiz.

Note:
Above contents and procedures in the course can be changed if needed.
Lecture Plan (Tentative)
Week Topic
CHAPTER 1: INTRODUCTION
1.1 A Historical Perspective
1
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
Chapter 2: THE MANUFACTURING PROCESS
2 2.1 Introduction
2.2 Manufacturing CMOS Integrated Circuits
2.3 Design Rules The Contract between Designer and Process Engineer
3 2.4 Packaging Integrated Circuits
2.5 Perspective Trends in Process Technology
CHPATER 3: THE DEVICES
4
3.1 Introduction
3.2 The Diode
5
3.3 The MOS(FET) Transistor

6 Chapter 5: THE CMOS INVERTER


5.1 Introduction
5.2 The Static CMOS Inverter An Intuitive Perspective
7
5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior
5.4 Performance of CMOS Inverter: The Dynamic Behavior
8 5.5 Power, Energy, and Energy-Delay

9 CHAPTER 6: DESIGNING COMBINATIONAL LOGIC GATES IN CMOS


6.1 Introduction
10 6.2 Static CMOS Design
6.3 Dynamic CMOS Design
11 6.4 Perspectives

CHAPTER 7: DESIGNING SEQUENTIAL LOGIC CIRCUITS


12
7.1 Introduction
7.2 Static Latches and Registers
7.3 Dynamic Latches and Registers
13
7.4 Alternative Register Styles*
7.5 Pipelining: An approach to optimize sequential circuits
7.6 Non-Bistable Sequential Circuits
14
7.7 Perspective: Choosing a Clocking Strategy

CHAPTER 8: IMPLEMENTATION STRATEGIES FOR DIGITAL ICS


15 8.1 Introduction
8.2 From Custom to Semicustom and Structured Array Design Approaches
8.3 Custom Circuit Design
8.4 Cell-Based Design Methodology
16 8.5 Array-Based Implementation Approaches
8.6 PerspectiveThe Implementation Platform of the Future

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