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UVM Interview Questions

The document discusses various UVM concepts and components. It compares uvm_do and uvm_rand_send, noting that uvm_do performs all steps except object creation while uvm_rand_send requires external object creation. It also compares uvm_transaction and uvm_seq_item, noting that seq_items provide hooks for sequences and sequencers while transactions only provide basic methods. Finally, it provides explanations for concepts like virtual sequences, super keywords, p_sequencer references, UVM RAL, new() vs create(), TLM FIFOs, sequencer types, UVM phases, overrides, configuration, factories, and ending simulation.

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Abdul Thoufiq
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780 views

UVM Interview Questions

The document discusses various UVM concepts and components. It compares uvm_do and uvm_rand_send, noting that uvm_do performs all steps except object creation while uvm_rand_send requires external object creation. It also compares uvm_transaction and uvm_seq_item, noting that seq_items provide hooks for sequences and sequencers while transactions only provide basic methods. Finally, it provides explanations for concepts like virtual sequences, super keywords, p_sequencer references, UVM RAL, new() vs create(), TLM FIFOs, sequencer types, UVM phases, overrides, configuration, factories, and ending simulation.

Uploaded by

Abdul Thoufiq
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. What is the difference between `uvm_do and `uvm_ran_send?

A: uvm_do perform the below steps: create->start_item->randomize->finish_item-


>get_response (optional).while `uvm_rand_send perform all the above steps except create. User
needs to create sequence / sequence_item.

1. diff between uvm_transaction and uvm_seq_item?


A: uvm_sequence_item provides the hooks for sequencer and sequence , So you can generate
transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like
do_print and do_record etc .

Sequence_item --> Wr or rd or both of them


sequence --> collection of sequence items

Conceptually, sort of. Sequences are objects whose body() method is used to generate
sequence_items to be sent to the driver.
A virtual sequence is a sequence that controls the execution of other sequences and almost never
generates sequence_items itself. This is different from a sequence_library which is a sequence that
lets you pick from a group of sequences that are registered with the library.
Quote:
Shall i use virtual sequence on different agent sequencers? how it can be done?

A virtual sequence contains pointers to agent sequencers so you start other sequences on those
sequencers.

What is super keyword? What is the need of calling super.build() and super.connect()?
A: super is a keyword. It is used inside a sub-class method definition to call a method
defined in the super class. Private methods of the super-class cannot be called. Only public
and protected methods can be called by the super keyword. It is also used by class
constructors to invoke constructors of its parent class.
What is p_sequencer?
A: p_sequencer usage in UVM !!!
UVM sequences generally do not have access to the TLM ports In that case the TLM ports and other
features available in the sequencer can be accessed from the sequence using p_sequencer
reference. This feature is very useful in a layering scenario when higher level sequence is layered into
the lower level sequence.

What is UVM RAN? And why its required


A:By using UVM RAL in the conventional method, we tend to create handles for all these
register classes, we then compile them, load them and simulate them in every test. ... This
handle creation also facilitates any overrides if requested.

What is the difference between new() and create?


A:Create() is a factory method which construct an object. To override an object you need to
construct it using create(). if you use set_type_override then before run ,factory replaces
constructed object with derived object( specified in override).

if you use new() then you cant override.


What is TLM FIFO?

TLM FIFO is used to synchronize data flow between producer and. consumer. So, the
producer puts the transaction into the TLM FIFO fifo, while the. consumer independently
gets the transaction from the FIFO.

What is the difference between copy and clone

Clone() : It gives the shallow copy of the object


Copy() : It gives the deep copy of the object

What are the types of sequencer? Explain each?


A: Pull and Push from sequnces /to and from from driver

What are the different phases of uvm_component? Explain each?


1. new
2. build_phase
3. connect_phase
4. end_of_elaboration_phase
5. start_of_simulation_phase
6. run_phase
1. reset_phase
2. configure_phase
3. main_phase
4. shutdown_phase
7. extract_phase
8. check_phase
9. report_phase
10. final_phase

What are the different override types?


Instance & type base overrides

How set_config_* works?


A:Configuration is a mechanism in OVM that higher level components in a hierarchy can
configure the lower level components variables. Using set_config_* methods, user can
configure integer, string and objects of lower level components. Without this mechanism,
user should access the lower level component using hierarchy paths, which restricts
reusability.
What is uvm_config_db
What is uvm_config_db and its role?
[my answer]
- used to store the fields and field values; so that particular field/s can be accessed by any part of uvm
hierarchy
- uvm_config_db is looks like a table with fields and field values
What is uvm_factory and its role?
[my answer]
- used to "register" components/fields/objects; so that it can be extended/over_ride from the any part
of uvm hierarchy
Why we need to register class with uvm factory?
UVM has introduced the factory concept which essentially means that you can modify or
substitute the nature of the components created by the factory without making changes to
the testbench. Say, you have written two driver classes, and the environment uses only one
of them. By registering both the drivers with the factory, you can ask the factory to substitute
the existing driver in environment with the other type. The code needed to achieve this is
minimal, and can be written in the test.

End simulation in UVM?


You should only raise_objection() and drop_objection() in the run_phase() of your tests

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