Digital Electronics (Formula Notes) gradeup

Number System and Codes:

A number system with base r, contents r different digits and they are from 0 to
r 1.
Decimal to other codes conversions: To convert decimal number into other system
with base r, divide integer part by r and multiply fractional part with r.

Other codes to Decimal Conversions: ( x2 x1 x0 . y1 y2 ) r (A)10

A x2 r 2 x1 r x0 y1 r 1 y 2 r 2

Hexadecimal to Binary: Convert each Hexadecimal digit into 4 bit binary.

(0101 1010 1111) 2
(5AF )16
5 A F

11 01
01 .11 00 (35.C)16

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Binary to Hexadecimal: Grouping of 4 bits into one hex digit.
(110101.11) 2 00

Octal to Binary and Binary to Octal: Same procedure as discussed above but here
group of 3 bits is made.

Codes:
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Binary coded decimal (BCD):
In BCD code each decimal digit is represented with 4 bit binary format.

Eg : (943)10 10

01 01
00 0011
9 4 9 BCD
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It is also known as 8421 code

Invalid BCD codes
Total Number possible 2 4 16
Valid BCD codes 10
Invalid BCD codes 16 10 6
These are 1010, 1011, 1100, 1101, 1110, and 1111

Excess-3 code: (BCD + 0011)

It can be derived from BCD by adding 3 to each coded number.
It is unweighted and self-complementing code.

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Gray Code:
It is also called minimum change code or unit distance code or reflected code.

Binary code to Gray code:

+ + + +
MSB 1 0 0 1 0 Binary

MSB 1 1 0 1 1 Gray

Gray code to Binary code:

Alpha Numeric codes: EBCDIC (Extended BCD Interchange code)

It is 8 bit code. It can represent 128 possible characters.
Parity Method is most widely used schemes for error detection.
Hamming code is most useful error correcting code.

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BCD code is used in calculators, counters.

Complements: If base is r then we can have two complements.

(i) (r 1)s complement.
(ii) rs complement.
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To determine (r1)s complement: First write maximum possible number in the
given system and subtract the given number.
To determine rs complement: (r1)s complement + 1
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First write (r1)s complement and then add 1 to LSB

Example: Find 7s and 8s complement of 2456

7777 5321
2456 1
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7's complement 8's complement

5321 5322
Find 2s complement of 101.110
1s complement 010.001
For 2s complement add 1 to the LSB
010.001
1
2'scomplement
010.010

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Data Representation:

Unsigned Magritude: Range with n bit 0 to 2 n 1 5 101

5 Not possible
Signed Magritude: Range with n bit (2 n 1 1) to (2 n 1 1)
6 0110 6 1 110 1 0000 110




sign bit


sign bit

with 4 bits with 8 bits

1s complement: Range with n bit (2 1) to (2 n 1 1)

n 1

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6 0110 6 1 001

sign bit 1's complement of 6

2 complement: With n bits Range 2 n 1 to (2 n 1 1)

6 0110 6 1 010

sign bit 2 's complement of 6
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In any representation
+ve numbers are represented similar to +ve number in sign magnitude.
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Boolean Laws:
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Flip Flops :

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Excitation tables :
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S R J K D T
0 0 0 x 0 0 0 x 0 0 0 0 0 0
0 1 1 0 0 1 1 x 0 1 1 0 1 1
1 0 0 1 1 0 x 1 1 0 0 1 0 1
1 1 x 0 1 1 x 0 1 1 1 1 1 0

Q(n+1) = S + R Q
=D
=J + Q
=T + Q

For ring counter total no.of states = n

For twisted Ring counter = 2n (Johnson counter / switch tail Ring counter ) .
To eliminate race around condition t <<t .
In Master slave master is level triggered & slave is edge triggered

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 Combinational Circuits
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Multiplexer :
2 i/ps ; 1 o/p & n select lines.
It can be used to implement Boolean function by selecting select lines as Boolean variables
For implementing n variable Boolean function 2 1 MUX is enough .
For implementing n + 1 variable Boolean 2 1 MUX + NOT gate is required .
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For implementing n + 2 variable Boolean function 2 1 MUX + Combinational Ckt is
required
If you want to design 2 1 MUX using 2 1 MUX . You need 2 2 1 MUXes
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Decoder :

n i/p & 2 o/ps

used to implement the Boolean function . It will generate required min terms @ o/p & those terms
should be OR ed to get the result .
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Suppose it consists of more min terms then connect the max terms to NOR gate then it will give the
same o/p with less no. of gates .
If you want to Design m 2 Decoder using n 2 Decoder . Then no. of n 2 Decoder
required = .
In Parallel (n bit ) total time delay = 2 t .
For carry look ahead adder delay = 2 t .

PROM , PLA & PAL :-

AND OR

Fixed Programmable PROM

Programmable fixed PAL

Programmable Programmable PLA

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Asynchronous Sequential circuits: Asynchronous Sequential circuits do not use a clock and can
change their output state as fast as the signal path's propagation delay from the input allows. This
means they can be faster than Synchronous Sequential circuits. However, they are considerably more
likely to suffer from race conditions (inputs arriving at different times causing different output states)
and intermediate output states (as the outputs change from one state to the next final state) than
Synchronous Sequential circuits.

Synchronous Sequential circuits: Synchronous Sequential circuits use a clock signal to alleviate the
two problems mentioned above. The outputs can only change state with the clock and are designed
such that all propagation delays are satisfied before the outputs are allowed to change. This however
makes them potentially slower (because the whole circuit must run at the speed of the slowest path in
it) and consumes significantly more power due to the extra circuitry required by distributing the clock
to all flip-flops, and the continual switching.

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I OH I OL
Fan out of a logic gate = or
I IH I IL
Noise margin : VOH - VIH or VOL - VIL
I +I
Power Dissipation PD = Vcc Icc = Vcc 2
I Ic when o/p low
I Ic when o/p high .
TTL , ECL & CMOS are used for MSI or SSI
Logic swing : VOH - VOL
RTL , DTL , TTL saturated logic ECL Un saturated logic
Advantages of Active pullup ; increased speed of operation , less power consumption .
For TTL floating i/p considered as logic 1 & for ECL it is logic 0 .
MOS mainly used for LSI & VLSI . fan out is too high
ECL is fastest gate & consumes more power .
CMOS is slowest gate & less power consumption
NMOS is faster than CMOS .
Gates with open collector o/p can be used for wired AND operation (TTL)
Gates with open emitter o/p can be used for wired OR operation (ECL)
ROM is nothing but combination of encoder & decoder . This is non volatile memory .
SRAM : stores binary information interms of voltage uses FF.

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DRAM : infor stored in terms of charge on capacitor . Used Transistors & Capacitors .
SRAM consumes more power & faster than DRAM .
CCD , RAM are volatile memories .
1024 8 memory can be obtained by using 1024 2 memories
No. of memory ICs of capacity 1k 4 required to construct memory of capacity 8k 8 are 16
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DAC ADC
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1
FSV = VR 1 * LSB = Voltage range / 2n
2
ste p size V R /2n 1 FS V
Resolution = = 1 = 100% * Resolution =
FS V V R 1 n 2n 1 2n 1
2
1 1 V
Accuracy = LSB = n +1 * uantisation error = 2nR %
2 2
Analog o/p = K. digital o/p
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Flash Type ADC : 2n1 comparators

2n resistors
2n n Encoder

Fastest ADC :-

Successive approximation ADC : n clk pulses

Counter type ADC : 2n - 1 clk pulses
Dual slope integrating type : 2n+1 clock pulses .

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Microprocessor

A Microprocessor includes ALU, register arrays and control circuits on a single chip.

Microcontroller:

A device that includes microprocessor, memory and input and output signal lines on
a single chip, fabricated using VLSI technology.

Architecture of 8085 Microprocessor

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8085 MPU:

8 bit general purpose microprocessor capable of addressing 64 K of memory.

It has 40 pins, requires a +5V single power supply and can operate with 3 MHz
single phase clock.

Accumulator: Is an 8 bit register that is used to perform arithmetic and logic

functions.

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Flag Register:

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

Carry Flag (CY): If an arithmetic operation result in a carry or borrow, the CY flag
is set, otherwise it is reset.

Parity Flag (P):

If the result has au even number of 1s, the flag is set, otherwise the flag is reset.

Auxiliary Carry (AC): In an arithmetic operation

If carry is generated by D 3 and passed to D 4 flag is set.
Otherwise it is reset.
Zero Flag (Z): Zero Flag is set to 1, when the result is zero otherwise it is reset.

Sign Flag (S): Sign Flag is set if bit D7 of the result is 1. Otherwise it is reset.

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Program counter (PC): It is used to store the l6 bit address of the next byte to be
fetched from the memory or address of the next instruction to be executed.

Stack Pointer (SP): It is 16 bit register used as a memory pointer. It points to memory
location in Read/Write memory which is called as stack.
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8085 Signals:
Address lines:

There are l6 address lines AD0 AD7 and A8 A15 to identify the memory
locations.
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In memory mapped I/O ; I/O Devices are treated as memory locations . You can connect max of
65536 devices in this technique .
In I/O mapped I/O , I/O devices are identified by separate 8-bit address . same address can be used
to identify i/p & o/p device .
Max of 256 i/p & 256 o/p devices can be connected .

Programmable Interfacing Devices :-

8155 programmable peripheral Interface with 256 bytes RAM & 16-bit counter
8255 Programmable Interface adaptor
8253 Programmable Interval timer
8251 programmable Communication interfacing Device (USART)
8257 Programmable DMA controller (4 channel)
8259 Programmable Interrupt controller
8272 Programmable floppy Disk controller
CRT controller
Key board & Display interfacing Device

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CALL & RET PUSH & POP

When CALL executes , p automatically stores * Programmer use PUSH to save the contents
16 bit address of instruction next to CALL on the rp on stack
Stack
CALL executed , SP decremented by 2 * PUSH executes SP decremented by 2 .
RET transfers contents of top 2 of SP to PC * same here but to specific rp .
RET executes SP incremented by 2 * same here

Rotate Instructions:

RLC :- Each bit shifted to adjacent left position . D7 becomes D0 .

CY flag modified according to D7

RAL :- Each bit shifted to adjacent left position . D7 becomes CY & CY becomes D0 .

ROC :-CY flag modified according D0

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RAR :- D0 becomes CY & CY becomes D7

CALL and Return Instructions

CALL 18T states SRRWW

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CC Call on carry 9 18 states
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CM Call on minus 9-18

CNC Call on no carry

CZ Call on Zero ; CNZ call on non zero

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CP Call on +ve

CPE Call on even parity

CPO Call on odd parity

RET : - 10 T

RC : - 6/ 12 T states
Jump Instructions

JMP 10 T JP Jump on Positive

JC Jump on Carry 7/10 T JM Jump on Minus

states JNC Jump on no carry JPE Jump on even parity

JZ Jump on zero JPO Jump on odd parity .

JNZ Jump on non zero

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PCHL : Move HL to PC 6T
PUSH : 12 T ; POP : 10 T
SHLD : address : store HL directly to address 16 T
SPHL : Move HL to SP 6T
STAX : R p store A in memory 7T
STC : set carry 4T
XCHG : exchange DE with HL 4T

XTHL :- Exchange stack with HL 16 T

For AND operation AY flag will be set & CY Reset

For CMP if A < Reg/mem : CY 1 & Z 0 (Nothing but A-B)
A > Reg/mem : CY 0 & Z 0

A = Reg/mem : Z 1 & CY 0 .
DAD Add HL + RP (10T) fetching , busidle , busidle
DCX , INX wont effect any flags . (6T)
DCR, INR effects all flags except carry flag . Cy wont be modified
LHLD load HL pair directly

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RST 12T states
SPHL , RZ, RNZ ., PUSH, PCHL, INX , DCX, CALL fetching has 6T states

PUSH 12 T ; POP 10T

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