ETA-1 Service PDF
ETA-1 Service PDF
SERVICE MANUAL
ADJUSTMENTS ..............................................................................................................4
CIRCUIT ADJUSTMENTS.....................................................................................................7
CHASSIS DESCRIPTION................................................................................................14
SERVICE DATA..........................................................................................................15
APPENDIX
CIRCUIT DIAGRAM
SERVICE MANUAL
SAFETY PRECAUTION
WARNING: REFER SERVICING TO QUALIFIED SERVICE PERSONNEL ONLY.
1. The TV has a nominal working EHT voltage. Extreme caution should be exercised when working
on the TV with the back removed.
1.1 Do not attempt to service this TV if you are not conversant with the precautions and procedures for
working on high voltage equipment.
1.2 When handling or working on the CRT, always discharge the anode to the TV chassis before
removing the anode cap in case of electric shock.
1.3 The CRT, if broken, will violently expel glass fragments. Use shatterproof goggles and take
extreme care while handling.
1.4 Do not hold the CRT by the neck as this is a very dangerous practice.
2. It is essential that to maintain the safety of the customer all power cord forms be replaced exactly
as supplied from factory.
3. Voltage exists between the hot and cold ground when the TV is in operation. Install a suitable
isolating transformer of beyond rated overall power when servicing or connecting any test
equipment for the sake of safety.
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4. When replacing ICs, use specific tools or a static-proof electric iron with small power (below 35W).
5. Do not use a magnetized screwdriver when tightening or loosing the deflection yoke assembly to
avoid electronic gun magnetized and decrement in convergence of the CRT.
6. When remounting the TV chassis, ensure that all guard devices, such as nonmetal control buttons,
switch, insulating sleeve, shielding cover, isolating resistors and capacitors, are installed on the
original place.
7. Replace blown fuses within the TV with the fuse specified in the parts list.
8. When replacing wires or components to terminals or tags, wind the leads around the terminal
before soldering. When replacing safety components identified by the international hazard symbols
on the circuit diagram and parts list, it must be the company-approved type and must be mounted
as the original.
9. Keep wires away from high temperature components.
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MAINTENANCE
1. Place the TV set on a stable stand or base that is of adequate size and strength to prevent it from
being accidentally tipped over, pushed off, or pulled off. Do not place the set near or over a
radiator or heat register, or where it is exposed to direct sunlight.
2. Do not install the TV set in a place exposed to rain, water, excessive dust, mechanical vibrations or
impacts.
3. Allow enough space (at least 10cm) between the TV and wall or enclosures for proper ventilation.
4. Slots and openings in the cabinet should never be blocked by clothes or other objects.
5. Please power off the TV set and disconnect it from the wall immediately if any abnormal condition
are met, such as bad smell, belching smoke, sparkling, abnormal sound, no picture/sound/raster.
Hold the plug firmly when disconnecting the power cord.
6. Unplug the TV set from the wall outlet before cleaning or polishing it. Use a dry soft cloth for
cleaning the exterior of the TV set or CRT screen. Do not use liquid cleaners or aerosol cleaners.
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ADJUSTMENTS
SET-UP ADJUSTMENTS
The following adjustments should be made when a complete realignment is required or a new picture
tube is installed.
Perform the adjustments in the following order:
1. Color purity
2. Convergence
3. White balance
Notes:
The purity/convergence magnet assembly and rubber wedges need mechanical positioning.
For some picture tubes, purity/ convergence adjustments are not required.
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Yok
Fig. 1
2. Convergence Adjustment
Preparation:
Before attempting any convergence adjustment, the TV should be operated for at least 15 minutes.
2.1 Center convergence adjustment
2.1.1 Receive dot pattern.
2.1.2 Adjust the brightness/contrast controls to obtain a sharp picture.
2.1.3 Adjust two tabs of the 4-pole magnet to change the angle between them and red and blue
vertical lines are superimposed each other on the center of the screen.
2.1.4 Turn both tabs at the same time keeping the angle constant to superimpose red and blue
horizontal on the center of the screen.
2.1.5 Adjust two tabs of the 6-pole magnet to superimpose red/blue line and green line.
2.1.6 Remember red and blue movement. Repeat steps 2.1.32.1.5 until optimal convergence is
obtained.
2.2 Circumference convergence adjustment
2.2.1 Loosen the clamp screw holding the deflection yoke assembly and allow it tilting.
2.2.2 Temporarily put the first wedge between the picture tube and deflection yoke assembly. Move
front of the deflection yoke up or down to obtain better convergence in circumference. Push the
mounted wedge in to fix the yoke temporarily.
2.2.3 Put the second wedge into bottom.
2.2.4 Move front of the deflection yoke to the left or right to obtain better convergence in
circumference.
2.2.5 Fix the deflection yoke position and put the third wedge in either upper space. Fasten the
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Fig. 2
Incline the Yoke Up (or Down) Incline the Yoke Right (or Left)
Fig.3
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CIRCUIT ADJUSTMENTS
Preparation:
Circuit adjustments should be made only after completion of set-up adjustments.
Circuit adjustments can be performed using the adjustable components inside the TV set. For TVs with
2
I C bus control, first change the bus data.
1. Degaussing
A degaussing coil is built inside the TV set. Each time the TV is powered on, the degaussing coil
will automatically degauss the TV. If the TV is magnetized by external strong magnetic field,
causing color spot on the screen, use a specific degausser to demagnetize the TV in the following
ways. Otherwise, color distortion will be shown on the screen.
1.1 Power on the TV set and operate it for at least 15 minutes.
1.2 Receive red full-field pattern.
1.3 Power on the specific degausser and face it to the TV screen.
1.4 Turn on the degausser. Slowly move it around the screen and slowly take it away from the TV.
1.5 Repeat the above steps until the TV is degaussed completely.
Note:
Its impossible to check the power part separately from the main chassis board as the part is
mounted on the main chassis board. The power components, etc. should be checked for
burnout when power-on. If burned out, do not power on the TV again until the cause is found
out.
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3. High Voltage Inspection
Measure voltages of test points on the main PCB with the digital voltmeter. Measure the CRT
high voltage with the high-voltage testing equipment and heater voltage with the high-frequency
effective voltmeter. The rated values are shown as below.
Table 2
Test Point Voltage (V)
Negative of VD461 261V
Negative of VD485 1905V
Heater 6.30.3Vrms
4. Focus Adjustment
Caution: Dangerously high voltages are present inside the TV. Extreme caution should be
exercised when working on the TV with the back removed.
4.1 After removing the back cover, look for the FBT on the main PCB. There should be a FCB on
the FBT.
4.2 Power on the TV and preheat it for 15 min.
4.3 Receive a normal TV signal. Rotate knob of the FCB until you get a sharp picture.
Fig. 4
5. Safety Inspection
5.1 Inspection for insulation and voltage-resistant
Perform safety test for all naked metal of the TV. Supply high voltage of 3000V AC, 50Hz (limit
current of 10mA) between all naked metal and cold ground. Test every point for 3 sec. and
ensure no arcing and sparking.
5.2 Requirements for insulation resistance
Measure resistance between naked metal of the TV and feed end of the power cord to be
infinity with a DC-500 high resistance meter and insulation resistance between the naked metal and
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degaussing coil to be over 20M.
6. SERVICE mode
Set the volume to 0. Then press and hold the MUTE button on the remote control, and press the
MENU button on the TV to enter the SERVICE mode. In this case, red s is displayed on the
upper center of the screen. To exit from the S mode, turn off the TV set by the POWER button
Caution: The user service mode adjustment can be changed only when service personnel adjust
the whole set data during servicing. As the control data have dramatic effects on functions and
performance of the TV, service personnel should not tell user how to enter the SERVICE mode
(continued)
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LOGO1COLOR OPT
LOGO2COLOR OPT
LOGO1LINE OPT
LOGO2LINE OPT
PAGE18
LOGO1SIZE OPT
LOGO2SIZE OPT
LG1 OPT
LG2 OPT
Notes:
The data sheet may differ dependent on different models.
The data sheet may differ dependent on different CRTs for the same model.
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IR KEY
Video
Amplifier
Circuit Amplifier
AVIN
AVIN
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2. CHASSIS DESCRIPTION
General Description
ETA-1 chassis is applied in SF21GA63 series.
By use of Toshiba V/C/D-MCU 2IN1 IC for TV small signal processing and bus control,
the chassis enables TV tuning, adjustment, control and picture correction, featuring
high-integration, high-performance-to-price ratio and high-reliability and compact circuit
with fewer external components. The chassis, widely used in small and medium TVs,
provides much more convenience for manufacturing and technical service. It includes:
2IN1 IC TMPA8873PSANG-4VB6 for PAL/NTSC small signal processing and bus control
EEPROM AT24C16 for data memory
LA78040 for vertical output power amplifying
TFA9842AJ for audio power amplifying
Thick-film IC STR-G5653 for power circuit adjustment and control
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SERVICE DATA
TECHNICAL DATA OF KEY ICS
1.MCU and Signal Processor for a PAL/NTSC TV
TMPA8873CMANG /CPANG/CRANG /CSANG
1.General Description
The TMPA8873CPANG is an integrated circuit for a PAL/NTSC TV. A MCU and a TV signal processor are
integrated in a 64-pin shrink DIP package. The MCU contains 8-bit CPU, ROM, RAM, I/O ports,
timer/counters, A/D converters, an on-screen display controller, remote control interfaces, IIC bus interfaces
and the Closed Caption decoder. The TV signal processor contains PIF, SIF, Video, multi-standard chroma,
Sync, RGB processors.
Mask ROM: TMPA8873CMANG (ROM size: 32k)
Mask ROM: TMPA8873CPANG (ROM size: 48k)
Mask ROM: TMPA8873CRANG (ROM size: 56k)
Mask ROM: TMPA8873CSANG (ROM size: 64k)
OTP ROM: TMPA8873PSANG (ROM size: 64k)
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2.Features
TV Processor
IF RGB/Base-Band
Integrated PIF VCO aligned automatically Integrated 1 H base-band delay line
Negative demodulation PIF Base-band TINT control
Multi-frequency SIF demodulator without external Internal OSD interface
Tank-coil Half-tone and transparent for OSD
SIF BPF built-in External YCbCr interface for DVD
SIF Trap filter built in RGB cut-off/drive controls by bus
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3.Block Diagram
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4.Basic Structure
1. Internal Connections
TMPA8873 has two pieces of IC chip in one package, using Multi-Chip-Package (MCP) technology.
One is a micro controller (MCU) and the other one is a signal processor (SP) for a color TV. There
are some internal connections between these two ICs for handling below signals.
8 C-Video S to M Composite video signal from internal video switch, for CCD
Functions of SP from MCU are controllable through the IIC bus of the internal connections.
2. Power Supply
TMPA8873 has some power supplies and GND pins. Power supplies related MCU must be applied at
the first. Power supplies for H.VCC and TV D.VCC are the second with at least 100 ms delay after
MCU power ON. The other power supplies are the last, which are recommended to be supplied from a
regulator circuit using FBP.
3. Crystal Resonator
TMPA8873 requires only one crystal resonator, in stead that a conventional two-chip solution
requires two resonators at least, one for MCU and the other one for SP. An oscillation clock with the
crystal resonator of TMPA8873 is supplied for MCU operation, PIF VCO automatic alignment,
alignment free AFT, chroma demodulation and horizontal oscillation. The oscillation frequency is
very important so that those of functions work properly, so that designing the oscillation frequency
accurately is required. The spec of crystal is recommended to be within
fosc: 8 MHz +/20 ppm
ftemp: 8 MHz +/40 ppm (20C to +65C)
While RESET of MCU is active, the MCU function stops. Hardware and software initialization
sequence including power supplies control is required, because status of any hardware after the
RESET period is unknown especially horizontal oscillator which is a very basic timing generator of SP
operation.
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5.TERMINAL INTERFACE
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SIGNAL PROCESSOR BLOCK
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Microcontrollers Descriptions (MROM version: TMPA8873CMANG /CPANG /CRANG /CSANG)
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2. TFA9842AJ
2-channel audio amplifier with volume control (SE: 1 W to 7.5 W)
1. General description
The TFA9842AJ contains two identical audio power amplifiers. The TFA9842AJ can be used as two
Single-Ended (SE) channels with a volume control. The maximum gain is 26 dB.
The TFA9842AJ comes in a 9-pin DIL-bent-SIL (DBS9P) power package. The TFA9842AJ is pin compatible
with the TFA9843AJ, TFA9843(B)J, TFA9842(B)J and TFA9841J. The difference between the TFA9843AJ
and the TFA9843(B)J,TFA9842(B)J, TFA9841J is the functionality of pin 7. The TFA9843AJ has a Volume
Control (VC) on pin 7. The TFA9843(B)J, TFA9842(B)J and TFA9841J have a mode select (Mode) on pin 7.
The TFA9842AJ contains a unique protection circuit that is solely based on multiple temperature
measurements inside the chip. This gives maximum output power for all supply voltages and load conditions
with no unnecessary audio holes. Almost any supply voltage and load impedance combination can be made
as long as thermal boundary conditions (number of channels used, external heatsink and ambient
temperature) allow it.
2. Features
2 Channel SE: 1 W to 7.5 W operation possibility
Soft clipping
Input clamps
Volume control
Standby and mute mode
No on/off switching plops
Low standby current
High supply voltage ripple rejection
Outputs short-circuit protected to ground, supply and across the load
Thermally protected
Pin compatible with the TFA9843AJ, TFA9843(B)J, TFA9842(B)J, TFA9841J.
3. Applications
CRT TV, LCD TV
Monitors
PC speakers
Boom box
Mini and micro audio receivers.
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3. Block diagram
4. Pinning information
4.1 Pinning
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5. EEPROM AT24C04/08/16
1) Features
Low-voltage and Standard-voltage Operation
-2.7 (Vcc=2.7V to 5.5V)
-1.8 (Vcc=1.8V to 5.5V)
Internally Organized 128x8(1K), 256x8 (2K), 512x8 (4K),
1024x8 (8K) or 2048x8 (16K)
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
100kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Partial Page Writes are Allowed
Self-timed Write Cycle (10 ms max)
High-reliability
-Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP Package
2-wire
Serial EEPROM
AT24C01A 1K (128 x 8)
AT24C02 2K (256 x 8)
AT24C04 4K (512 x 8)
AT24C08 8K (1024 x 8)
AT24C16 6K (2048 x 8)
2) Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable
and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications where low-power
and low-voltage operations are essential. The AT24C01A/02/04/08/16 is available in space-saving
8-pin PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
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3) Pin Configuration
Table 12 8-lead MAP
8-lead TSSOP
Pin Name Function
A0-A2 Address Inputs A0 1 8 VCC VCC 1 8 A0
Fig. 14
8-pin PDIP
8-lead SOIC
A0 1 8 VCC
8
A0 1 VCC
A1 2 7 WP
7
A1 2 WP
A2 3 6 SCL
6
A2 3 SCL
GND 4 5 SDA
5
GND 4 SDA
Fig. 15
4) Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device
and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed
on a single bus system (device addressing is discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may
be addressed on a single bus system. The A0 pin is a no connect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be
addressed on a single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the device address pins, which limits the number of devices on a single bus
to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data
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protection. The Write Protect pin allows normal read/write operations when connected to ground (GND).
When the Write Protect pin is connected to Vcc, the write protection feature is enabled and operates as
shown in table 14.
Table 13
WP Pin Part of the Array Protected
Status 24C01A 24C02 24C04 24C08 24C16
At Vcc Full (1K) Full (2K) Full (4K) Normal Upper
Array Array Array Read/ Half
Write (8K)
Operation Array
At GND Normal Read/Write Operations
5) Memory Organization
AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires
a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires
an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires
a 9-bit data word address for random word addressing.
AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires
a 10-bit data word address for random word addressing.
AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word addressing.
6) Block Diagram
Fig.16
7) Refer to Table 21 about Functions and Data of the ICs Pins.
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Fig.18
3) Function of Terminal
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protection. The Write Protect pin allows normal read/write operations when connected to ground (GND).
When the Write Protect pin is connected to Vcc, the write protection feature is enabled and operates as
shown in table 14.
Table 13
WP Pin Part of the Array Protected
Status 24C01A 24C02 24C04 24C08 24C16
At Vcc Full (1K) Full (2K) Full (4K) Normal Upper
Array Array Array Read/ Half
Write (8K)
Operation Array
At GND Normal Read/Write Operations
5) Memory Organization
AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires
a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires
an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires
a 9-bit data word address for random word addressing.
AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires
a 10-bit data word address for random word addressing.
AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word addressing.
6) Block Diagram
Fig.16
7) Refer to Table 21 about Functions and Data of the ICs Pins.
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Pin No 1 2 3 4 5 6
Pin No 7 8 9 10 11 12
Pin No 13 14 15 16 17 18
Pin No 19 20 21 22 23 24
Pin No 25 26 27 28 29 30
Pin No 31 32 33 34 35 36
Pin No 37 38 39 40 41 42
Pin No 43 44 45 46 47 48
Pin No 49 50 51 52 53 54
Pin No 55 56 57 58 59 60
Resistance - - - - - >2000 K
Pin No 61 62 63 64
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Pin No 1 2 3 4 5 6
Pin No 7 8 9 10 11 12
Pin No 13 14 15 16 17 18
Pin No 19 20 21 22 23 24
Pin No 25 26 27 28 29 30
Pin No 31 32 33 34 35 36
Pin No 37 38 39 40 41 42
Pin No 43 44 45 46 47 48
Pin No 49 50 51 52 53 54
Pin No 55 56 57 58 59 60
Pin No 61 62 63 64
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Digital Multimeter
Pin
Symbol Functions Description Reference Positive Resistance(20K
No.
Voltage(V) )
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Table 21 Functions and Service Data of AT24C08/16 Pins
Digital Multimeter
Pin No. Function Description Reference Voltage Positive Negative Resistance
(V) Resistance (20K)
(20K)
1 Address input 0 0 0
2 Address input 0 0 0
3 Address input 0 0 0
4 Common ground 0 0 0
7 PW write protect 0 0 0
Digital Multimeter
Pin
Functions Description
No. Reference Voltage Positive Resistance (20K Negative Resistance
(V) ) (20K)
3 Ground terminal 0 0 0
Overcurrent/Freedback
5 1.85 0.68 0.68
terminal
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1. Any components identified by have special safety-related characteristics.
Use replacement Which have the same characteristics as original parts.
2. Cold ground Hot ground
This circuit diagram is only for reference, specifications are subject to change without reference. Circuit Diagram FOR SF21GA63