VHDL BASICS

BY:
Varun Tiwari
VNIT, Nagpur

9/21/2015 Varun Tiwari 1

 Evolution of VLSI System
Sr. Technology Year
No.
1. Transistors 1950s

2. Integrated Circuits 1960s

3. Microprocessors/Microcontrollers 1970s

4. Digital Signal Processors 1980s

5. FPGAs/ASICs 1990s
6. System on Chip 2000s

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 History of VHDL
1981: Initiated in 1981 by US DoD to address the hardware
life-cycle crisis
1983-85: Development of baseline language by Intermetrics,
IBM and TI
1986: All rights transferred to IEEE
1987: Publication of IEEE Standard
1987: Mil Std 454 requires comprehensive VHDL descriptions
to be delivered with ASICs
1994: Revised standard (named VHDL 1076-1993)
2000: Revised standard (named VHDL 1076 2000, Edition)
2002: Revised standard (named VHDL 1076-2002)
2009: Revised Standard (named VHDL 1076-2008)

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 VHDL
VHSIC Hardware
Description Language
--------------------------------------

VHSIC --
Very High Speed Integrated Circuits

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 Introduction
VHDL is a programming language that allows
one to model and develop complex digital
systems in a dynamic environment.

Allows you to designate in/out ports (bits) and

specify behavior or response of the system.

It is based on ADA language, and Verilog(another

hardware description language) is based on C.

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 VHDL Modeling
VHDL is for coding models of a digital system.
Reasons for modeling
requirements specification
documentation
testing using simulation
formal verification
synthesis
Goal
most reliable design process, with minimum cost and
time
avoid design errors!
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 Basic Concepts
Interfaces -- i.e. ports
Behavior
Structure
Test Benches
Analysis, simulation
Synthesis

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 Modeling Style
Dataflow
Behavioral
Structural

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 Dataflow Modeling
uses statements that defines the actual flow of
data.....
such as,
x <= y -- this is NOT less than equal to

this assigns the boolean signal x to the value of

boolean signal y... i.e. x = y
this will occur whenever y changes....

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 Behavioral Modeling
Architecture body
describes an implementation of an entity
may be several per entity
Behavioral architecture
describes the algorithm performed by the module
contains
process statements, each containing
sequential statements, including
signal assignment statements and
wait statements

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 Structural Modeling
Structural architecture
implements the module as a composition of
subsystems
contains
signal declarations, for internal interconnections
the entity ports are also treated as signals
component instances
instances of previously declared entity/architecture pairs
port maps in component instances
connect signals to component ports

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 Mixed Modeling
An architecture can contain both behavioral
and structural parts and it can be called as
mixed modeling.
process statements and component instances
collectively called concurrent statements
processes can read and assign to signals

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 Test Bench
Testing a design by simulation
Use a test bench model
a Model that uses your Model
apply test sequences to your inputs
monitors values on output signals
either using simulator
or with a process that verifies correct operation
or logic analyzer

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 Basic VHDL Model
A digital system in VHDL consists of a design entity that can contain other
entities that are then considered components of the top-level entity. Each
entity is modeled by an entity declaration and an architecture body. One
can consider the entity declaration as the interface to the outside world
that defines the input and output signals, while the architecture body
contains the description of the entity and is composed of interconnected
entities, processes and components, all operating concurrently. In a typical
design there will be many such entities connected together to perform the
desired function.

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 To remember
VHDL uses reserved keywords that cannot be used as signal names or
identifiers.

Keywords and user-defined identifiers are case insensitive.

Lines with comments start with two adjacent hyphens (--) and will be
ignored by the compiler.

VHDL ignores line breaks and extra spaces.

VHDL is a strongly typed language which implies that one has always to
declare the type of every object that can have a value, such as signals,
constants and variables.

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 Entity
The entity declaration defines the NAME of
the entity and lists the input and output ports.
The general form is as follows,

entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;

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 Entity(Cont..)
NAME_OF_ENTITY is a user-selected identifier
signal_names are user-selected identifiers that specify
external interface signals.
mode: is one of the reserved words to indicate the
signal direction:
in indicates that the signal is an input
out indicates that the signal is an output of the entity
whose value can only be read by other entities.
buffer indicates that the signal is an output of the entity
whose value can be read inside the entitys architecture.
inout the signal can be an input or an output.

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 Entity(Cont..)
type: a built-in or user-defined signal type. Examples of
types are bit, bit_vector, Boolean, character, std_logic, and
std_ulogic.

bit can have the value 0 and 1

bit_vector is a vector of bit values (e.g. bit_vector (0 to 7)
std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can
have 9 values to indicate the value and strength of a signal.
boolean can have the value TRUE and FALSE
integer can have a range of integer values
real can have a range of real values
character any printing character
time to indicate time

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 Entity(Cont..)
Example:

entity adder is
port (a, b : in bit_vector(0 to 1);
sum : out bit_vector(0 to 1);
carry : out bit );
end adder;

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 Architecture
The architecture body specifies how the circuit operates and how it is
implemented.
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
:
end architecture_name;

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 Architecture(Cont..)
Example adder:
entity adder is
port (a, b : in bit;
sum, carry : out bit );
end adder;

architecture adder_arch of adder is

begin
sum <= a xor b;
carry <= a and b;
end adder_arch;

NOTE: The statements are concurrent statements.

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 Library and Packages
A library can be considered as a place where the compiler stores
information about a design project. A VHDL package is a file or
module that contains declarations of commonly used objects, data
type, component declarations, signal, procedures and functions
that can be shared among different VHDL models.

Ex. For using std_logic one has specify the library and package and
this done at beginning.

library ieee;
use ieee.std_logic_1164.all;

The .all extension indicates to use all of the ieee.std_logic_1164

package.

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 Library and Packages(Cont..)
std_logic_1164 package: defines the standard data types.

std_logic_arith package: provides arithmetic, conversion and comparison

functions for the signed, unsigned, integer, std_ulogic, std_logic and
std_logic_vector types.

std_logic_unsigned package: this package extends the std_logic_arith

library to handle std_logic_vector values as unsigned integers.

std_logic_misc package: defines supplemental types, subtypes, constants

and functions for the std_logic_1164 package.
To use any of these one must include the library and use clause:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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 Example ADDER
library ieee;
use ieee.std_logic_1164.all;

entity adder is
port (a, b : in std_logic;
sum, carry : out std_logic);
end adder;

architecture adder_arch of adder is

begin
sum <= a xor b;
carry <= a and b;
end adder_arch;
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 References
1. http://en.wikipedia.org/wiki/Ada_(programming_la
nguage)
2. A VHDL Primer 3rd Edition by-Bhaskar, J. ISBN: 978-
81-203-2366-7
3. VHDL: Programming by Example 4th Edition by-
Douglas L. Perry, ISBN-13: 978-0071400701

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