Siliconsmart Ds
Siliconsmart Ds
SiliconSmart
A Smarter Way to Get PrimeTime Signoff-Quality Timing Models
Overview Introduction
Accurate library characterization The SiliconSmart solution includes a comprehensive array of library characterization
is the foundation of successful and QA capabilities that are tuned to produce PrimeTime sign-off quality libraries
with maximum throughput on available compute resources. SiliconSmarts
digital implementation. Synthesis,
innovative technologies utilize embedded gold reference SPICE engines to provide
place-and-route, verification a characterization speed up of advanced Liberty models used by PrimeTime static
and signoff tools rely on precise timing analysis (STA) to accurately account for effects seen in ultra-low voltage
model libraries to accurately FinFET processes that impact timing. This includes PrimeTime parametric on-chip
represent the timing, noise and variation (POCV), advanced waveform propagation (AWP) and electromigration
power performance of digital (EM) analysis.
SPICE Reference
Netlist Library
Validation
IBIS Reports
AOCV/
POCV LVF Datasheet
Liberty Timing,
Noise & Power
Verilog
SiliconSmart ADV
SiliconSmart ADV provides additional features for advanced node cell libraries.
Comprehensive Liberty Variation Format (LVF) characterization and modeling capabilities enable best-in-class
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PrimeTime POCV variation analysis. Smart LVF performance optimization technology provides highest
throughput and accuracy.
Support for the latest Liberty EM model extensions are included for cell-level EM characterization.
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A suite of tools to accelerate the manual and error-prone QA process for sign-off quality libraries is provided.
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The entire library qualification process is automatically parallelized to provide quick turnaround time and
identify problems early on. Visualization aids and intelligently organized results help to quickly isolate
problem areas and provide QA management metrics.
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Memory Characterization
The SiliconSmart memory characterization solution provides accurate memory instance re-characterization
using a simulation-based approach. Dynamic simulator-based netlist reduction eliminates inactive portions
of the memory netlist to speed up simulation without compromising accuracy. It provides ease of setup using
internal node identification and templates for memory function description. Memory re-characterization
applications include embedded SRAM, register file and ROM. User-defined customization is available for
special applications.
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02/02/16.PS CS6888_SiliconSmartDS.