SN54/74LS122

SN54/74LS123
RETRIGGERABLE MONOSTABLE
MULTIVIBRATORS
These dc triggered multivibrators feature pulse width control by three meth- RETRIGGERABLE MONOSTABLE
ods. The basic pulse width is programmed by selection of external resistance
MULTIVIBRATORS
and capacitance values. The LS122 has an internal timing resistor that allows
the circuits to be used with only an external capacitor. Once triggered, the ba- LOW POWER SCHOTTKY
sic pulse width may be extended by retriggering the gated low-level-active (A)
or high-level-active (B) inputs, or be reduced by use of the overriding clear.
Overriding Clear Terminates Output Pulse
Compensated for VCC and Temperature Variations
DC Triggered from Active-High or Active-Low Gated Logic Inputs
Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle J SUFFIX
CERAMIC
Internal Timing Resistors on LS122 CASE 620-09
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NOTES: ORDERING INFORMATION

1. An external timing capacitor may be connected between Cext and Rext/Cext (positive).
2. To use the internal timing resistor of the LS122, connect Rint to VCC. SN54LSXXXJ Ceramic
3. For improved pulse width accuracy connect an external resistor between Rext/Cext and SN74LSXXXN Plastic
VCC with Rint open-circuited. SN74LSXXXD SOIC
4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext
and VCC.

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 SN54/74LS122 SN54/74LS123

LS122 LS123
FUNCTIONAL TABLE FUNCTIONAL TABLE
INPUTS OUTPUTS INPUTS OUTPUTS
CLEAR A1 A2 B1 B2 Q Q CLEAR A B Q Q
L X X X X L H L X X L H
X H H X X L H X H X L H
X X X L X L H X X L L H
X X X X L L H H L
H L X H H H
H L X H L H
H X L H
H X L H
H H H H
H H H
H H H H
L X H H
X L H H

TYPICAL APPLICATION DATA

The output pulse tW is a function of the external compo- separate power supplies are used for VCC and VRC. If VCC is
nents, Cext and Rext or Cext and Rint on the LS122. For values tied to VRC, Figure 7 shows how K will vary with VCC and
of Cext 1000 pF, the output pulse at VCC = 5.0 V and VRC = temperature. Remember, the changes in Rext and Cext with
5.0 V (see Figures 1, 2, and 3) is given by temperature are not calculated and included in the graph.
tW = K Rext Cext where K is nominally 0.45 As long as Cext 1000 pF and 5K Rext 260K
(SN74LS122 / 123) or 5K Rext 160 K (SN54LS122 / 123),
If Cext is on pF and Rext is in k then tW is in nanoseconds.
the change in K with respect to Rext is negligible.
The Cext terminal of the LS122 and LS123 is an internal
If Cext 1000 pF the graph shown on Figure 8 can be used
connection to ground, however for the best system perfor-
to determine the output pulse width. Figure 9 shows how K will
mance Cext should be hard-wired to ground.
change for Cext 1000 pF if VCC and VRC are connected to the
Care should be taken to keep Rext and Cext as close to the
same power supply. The pulse width tW in nanoseconds is
monostable as possible with a minimum amount of inductance
approximated by
between the Rext/Cext junction and the Rext/Cext pin. Good
groundplane and adequate bypassing should be designed tW = 6 + 0.05 Cext (pF) + 0.45 Rext (k) Cext + 11.6 Rext
into the system for optimum performance to insure that no
false triggering occurs. In order to trim the output pulse width, it is necessary to
It should be noted that the Cext pin is internally connected include a variable resistor between VCC and the Rext/Cext pin
to ground on the LS122 and LS123, but not on the LS221. or between VCC and the Rext pin of the LS122. Figure 10, 11,
Therefore, if Cext is hard-wired externally to ground, substitu- and 12 show how this can be done. Rext remote should be kept
tion of a LS221 onto a LS123 socket will cause the LS221 to as close to the monostable as possible.
become non-functional. Retriggering of the part, as shown in Figure 3, must not
The switching diode is not needed for electrolytic capaci- occur before Cext is discharged or the retrigger pulse will not
tance application and should not be used on the LS122 and have any effect. The discharge time of Cext in nanoseconds is
LS123. guaranteed to be less than 0.22 Cext (pF) and is typically 0.05
To find the value of K for Cext 1000 pF, refer to Figure 4. Cext (pF).
Variations on VCC or VRC can cause the value of K to change, For the smallest possible deviation in output pulse widths
as can the temperature of the LS123, LS122. Figures 5 and from various devices, it is suggested that Cext be kept
6 show the behavior of the circuit shown in Figures 1 and 2 if 1000 pF.

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 SN54/74LS122 SN54/74LS123

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 55 25 125 C
74 0 25 70
IOH Output Current High 54, 74 0.4 mA
IOL Output Current Low 54 4.0 mA
74 8.0
Rext External Timing Resistance 54 5.0 180 k
74 5.0 260
Cext External Capacitance 54, 74 No Restriction
Rext / Cext Wiring Capacitance at Rext / Cext Terminal 54, 74 50 pF

WAVEFORMS

 

   

  

 

  
  

EXTENDING PULSE WIDTH

  

    

 
  

 

OVERRIDING THE OUTPUT PULSE

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 SN54/74LS122 SN54/74LS123

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage 0.65 1.5 V VCC = MIN, IIN = 18 mA
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

20 A VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) 20 100 mA VCC = MAX
LS122 11
ICC Power Supply Current mA VCC = MAX
LS123 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions

tPLH Propagation Delay, A to Q 23 33

ns
tPHL Propagation Delay, A to Q 32 45 Cext = 0
23 44 CL = 15 pF
tPLH Propagation Delay, B to Q
ns
tPHL Propagation Delay, B to Q 34 56 Rext = 5.0 k
28 45 RL = 2.0 k
tPLH Propagation Delay, Clear to Q
ns
tPHL Propagation Delay, Clear to Q 20 27
tW min A or B to Q 116 200 ns Cext = 1000 pF, Rext = 10 k,
tWQ A to B to Q 4.0 4.5 5.0 s CL = 15 pF, RL = 2.0 k

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tW Pulse Width 40 ns

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Figure 10. LS123 Remote Trimming Circuit

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 SN54/74LS122 SN54/74LS123



 


 

 



 

Figure 11. LS122 Remote Trimming Circuit Without Rext






 

 

 

Figure 12. LS122 Remote Trimming Circuit with Rint

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