Complex Programmable Logic Device (CPLD):

CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then
in three additional series, called MAX 5000, MAX 7000 and MAX 9000. The CPLD is the
complex programmable Logic Device which is more complex than the SPLD. This is build on
SPLD architecture and creates a much larger design. Consequently, the SPLD can be used to
integrate the functions of a number of discrete digital ICs into a single device and the CPLD can
be used to integrate the functions of a number of SPLDs into a single device.
So, the CPLD architecture is based on a small number of logic blocks and a global
programmable interconnect. Instead of relying on a programming unit to configure chip , it is
advantageous to be able to perform the programming while the chip is still attached to its circuit
board. This method of programming is known is called In-System programming (ISP). It is not
usually provided for PLAs (or) PALs , but it is available for the more sophisticated chips known
as Complex programmable logic device.

The CPLD consists of a number of logic blocks or functional blocks, each of which contains a
macrocell and either a PLA or PAL circuit arrangement. In this view, eight logic blocks are
shown. The building block of the CPLD is the macro-cell, which contains logic implementing
disjunctive normal form expressions and more specialized logic operations. The macro cell
provides additional circuitry to accommodate registered or nonregistered outputs, along with
signal polarity control. Polarity control provides an output that is a true signal or a complement
of the true signal. The actual number of logic blocks within a CPLD varies; the more logic
blocks available, the larger the design that can be configured.

In the center of the design is a global programmable interconnect. This interconnect allows
connections to the logic block macrocells and the I/O cell arrays (the digital I/O cells of the
CPLD connecting to the pins of the CPLD package).The programmable interconnect is usually

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based on either array-based interconnect or multiplexer-based interconnect: Array-based
interconnect allows any signal within the programmable interconnect to connect to any logic
block within the CPLD.

This is achieved by allowing horizontal and vertical routing within the programmable
interconnect and allowing the crossover points to be connected or unconnected (the same idea as
with the PLA and PAL), depending on the CPLD configuration.
Multiplexer-based interconnect uses digital multiplexers connected to each of the macrocell
inputs within the logic blocks. Specific signals within the programmable interconnect are
connected to specific inputs of the multiplexers. It would not be practical to connect all internal
signals within the programmable interconnect to the inputs of all multiplexers due to size
and speed of operation considerations.

FPGAs FIELD PROGRAMMABLE GATE ARRAYS

The FPGA concept emerged in 1985 with the XC2064TM FPGA family from Xilinx . The
FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that
can be viewed as standard components. The individual cells are interconnected by a matrix of
wires and programmable switches. A user's design is implemented by specifying the simple

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logic function for each cell and selectively closing the switches in the interconnect matrix. The
array of logic cells and interconnect form a fabric of basic building blocks for logic circuits.
Complex designs are created by combining these basic blocks to create the desired circuit.

Unlike CPLDs (Complex Programmable Logic Devices) FPGAs contain neither AND nor OR
planes.The FPGA architecture consists of configurable logic blocks, configurable I/O blocks,
and programmable interconnect. Also, there will be clock circuitry for driving the clock signals
to each logic block, and additional logic resources such as ALUs, memory, and decoders may be
available. The two basic types of programmable elements for an FPGA are Static RAM and anti-
fuses.
Each logic block in an FPGA has a small number of inputs and one output. A look
up table (LUT) is the most commonly used type of logic block used within FPGAs.
There are two types of FPGAs.(i) SRAM based FPGAs and (ii) Antifuse technology based(OTP)

Every FPGA consists of the following elements

Configurable logic blocks(CLBs)

Configurable input output blocks(IOBs)
Two layer metal network of vertical and horizontal lines for interconnecting the CLBS
Configurable logic blocks(CLBs):
The configurable logic block is the basic logic cell and it is either RAM based or PLD based .
It consists of registers (memory), Muxes and combinatorial functional unit. An array of CLBS
are embedded within a set of vertical and horizontal channels that contain routing which can be
personalized to interconnect CLBs.

Configurable Input / Output logic locks (IOBs):

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 CLBs and routing channels are surrounded by a set of programmable I/Os which is
an arrangement of transistors for configurable I/O drivers.
Programmable interconnects:
These are un programmed interconnection resources on the chip which have
channeled routing with fuse links. Four types of interconnect architectures are available. They
are
Row-Column Architecture
Island Style Architecture
Sea-of-Gates Architecture
Advantages of FPGAs:

Design cycle is significantly reduced. A user can program an FPGA design in a few
minutes or seconds rather than weeks or months required for mask programmed parts.
High gate density i.e, it offers large gate counts.
No custom masks tooling is required (Low cost).
Low risk and highly flexible.
Reprogram ability for some FPGAs (design can be altered easily).
Suitable for prototyping.
Parallelism

Allows for system-level extraction of parallelism to match input data
at design time
Huge computational capability
Fast development and Dynamic reconfiguration
Updating new pattern matching rules (or simply rules)
Device should not stop when updating new rules
Update time for new rules
To provide fast response to new attacks, the compilation and updating
time for new rules needs to be short

In case of a hardwired FPGA architecture, the update time is mostly dependent

on place & route time
Memory-based units can provide near instantaneous updates
Limitations:

Speed is comparatively less.

The circuit delay depends on the performance of the design implementation tools.

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 The mapping of the logic design into FPGA architecture requires sophisticated design
implementation (CAD) tools than PLDs.
FPGA Programming Technologies:
(a) Antifuse Technology:
An antifuse is a two terminal device that when un-programmed has a very high resistance
between the two terminals and when programmed, or blown, creates a very low resistance or
permanent connection. The application of a high voltage from 11 V to 21 V will create the low
resistive permanent connection. Antifuse technologies come in two types. The first is oxide-
nitride-oxide (ONO) dielectric based and the other is amorphous silicon or metal-to-metal
antifuse structures.
Dielectric based antifuses consist of a dielectric material between N+ diffusion and polysilicon
which breaks down when a high voltage is applied. Early dielectrics were a single-layered oxide
dielectric until Actel came out with the programmable low impedance circuit element (PLICE),
which is a multi-layer oxide-nitride-oxide (ONO) dielectric fuse. A high voltage across the
PLICE melts the dielectric and creates polycrystalline silicon between the terminals. When the
PLICE is blown, it adds three layers rather than the double metal CMOS process. The layers are
a thin layer of oxide an top off the N+ surface, Low-pressure Chemical Vapor Deposition
(LPCVD) nitride and the reoxidized top oxide. The programming current has an important effect
because the higher the current during programming, the lower the link resistance, resulting in
smaller thickness for the antifuse material. Programming circuits for antifuses need to supply
high currents (15 ma for Actel) to insure high reliability and performance.
Amorphous silicon antifuse technology is the alternative to dielectric antifuse. It consists of
amorphous silicon between two layers of metal that changes phases when current is applied.
When the antifuse is not programmed the amorphous silicon has a resistance of 1 Giga ohm.
When a high current (about 20 mA) is applied to the anitfuse the amorphous silicon changes into
a conductive polysilicon link. Quick Logic pASIC FPGA is a perfect example of an amorphous
silicon antifuse technology.
(b). SRAM-based Technology:
SRAM FPGA architecture consists of static RAM cells to control pass gates or multiplexers.
The FPGA speed is determined by the delay introduced by the logic cells and the routing
channels. Multiplexers, look-up tables and output drivers affect the speed of signals through the
logic cells. An FPGA with more PIPs is easier to route but introducing more routing delay. The
size of the look-up table plays an important role depending on the design. Smaller LUTs provide
higher density but larger ones are preferred for high-speed applications.

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Distinguish between SRAM and Antifuse Technologies: The following points explains the
differences between the two technologies.
1. Antifuse programming technology is faster than SRAM programming technology due to the
RC delays introduced by the interconnect structure.
2. Antifuse technology has more silicon area per gate and is easier to route than SRAM
technology.
3. A disadvantage of antifuse FPGA is that they require more process layers and mask steps and
also contain high voltage programming transistors.
4. SRAM-based technology contains higher capacity than antifuse technologies.
5. SRAM based technology is very flexible with in-system programmability and the ability to
reconfigure the design during the debugging stage while antifuse technology is one-time
programmable (OTP). This ability reduces design and development, which reduces overall
cost of the design. Another advantage to this is that SRAM technology can be programmed at
the factory through complete verification test where the antifuse are tested as blanks and
require programming by the user to verify design requirements and operation.
6. A disadvantage of SRAM technology is that it is volatile meaning it has to be reprogrammed
every time power is turned off and on again. The SRAM usually require an extra memory
element to program the chip which occupies board space .
Alteras FLEX 10K Series CPLDs
Alteras FLEX 10K devices are the industrys first embedded PLDs. Based on reconfigurable
CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates
all features necessary to implement common gate array mega functions. With 10,000 to 250,000
typical gates ,the FLEX 10K family provides the density, speed, and features to integrate entire
systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable .So, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer need not manage inventories of different
ASIC designs; FLEX 10K devices can be configured on the board for the specific functionality
required.
Each FLEX 10K device contains an Embedded Array (EA) and a Logic Array (LA).
The Embedded Array is used to implement a variety of memory functions or complex logic
functions, such as digital signal processing (DSP) ,microcontroller, wide-data-path manipulation,
and data-transformation functions.

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The Logic Array performs the same function as the sea-of-gates in the gate array: it is used to
implement general logic, such as counters, adders, state machines, and multiplexers.
The combination of embedded and logic arrays provides the high performance and high density
of embedded gate arrays, enabling designers to implement an entire system on a single device.
FLEX 10K devices are configured at system power-up with data stored in an Altera serial
configuration device or provided by a system controller.
Logic Element is , the smallest unit of logic in the FLEX 10K architecture, has a compact size
that provides efficient logic utilization. Each LE contains a four-input LUT, which is a function
generator that can quickly compute any function of four variables. In addition, each LE contains
a programmable flip flop with a synchronous enable, a carry chain, and a cascade chain. Each LE
drives both the local and the Fast Track. The programmable flip flop in the LE can be configured
for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flip flop can be
driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial
functions, the flip flop is bypassed and the output of the LUT drives the output of the LE.