Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

DIGITAL LOGIC DESIGN

BASIC ELECTRICAL & ELECTRONICS LAB

DEPARTMENT OF ELECTRICAL ENGINEERING

Prepared By: Checked By: Approved By:

Engr. Yousaf Hameed Engr. M.Nasim Khan Dr.Noman Jafri

Lecturer (Lab) Electrical, Senior Lab Engineer Electrical, Dean,
FUUAST-Islamabad FUUAST-Islamabad FUUAST-Islamabad

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Name: ____________________________________________

Registration No: ____________________________________

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

C
COON
NTTE
ENNT
TSS

Exp No List of Experiments

1 FAMILIARIZATION WITH ETS-5000 LOGIC TRAINER

2
To demonstrate Diode Logic AND and OR gate
3
Verification of truth table of AND, OR, NOT,NOR, NAND logic gates
4 Implementation of multivariable Boolean expression using logic gates & Verification
of Demorgans Theorem
5
Implementation of 7 segment using EXCESS-3 code, Implementation of Gray code
6 Implementation of half adder & full adder

7 Design & Implementation of a 2 x 4 DECODER

8 Design & Implementation of a 4-to-2 ENCODER

9 Design of a 2x1 and 4x1 Multiplexer

10 Implementation of full adder using MUX

11 Designing and Implementing De-Multiplexer

12 Implementation/design of 1 bit & 2 bit Magnitude Comparators

13
RS Flip-Flop
14
JK Flip-Flop
15
Shift Register

16 Binary Counter

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 1

FAMILIARIZATION WITH ETS-5000 LOGIC TRAINER

ETS-5000 Logic Trainer is a device which is used to study interaction of different logic and universal gates.

Section A comprises of POWER SWITCH it is top left side of trainer. The function of this switch is to use OFF
or ON the power.

Section B comprises of DC POWER. It consists of Voltage Section one port is of +5V, the other is for ground
connection and the third is of -5V.

Section C consists of PULSE GENERATOR. It can be generate a pulse of 1 second, 0.1 second and 0.01
second.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Section D is for computer Interfacing.

Section E consists of PULSE SWITCHES.

Section F consists of SOLDER LESS BREADBOARD OR PROTO BOARD It is consisting of so many holes.

Section G consists of DATA SWITCHES. There are Eight Data Switches in this trainer.

Section H consists of 8 BIT LED OUTPUT INDICATOR. The bulb in this section glows (Red) when there is logic 1
and (Green) when there is logic 0.

Section I consists of MODE SELECTOR. It is used to set the mode on TTL & on CMOS.

Section J consists of DIGITAL DISPLAY. Basically they consist of BCDs.

Section K consists of DIGITAL PROBE.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO-2

TO DEMONSTRATE DIODE LOGIC AND & OR GATE

APPARATUS
Bread board, Power Supply, Multimeter, Resistor 2.2K, Diode IN 4001, Connecting leads

DIODE LOGIC AND GATE

FIGURE - 1 CIRCUIT FOR AND GATE

PROCEDURE

Implement the circuits on breadboard as shown in fig 1 for AND

Apply voltage levels mentioned in the table on the inputs turn by turn and measure respective output
voltage level at the output
Record your observation in the table

OBSERVATIONS OF AND GATE

Table-1
Input Output
A B Y
0V 0V

0V 5V

5V 0V

5V 5V

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

DIODE LOGIC OR GATE

Figure Circuit for OR gate

PROCEDURE

Implement the circuits on breadboard as shown in fig for OR gate

Apply voltage levels mentioned in the table on the inputs turn by turn and measure respective output
voltage level at the output
Record your observation in the table

OBSERVATIONS OF OR GATE

Table-2
Input Output
A B Y
0V 0V

0V 5V

5V 0V

5V 5V

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 3

VERIFICATION OF TRUTH TABLE OF AND, OR, NOT, NAND AND NOR LOGIC GATES.

APPARATUS:

AND (7408), OR (7432), NOT (7404), NAND (7400), NOR (7402 ICs
+Vcc

1 14
Truth Table of AND Gates
2 13
Inputs Output
1
3 12 A B Y
4
7408

4 11 0 0
5 10 0 1
2
6 9
1 0
3
7 8
Ground 1 1
+Vcc

1 14 Truth Table of OR Gates

Inputs Output
2 13
A B Y
1 12
3 0 0
7432

4
4 11
0 1
5 10
1 0
2
6 9

3 1 1
7 8
Ground

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

+Vcc

Truth Table of NOT Gates

1 14 Inputs Output
1

2 13 A Y
6

3
7404 12 0
2

4 11 1
5

5 10
3

6 9
4

7 8
Ground

+Vcc

1 14 Truth Table of NAND Gates

2 13 Inputs Output
1 A B Y
3 12

4 0 0
7400

4 11

5 10 0 1
2
6 9
1 0
3
7 8
Ground 1 1

+Vcc

Truth Table of NOR Gates

1 14 Inputs Output
1
2 13 A B Y
4
3 12 0 0
7402

4 11
2 0 1
5 10
3
1 0
6 9

7 8 1 1
Ground

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 4

IMPLEMENTATION OF MULTIVARIABLE BOOLEAN EXPRESSION USING LOGIC GATES AND

VERIFICATION OF DEMORGANS THEOREM

APPARATUS:

7408, 7432, 7404 ICs, logic kit and connecting wires.

Given Boolean function is
F1 = a b c + .a b c

F2 = (a + b+ c) (a + b)

a b c

a.b'.c

a' b' c'

a.b' F1 = a.b'.c + a'.b.c
To LED
a'.b

a'.b.c
a+b
a+b+c'

F2 = (a+b+c) (a'+b)
a'+b To LED

Now we shall check the logic circuit by the following Truth Table.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

TRUTH TABLE

Outputs
Inputs F1 F2

a b c Actual Observed Actual Observed

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Comments: __________________________________________________________________________

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

DEMORGANS THEOREM
APPARATUS:

7408, 7432, 7404 digital logic kit and connecting leads.

DEMORGANSS LAW: It has two statements.

1. (x+y+z) = x.y.z
where let F1 = (x+y+z) & F2 = x.y.z
2. (x.y.z) = x+y+z
Where let F3 = (x.y.z) F4 = x+y+z

x y z

x'
x'.y'
y' F2 = x'.y'.z'
(To LED)
z'

x
x+y
y x+y+z F1 = (x+y+z)'
(To LED)
z

x'
x'+y'
y' F4 = x'+y'+z'
(To LED)
z'

x
x.y

y F3 = (x.y.z)'
(To LED)
z

Now we shall check this logic circuit by the Truth Table.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Truth Table
Inputs Outputs

F1 = (x+y+z) F2 = x.y.z F3 = (x.y.z) F4 =x+y+z

x y z Actual Observed Actual Observed Actual Observed Actual Observed

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Comments: __________________________________________________________________________

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 5
IMPLEMENTATION OF 7 SEGMENT USING EXCESS-3 CODE, IMPLEMENTATION OF GRAY CODE
APPARATUS:

1. IC 7404(NOT)
2. 7408(AND)
3. 7432(OR)
4. 7446 / 7447 (BCD TO 7-SEGMENT DECODER)
PROCEDURE:

1. In the case of BCD to Excess-3 code conversion, the inputs A, B, C and D are given at a respective

pin and outputs W, X, Y, and Z are taken for all the 10 combinations of the input.

2. The values of the outputs are tabulated.

TABLE:
Truth table for BCD to-Excess 3 Code

BCD CODE EXCESS 3 CODE

INPUTS OUTPUTS
A B C D W X Y Z

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

By writing Boolean function from the table

W = AB CD + AB C D + AB C D + A BCD + A BCD

X = ABCD + ABC D + ABC D + AB CD + A BCD

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Y = ABCD + ABC D + AB CD + AB C D + A BCD

Z = ABCD + ABC D + AB CD + AB C D + A BCD

Now we simplify output functions by k-map technique

Maps for BCD to Excess 3 code converter

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Boolean Functions
Now writing Boolean functions from above k-maps for outputs of BCD to Excess 3 code converter, we get.
Z = D
Y = CD + CD
= CD + (C+D)
X = BC + BD + BCD
= B(C + D) + BCD
= B(C+D) + B(C+D)
W = A + BC +BD
= A + B(C + D)

IMPLEMENTATION

Figure: Logic diagram for BCD to-Excess-3 code converter

7-Segment Light Emitting Diode (LED) Display

Numbers can be represented in different numerical systems with different bases. In daily life, we represent a number using the digits
0 to 9. This is the decimal system and the base is 10. In digital electronics, only two states, Low and High, are used to represent the
digits 0 and 1. This is the binary system and the base is 2. Each digit in a binary number is called a bit, which comes from the English
words binary digit.
Four Inputs W to Z are used to control the number displayed on the LED Display. The Inputs are arranged in the sequence ZYXW
to represent a 4-bit Binary Number. Their weights are as follows:
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Input Z is the Most Significant Bit: (MSB) 23 = 8

Input Y is the Second Significant Bit:(2ndSB) 22 = 4
Input X is the Third Significant Bit: (2rdSB) 21 = 2
Input W is the Least Significant Bit: (LSB) 20 = 1
The conversion between a 4-bit Binary Number and a Decimal Number is:
Decimal Number = Z x 23 + Y x 22 + X x 21 + W x 20

A 7-Segment LED Display is composed of seven segments, Figure 1. Each segment is a LED. They are combined to produce
standardized representations of the decimal Arabic numbers.

An Integrated Circuit (IC) chip, BCD to 7-Segment Decoder (7446/7447), is used to convert the four binary Inputs A to D to seven
Outputs, which drive the 7-Segment LED Display. BCD means Binary Coded Decimal. Table 1 shows the relation between the binary
Inputs, Decoder Outputs and decimal numbers 0 to 9. Figure 2 is the diagram of a display module with a BCD to 7-Segment Decoder
and a 7 Segment-LED Display.

Figure 1: A 7-Segment LED

Display
Figure 2 BCD to 7-Segment

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Table: BCD to 7-Segment Decoder Truth-Table

Truth table for BCD to-Excess 3 Code

BCD CODE EXCESS 3 CODE

INPUTS OUTPUTS 7 Segment
Display
A B C D W X Y Z

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

BINARY TO GRAY CODE CONVERSION

APPARATUS:

IC 7486, etc

PROCEDURE: -

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.
3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at a
respective pin and outputs G0, G1, G2, G3 are taken for all the 16 combinations of the input.
4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at
respective pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations of inputs.
5. The values of the outputs are tabulated.
Table:
Truth table for Gray Code

BCD CODE GRAY CODE

INPUTS OUTPUTS
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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IMPLEMENTATION

B0
B0 G0
G0 B1
B1 G1

G1 B2
B2 G2

G2 B3
B3 G3

G3

Table:
Truth table for Gray Code

BCD CODE GRAY CODE

INPUTS Observed
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 6
IMPLEMENTATION OF HALF ADDER & FULL ADDER
APPARATUS:
7486, 7432, 7408, 7404 ICs, logic kit and connecting leads.
HALF ADDER:
Half Adder is combinational logic circuit that generates the sum of two binary numbers (each having 1 bit
length). The logic circuit has two inputs and two outputs i.e. Sum & Carry abbreviated as SHA & CHA
respectively.
First of all, we shall construct Truth Table of Half Adder
Truth Table
Inputs Outputs
SHA = xy+xy CHA = x y
x y Actual Observed Actual Observed
0 0

0 1

1 0

1 1

Now we write Boolean function from above Truth Table as

SHA =xy + xy
CHA = xy
IMPLEMENTATION
Now we implement above Boolean expression by basic logic gates i.e.

Now we shall check this logic circuit by the Truth Table of Half Adder.
Lab Exercise:
1. Students are required to write outputs of Full adder using Basic logic gates..

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

2. Then implement Half Adder using basic logic gates.

FULL ADDER:
Full Adder is combination logic circuit that performs the sum of 3 input binary numbers, (each having 1 bit
length). Two of the binary input variables are x and y represent the two significant bits to be added the third
input z, represents the carry from previous lower significant position. Outputs of Full Adder are Sum and
Carry represented as SFA and CFA respectively.

First of all, we shall construct Truth Table of Full Adder i.e.

Truth Table
Inputs Outputs
x y z SFA CFA
Actual Observed Actual Observed
0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Now we write Boolean expression for Sum and Carry of Full Adder.

1) Sum = xyz+xyz+xyz+xyz

Simplifying by using Boolean Postulates & theorems/k-map, we get

Sum =(xy+xy) . z + (xy+xy).z

SFA = (x y ) z

2) Carry = xyz + xyz + xyz+xyz

Simplifying by using Boolean Postulates & theorems/k-map, we get

Carry = (xy+xy) . z+xy

CFA = (x y) z + xy

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Implementation

Now we implement simplified Boolean expressions of SFA & CFA i.e.

x y z

HA1 HA2

SFA = (x + y) + z
To LED

CFA = (x + y) z + xy
To LED

We shall check this logic circuit by the Truth Table of Full Adder

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 7

DESIGN & IMPLEMENTATION OF A 2 x 4 DECODER

APPARATUS:
7432, 7408, 7404 ICs logic kit and connecting leads
DECODER:
n 2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to max of 2n output
lines e.g. if we have 2 inputs i.e. x,y then there will be 4 output of a Decoder and size of
Decoder will be 2X4.

BLOCK DIAGRAM OF 2X4 DECODER.

data input lines

d0

output lines
x
2X4 d1
y DECODER d2
d3

Truth Table 2 X 4 Decoder

Inputs Enable Outputs

x y E d0 d1 d2 d3

0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1
Boolean Functions for 2 x 4 Decoder
do = E x y
d1 = E xy
d2 = E x y
d3 = E x y
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IMPLEMENTATION

x y

x' y'
d0 = x' y'
(To LED)

d1 = x' y
(To LED)

d2 = x y'
(To LED)

d3 = x y
(To LED)

E
Now we check this logic circuit by using Truth Tables of 2X4 Decoder as drawn above.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 8

DESIGN & IMPLEMENTATION OF A 4-TO-2 ENCODER

Apparatus:
7432, 7408, 7404 ICs logic kit and connecting leads

ENCODER:
Encoders work in exactly the opposite way as decoders, taking 2n inputs, and having n outputs. When a bit comes in on an
input wire, the encoder outputs the physical address of that wire. It takes 2n inputs and gives out n outputs; the enable pin should be
kept 1 for enabling the circuit.
n 2n .
n = No. of output lines.
2n = No. of input of a Decoder.

Block Diagram of 4 X 2 Encoder

Truth Table 4 X 2 Encoder

INPUTS Enable OUTPUT

d0 d1 d2 d3 E x y
1 0 0 0 1 0 0
0 1 0 0 1 0 1
0 0 1 0 1 1 0
0 0 0 1 1 1 1

Boolean Functions for 4 X 2 Encoder

x = d0 d1 d2 d3 + d0 d1 d2 d3

y = d0 d1 d2 d3 + d0 d1 d2 d3

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Implementation

Now we check this logic circuit by using Truth Tables of 4 to 2 Encoder as drawn above.

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 9

DESIGN OF A 2X1 and 4X1 MULTIPLEXER

APPARATUS:
7432, 7408, 7404 logic kit and connecting wires

MULTIPLEXER
Multiplexer, simply called MUX, is a data selector and is capable of selecting one of
many input lines (usually 2n) and display its input status on the only output line available.

A MUX has
1) Select lines
2) Data input lines
3) Output line.
BLOCK DIAGRAM OF 2X1 MUX

I0
data i/p lines 2X1 MUX Y

I1 output

select line

I0, I1 are inputs of MUX

S is select line
Y is output

THE FUNCTION TABLE OF 2X1 MUX IS

Select line Output

S Y
0 Io
1 I1

THE BOOLEAN FUNCTION FOR 2X1 MUX IS

Y = I1 s + I0 s
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LOGIC DIAGRAM OF 2X1 MUX IS

I1 s I0

I1 s
I1 s + I0 s' = Y
To LED

s'

I0 s'

BLOCK DIAGRAM OF 4X1 MUX

I0
I1 4X1 MUX Y
data i/p lines
I2 output

I3

S1 S0
select lines

THE FUNCTION TABLE OF 4X1 MUX IS

Select lines Output

S1 S0 Y
0 0 Io
0 1 I1
1 0 I2
1 1 I3
.
THE BOOLEAN FUNCTION FOR 4X1 MUX IS

Y = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0

Logic Diagram of 4x1 MUX is

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

S1 S0

I0
I0
I1 I1
Y
To LED
I2 I2

I3 I3

We check this logic circuit by Function Table of 4X1 MUX as drawn above.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 10

IMPLEMENTATION OF FULL ADDER USING MUX

APPARATUS:

74151 MUX, connecting wires.

MUX :
2n 1.
n = No. of select lines.
2n = No. of inputs of MUX
if n = 3, size of MUX is 8x1 i.e.

I0
I1
I2
Data input lines

I3 8X1 MUX
I4 Y
output
I5
I6
I7

x y z
select lines

FUNCTION TABLE
Select lines Output
x y z Y
0 0 0 Io
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

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PIN CONFIGURATION OF 74151 MUX

1 16
I3 VCC
2 I2 15

Data i/p
I4

lines

Data i/p
3 14
I1 I5

lines
74LS151
4 13
I0 I6
12
o/p lines

5
Y I7
6 11
x

Data select
W

lines
7 10
E y
8
GND z 9

74LS151 involves 8X1 mux.

PROCEDURE:

First of all we check / implement Carry of Full Adder (having 3 inputs) using 8X1 MUX, for
this take: I0 = 0, I1 = 0, I2 = 0, I3 = 1, I4 = 0, I5 = 1, I6 = 1, I7 = 1, from Carry column of Truth
table of Full Adder and then select x,y,z from Function table of 8X1 MUX and then observe
outputs at Y Pin of 74151 IC, that should be equal to Carry of Full Adder for combination of
x,y,z at select lines, which is inserted through data switches, this step is repeated for all
x,y,z combinations, at select lines to observe Carry of Full Adder.

Then we check/implement Sum of Full Adder for 3 input variables, using 8X1 MUX for this,
we take: I0 = 0, I1 = 1, I2 = 1, I3 = 0, I4 = 1, I5 = 0, I6 = 0, I7 = 1, from Sum column of Truth
Table of Full Adder, as data inputs to 8X1 MUX, and then for each combination of x,y,z at
select lines from Function table,. We see output at Y Pin of 74151 IC, which should be
equal to value of Sum of Full Adder for x,y,z combination at select lines, which is inserted
through data switches, this step is repeated for all x,y,z combinations, at select lines to
observe Sum of Full Adder.

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 Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Truth Table of Full Adder

Inputs of Full Adder Outputs

x y z S C

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

FUNCTION TABLE OF 8X1 MUX

Output of 8x1 Output of 8x1 Output of 8x1

Inputs of Full Adder = Select lines of MUX
MUX MUX MUX
x y z S=Y C=Y

0 0 0 0 0 I0
0 0 1 1 0 I1
0 1 0 1 0 I2
0 1 1 0 1 I3
1 0 0 1 0 I4
1 0 1 0 1 I5
1 1 0 0 1 I6
1 1 1 1 1 I7

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 11
DESIGNING AND IMPLEMENTING DE-MULTIPLEXER

A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations).the select lines
determine which output the input is connected to.

BLOCK DIAGRAM OF 1X4 DE-MUX

THE FUNCTION TABLE OF 1X4 DE-MUX IS

Select lines
Output
S1 S0
0 0 Do
0 1 D1
1 0 D2
1 1 D3
.
THE BOOLEAN FUNCTION FOR 1X4 DE- MUX IS

D0 = A S1 S0
D1 = A S1 S0
D2 = A S1 S0
D3 = A S1 S0

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Logic Diagram of 1X4 DE-MUX is

We check this logic circuit by Function Table of 1 DE-MUX as drawn above.

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO :12

IMPLEMENTATION/DESIGN OF 1 BIT & 2 BIT MAGNITUDE COMPARATORS

APPARATUS:
7486, 7432, 7408, 7404 logic kit and connecting wires.
ONE BIT MAGNITUDE COMPARATOR
One Bit Magnitude Comparator is combination logic circuit which is used to compare two input binary
numbers (each having one bit length) to check weather two inputs are equal or one less than other or greater
then.

First of all we write Truth Table of 1 Bit Magnitude Comparator i.e.

Truth Table
Inputs Outputs
x y E
x=y G
x>y L
x<y
0 0 1 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0

BOOLEAN FUNCTIONS FOR ONE BIT MAGNITUDE COMPARATOR

E = x y + x y
G = x y
L = x y
IMPLEMENTATION x y

x' y'
xy
E=(x y+x' y')

(To LED)
x' y'

G=x y'
(To LED)

L = x' y
(To LED)

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To check this logic circuit, we shall use the above Truth Table

2 BIT MAGNITUDE COMPARATOR

Two Bit Magnitude Comparator which is used to compare two input binary numbers (each having bit length
of two ) to check weather two inputs are equal or one less than other or greater then.
USING XOR GATES AND BASIC LOGIC GATES

First of all we write Truth Table of 2 Bit magnitude Comparator.

Truth Table
Inputs Outputs
A B
A1 A0 B1 B0 E
A=B G
A>B L
A<B
0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0
1 1 1 1 1 0 0
Now we simplify outputs of 2 Bit Magnitude Comparator by k-map technique.

k-maps for outputs of 2 Bit Magnitude Comparator.

k-map of E.

E B1B0
A1 A0 00 01 11 10
00 1
01 1
11 1
10 1

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k-map of G
G B1B0

A1A0 00 01 11 10
00
01 1
11 1 1 1
10 1 1

k-map of L.

L B1B0
A1 A0 00 01 11 10
00 1 1 1
01 1 1
11
10 1

BOOLEAN FUNCTIONS
Now writing Boolean functions from above k-maps for outputs of two Bit Magnitude Comparator, we get.

E = A1 A0 B1 B0+ A1 A0 B1 B0 + A1 A0 B1 B0+ A1 A0 B1 B0
E = A1 B1(A0 B0+ A0 B0) + A1 B1(A0 B0+ A0 B0)
E = (A0 B0+ A0 B0) (A1 B1+ A1 B1)

E = (A0 + B0)'(A1 + B1)'

G = A1B1 + A1 A0 B1 B0 + A1 A0 B1 B0
G = A1B1 + A0 B0 (A1B1 + A1 B1)

G = A1B'1 + A0B'0 (A1 + B1)'

L = A1B1 + A0 B0 (A1B1 + A1 B1)

L = A'1B1 + A'0B0 (A1 + B1)'

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

IMPLEMENTATION

A1 A0 B1 B0

E = (A0 + B0) (A1 + B1)

(To LED)

G = A1B'1 + A0B'0 (A1 + B1)'

(To LED)

L = A'1B1 + A'0B0 (A1 + B1)'

(To LED)

We check this circuit by Truth Table of 2 Bit Magnitude Comparator as written before.

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 13

RS FLIP-FLOP
THEORY

Figure-1 Clock Part RS Flip-Flop

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

PROCEDURE

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Table-1

INPUT OUTPUT
R S Q Q

0 0

0 1

1 0

1 1

Remark:

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 14

JK FLIP-FLOP
THEORY

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

ACT OF JK FLIP-FLOP

DEMERIT OF JK FLIP-FLOP

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PROCEDURE

Table-2

INPUT OUTPUT

J K CLK Q Q

0 0

0 1

1 0

1 1

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 15

SHIFT REGISTER

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

EXPERIMENT NO: 16

BINARY COUNTER
THEORY
BINARY RIPPLE COUNTER

Figure- 5 4-bit binary ripple Counter

Figure-6 Calculating order of Binary ripple Counter

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Binary down Counter

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Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

ASYNCHRONOUS DECIMAL(BCD) COUNTER

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Figure -9 Decimal (BCD) asynchronous counter

PROCEDURE:

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

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Digital Logic Design
Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

USEFUL ICs

THEORY:
IC Family Summary: Various families of logic ICs exist on the market however the families, mainly used in digital electronics lab are
the TTL and the high speed CMOS families.
Nomenclature of digital ICs:
MM74XXXNNRP
MM - Manufacturer
74/54 - Temperature range
XXX - Technology type
NNN - Logic Function
R - Revision
RP - Package Type
Manufacturer - MM
SN - Texas Instrument, Motorola
DM - National Semiconductor
Temperature Range 74 or 54
74 - Standard (commercial) 0 to 70C
54 - Military -55 to 125C
Technology Type XXX
LS Low power schottky
ALS Advanced low power schottky
Fv -- Fast TTL
HC -- high speed CMOS
C -- Low speed CMOS
Vcc It is supply voltage which operate any instrument without damaged. Vcc terminal is always Red.
Ground It is zero potential point, GND terminal is always black.

7400(NAND) 7402(NOR)

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7404(NOT) 7411(3-I/P AND)

7408(AND) 7420(4-I/P NAND)

7410(3-I/P NAND)
7432(OR)

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7476
7486(EX-OR)

7485

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Digital Logic Design