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Experiment 10 Lab Report

1) The document describes building an electronic dice roller circuit using sequential and combinational logic circuits. 2) The circuit uses a 3-bit counter made of JK flip-flops to count from 1 to 6, and an oscillator made of NAND gates and inverters to provide the clock signal. 3) The experiment's goal was achieved as the completed circuit functioned properly to randomly generate numbers from 1 to 6 on a 7-segment display each time the clock signal changed.

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Kip Kiper
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261 views

Experiment 10 Lab Report

1) The document describes building an electronic dice roller circuit using sequential and combinational logic circuits. 2) The circuit uses a 3-bit counter made of JK flip-flops to count from 1 to 6, and an oscillator made of NAND gates and inverters to provide the clock signal. 3) The experiment's goal was achieved as the completed circuit functioned properly to randomly generate numbers from 1 to 6 on a 7-segment display each time the clock signal changed.

Uploaded by

Kip Kiper
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Objective:

To use both sequential and combinational logic circuits to build a real world application - an
Electronic Dice Roller.

Intro:

For this experiment, we produced a virtual six sided die roller that generated a number from 1 to
6 each time the clock signal went high. To accomplish this, we constructed a 3 bit counter using
JK flip flops, and an oscillator using a NAND gate and a series connection of invertors. The
oscillator was connected to the clock of the flip flops, ensuring that the signal was random.

Procedure:

First, we created a 3 bit counter using JK flip flops. It counted from 6 to 1 and then repeated
itself. It order to produce the counter, we first made a state diagram with the corresponding J and
K values, and found the corresponding inputs function for each J and K. We also wired the
circuit so that it could be reset to 6. After creating the counter in Multi-Sim, we created an
oscillator using a two input NAND gate and a series of invertors. We connected the oscillator
input to the clock switch, and then connected the output of the oscillator to the clock inputs on
the flip flops. We then connected the outputs of the flip flops to the decoder, and connected the
decoder to a seven segment LED display. We then tested the circuit to ensured proper
functionality. After we were sure of the circuits correctness, we constructed it on the
breadboard. We then tested the final circuit to ensure than if functioned properly, and wrote the
lab report.

Equipment Section:

1.) The MultiSim software


2.) 74 LS series chips
3.) 7-segment display
4.) Wire and breadboard

Preparatory Exercises:

1.) What does the oscillator do when N is an odd number?


In our circuit, when we had an odd number of inverters, the number displayed on the
seven segment display would not change so the oscillator will not function correctly
when N is odd.

2.) What happens if N is an even number?


Whenever we had an even number of inverters, we would get a random number from our
circuit which was expected.
3.) If you want a high speed oscillator, do you increase the number of N or do you decrease
it?
For a high speed oscillator, you decrease the number of inverter. But you should stay
within the parameters of the chips.

4.) Do you or dont you see a dim 8 when the Enable switch of the oscillator is thrown
ON? Explain.
If the reset, or enable, is high and the clock is high, you will see a dim eight because the
circuit will be oscillating rapidly through the numbers 1 to 6. But for our circuit we did
not have a current limiting resistor so our 8 was relatively bright.

Results:

State Table:

Present State Next State J2 K2 J1 K1 J0 K0


110 101 d 0 d 1 1 d
101 100 d 0 0 d d 1
100 011 d 1 1 d 1 d
011 010 0 d d 0 d 1
010 001 0 d d 1 1 d
001 000 0 d 0 d d 1
000 110 1 d 1 d 0 d
111 ddd d d d d d d

State Diagram:

101

110 100

001 011

010
Karnaugh Maps:


2 = 1

2 = 0 =
1 1
0

+ 0
1 = 2 =
2 0
1 =
0

0 = 1

0 = 1
Sample Calculations:

From clock to outputs the signal goes through 2 2-input nand gates, 9 inverters, 1 JK flip flop,
and 1 decoder.

Typical Propagation Delay:

2(9ns) + 9(9ns) + 1(15ns) + 100ns = 214ns

Maximum Propagation Delay:

2(15ns) + 9(15ns) +1(20ns) + 100ns = 285ns

Circuit Diagram:

Circuit Picture:

Conclusions:

Our final circuit functioned exactly as it was supposed to. None of the logic in the circuit was
incorrect, but we discovered that we used the wrong seven segment display. After changing the
display, the circuit worked exactly as needed. Our design benefited from our chip placement.
Instead of placing the chips several rows apart, we placed several of the next to each other. This
reduced the amount of wiring we needed, which may have slightly improved the speed of the
circuit.

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