VHDL - Intro and Syntax - VLSI Design Using VHDL Training - Internshala VTC
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VHDL: Intro and Syntax
VHDL stands for VHSIC Hardware Description Language (where VHSIC is an abbreviation for Very High Speed Integrated
Circuits). We use VHDL for simulation and synthesis of digital circuits.
Simulation and Synthesis
Simulation: It is the preliminary step to verify the correct functioning of the circuit in terms of waveforms showing output and
input signal variations.
Synthesis: It is the process of generating gate-level schematics or RTL (RTL: Register Transfer Level) schematics for an entity
under design.
If you're wondering about the application of VHDL code,
1. You can download your VHDL code on a programmable logic device (like FPGA, CPLD, etc) to implement the IC you've
written code for!
2. Or you can submit it to foundry for fabrication of your IC.
DID YOU KNOW?
VHDL was developed at the behest of Department of Defence, USA for developing high speed ASICs (Application
Specic ICs)
Observe this little piece of VHDL code for a full-adder:
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6/22/2017 VHDL: Intro and Syntax | VLSI Design using VHDL Training | Internshala VTC
library IEEE; --Library Declaration
use IEEE.STD_LOGIC_1164.ALL; --Library Declaration
-- Writing code for a full-adder circuit.
entity full_adder is --Entity declaration: name of the circuit you want to
--make, all input, inout, output pins and their types
--are declared here.
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
carry_in : in STD_LOGIC;
carry_out : out STD_LOGIC;
sum : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
--Architecture of the circuit is coded in this part.
begin
sum <= a xor b xor carry_in;
carry_out <= (a and b) or (b and carry_in) or (a and carry_in);
end Behavioral;
Please note:
1. Every statement is terminated by a semicolon (;).
2. A double dash ('--') is used for commenting out a particular line. It organises the design and makes easily understandable
to others.
3. '<=' is an assignment operator, but is it used only when you're assigning a value to a SIGNAL. In case of a VARIABLE, we
use ':=' as an assignment operator. Dierence between SIGNAL and VARIABLE would be discussed later.
4. VHDL is not case sensitive.
From the above example, we nd that the writing a VHDL code can be divided into three parts:
1. Library declaration: Here we declare and included the libraries to be used in a particular code.
2. Entity: In this part of the code, all the ports (number and types) are declared.
3. Architecture: This describes how circuit should function.
Test Yourself
Q1. What is VHDL, and what it is used for?
Show/Hide Answer
Ans. VHDL is a hardware description language, and it is used for simulation and synthesis of ICs.
More Exercises
1. What symbol do we use to comment out a particular line?
(content.php?topic_id=7&module_id=1&course=vlsi101) (content.php?
topic_id=6&module_id=1&course=vlsi101)
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