ESD-1 LAB MANUAL M.E.

APPLIED ELECTRONICS

SYSTEM DESIGN USING PIC MICROCONTROLLER

Ex NO:1
Date:

AIM
To write a program for Transmission and Reception, LCD, Seven
Segment display using PIC microcontroller.

APPARATUS REQUIRED
PIC 16f877 kit
Power Cable
Serial Cable
PC

PROCEDURE

Double click on MP Lab

Open project,create a new project and give file name and save
Open new file,type the program and save with c extension
Include the source file and enable port by +pe.
Run compiler and close the window
Open PIC LSP by clicking on PIC LSP icon
Download file to pic kit to execute the output.

THEORY

Serial Transmission and reception

Serial communication is one of the simplest ways of

communication between a microcontroller and PC or vice versa. It
requires only single wire for transmission of a data and another for
receiving.This communication can be used for controlling the robot from
a PC manually or the computer program controls it. The serial port on
your PC is a full-duplex device meaning that it can send and receive data
at the same time. Once the start bit has been sent, the transmitter sends
the actual data bits. There may either be 5, 6, 7, or 8 data bits, depending
on the number you have selected. Both receiver and the transmitter must
agree on the number of data bits, as well as the baud rate. Almost all
devices transmit data using either 7 or 8 databits.

1
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

LCD

A liquid crystal display (LCD) is a flat panel display, electronic

visual display, or video display that uses the light modulating properties
of liquid crystals. Liquid crystals do not emit light directly.LCDs are
available to display arbitrary images (as in a general-purpose computer
display) or fixed images which can be displayed or hidden, such as preset
words, digits, and 7-segment displays as in a digital clock. They use the
same basic technology, except that arbitrary images are made up of a
large number of small pixels, while other displays have larger elements.
LCDs are used in a wide range of applications including computer
monitors, televisions, instrument panels, aircraft cockpit displays, and
signage. They are common in consumer devices such as video players,
gaming devices, clocks, watches, calculators, and telephones, and have
replaced cathode ray tube (CRT) displays in most applications. They are
available in a wider range of screen sizes than CRT and plasma displays,
and since they do not use phosphors, they do not suffer image burn-in.
LCDs are, however, susceptible to image persistence.

Seven segment display

A seven-segment display (SSD), or seven-segment indicator, is a

form of electronic display device for displaying decimal numerals that is
an alternative to the more complex dot-matrix displays. Seven-segment
displays are widely used in digital clocks, electronic meters, and other
electronic devices for displaying numerical information
In most applications, the seven segments are of nearly uniform
shape and size (usually elongated hexagons, though trapezoids and
rectangles can also be used), though in the case of adding machines, the
vertical segments are longer and more oddly shaped at the ends in an
effort to further enhance readability.
The numerals 0,1,6, 7 and 9 may be represented by two or more
different glyphs on seven-segment displays.The seven segments are
arranged as a rectangle of two vertical segments on each side with one
horizontal segment on the top, middle, and bottom. Additionally, the
seventh segment bisects the rectangle horizontally. There are also
fourteen-segment displays and sixteen-segment displays (for full
alphanumerics); however, these have mostly been replaced by dot-matrix
displays.The segments of a 7-segment display are referred to by the
letters A to G, where the optional DP decimal point (an "eighth segment")
is used for the display of non-integer numbers.

2
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

PROGRAM

1a.TRANSMISSON & RECEPTION

#include<16f877.h>
#use delay(clock=20000000)
#use rs232(baud=19200,xmit=pin_c6,rcv=pin_c7)
void main()
{
printf("\n\r Program for Serial Reception and
Transmission");
printf("\n\r Press Any Key On the Keyboard");
printf("\n\r");
while(1)
{
putc(getc());
}
}

3
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

1b.LCD
#include<16F877.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
void busycheck();
unsigned int array[13]={"DEPT. OF ECE"};
unsigned char array1[] = {"ME_AE"};
unsigned char array2[] = {"ESD LAB"};
unsigned char a,i,b;
void main()
{
output_low(PIN_B3);
output_high(PIN_B1);
busycheck();
output_d(0x38);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x06);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x01);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x0c);
output_high(PIN_B3);
output_low(PIN_B3);
busycheck();
output_d(0x82);
output_high(PIN_B3);
output_low(PIN_B3);
for (i=0;i<12;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
b=array[i];
output_d(b);
output_high(PIN_B3);
output_low(PIN_B3);

4
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

}
busycheck();
output_d(0xc6);
output_high(PIN_B3);
output_low(PIN_B3);
for (i=0;i<5;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
b=array1[i];
output_d(b);
output_high(PIN_B3);
output_low(PIN_B3);
}

busycheck();
output_d(0x96);
output_high(PIN_B3);
output_low(PIN_B3);
for (i=0;i<7;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);
b=array2[i];
output_d(b);
output_high(PIN_B3);
output_low(PIN_B3);
}

busycheck();
output_d(0xd4);
output_high(PIN_B3);
output_low(PIN_B3);
for (i=0;i<20;i++)
{
busycheck();
output_d(0x01);
output_low(PIN_B1);
output_high(PIN_B1);

5
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

output_d('-');
output_high(PIN_B3);
output_low(PIN_B3);
}
stop:
goto stop;
}
void busycheck()
{
output_d(0x02);
output_low(PIN_B1);
output_high(PIN_B1);
delay_ms(2);

busy:
output_high(PIN_B3);
output_low(PIN_B3);
a=input_d();
if ((a&0x80)==0x80)
goto busy;
output_d(0x0);
output_low(PIN_B1);
output_high(PIN_B1);
delay_us(10);
}

6
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

1c.SEVENSEGMENT
#include <16F877.h>
#use delay(clock=20000000)
#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)
void IC_Config();
unsigned long int c;
void main()
{ IC_Config(
); while(1)
{ delay_ms(5
); i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(0x77);
i2c_write(0xfe);
i2c_stop();
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(0x7f);
i2c_write(0xfd);
i2c_stop();
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(0x39);
i2c_write(0xfb);
i2c_stop();
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(0x3f);
i2c_write(0xf7);
i2c_stop();
}
}
void IC_Config()
{

7
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

delay_us(1000);
i2c_start();
i2c_write(0x44);
i2c_write(0x04); //GPIO Register
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
delay_us(1000);
i2c_start();
i2c_write(0x44);
i2c_write(0x06); //GPIO Register
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
delay_us(1000);
i2c_start();
i2c_write(0x44);
i2c_write(0x0a); //GPIO Register
i2c_write(0x01);
i2c_write(0x01);
i2c_stop();
delay_us(1000);
}

RESULT
Thus, the system design for Transmission &
Reception,LCD,Seven Segment display are executed using PIC
Microcontroller and its output are verified.

8
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SYSTEM DESIGN USING DSP

Ex. No:2
Date:

AIM

To write a program for adaptive filter, periodogram and multistage multirate system
using DSP processor

SOFTWARE/APPARATUS REQUIRED
TMS 320C6713
CCS studio 3.1, vsk 6713software
Serial Cable
PC
Function generator
CRO

PROCEDURE
Double click on CCS studio
Open project,create a new project and give file name and save
Open new file,type the program and save with c extension
Include the source file
Run compiler and close the window
Open vsk 6713 by clicking on vsk 6713 icon
Download file to DSP processor kit to execute the output.
Give inputs from function generator and check the executed output in
the CRO.
THEORY

Periodogram

The periodogram is based on the definition of the power spectral density

(PSD) . Let denote a windowed segment of samples from a
random process , where the window function (classically the rectangular
window) contains nonzero samples. Then the periodogram is defined as the

squared-magnitude DTFT of divided by .

(7.23)

9
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

In the limit as goes to infinity, the expected value of the periodogram equals the
true power spectral density of the noise process . This is expressed by writing

Adaptive filter

Digital signal processing (DSP) has been a major player in the current
technical advancements such as noise filtering, system identification, and voice
prediction. Standard DSP techniques, however, are not enough to solve these
problems quickly and obtain acceptable results. Adaptive filtering techniques must be
implemented to promote accurate solutions and a timely convergence to that solution.

Adaptive Filtering System Configurations

There are four major types of adaptive filtering configurations; adaptive
system identification, adaptive noise cancellation, adaptive linear prediction, and
adaptive inverse system. All of the above systems are similar in the implementation of
the algorithm, but different in system configuration. All 4 systems have the same
general parts; an input x(n), a desired result d(n), an output y(n), an adaptive transfer
function w(n), and an error signal e(n) which is the difference between the desired
output u(n) and the actual output y(n). In addition to these parts, the system
identification and the inverse system configurations have an unknown linear system
u(n) that can receive an input and give a linear output to the given input.

Adaptive System Identification Configuration

The adaptive system identification is primarily responsible for determining a
discrete estimation of the transfer function for an unknown digital or analog system.
The same input x(n) is applied to both the adaptive filter and the unknown system
from which the outputs are compared (see figure 1). The output of the adaptive filter
y(n) is subtracted from the output of the unknown system resulting in a desired signal
d(n). The resulting difference is an error signal e(n) used to manipulate the filter
coefficients of the adaptive system trending towards an error signal of zero.

10
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

PROGRAM
2.a Adaptive Filter

typedef unsigned int Uint32;

typedef int Int32;
typedef short Int16;
typedef unsigned short Uint16;

int main(void)
{
Int16 outCh1;
Int16 outCh2;
Int16 *origSig;
Int16 *noiseSig;
Int16 alteredSig;
Int16 noiseEst;

double *kern;
Int16 errorSig;
Int32 outValue;
Int32 filtCount;
Uint32 *socValue;
Uint32 socRead;
Uint32 *adcValue;
Uint32 *dacCh1;
Uint16 *dacCh2;
Uint16 adcOut;
socValue = (Uint32 *)0x9004000c;
adcValue = (Uint32 *)0x90040008;
dacCh1 = (Uint32 *)0x90040008;
dacCh2 = (Uint16 *)0x9004000a;
origSig = (Int16 *)0x00013000;
noiseSig = (Int16 *)0x00014000;
kern = (double *)0x00016000;

for(filtCount = 0; filtCount < 32; filtCount++)

{
*(noiseSig + filtCount) = 0x00000000;
*(kern + filtCount) = 0x00000000;
}
while(1)
{
socRead = *socValue;

adcOut = *adcValue;
adcOut &= 0x0fff;
//adcOut ^= 0x0800;

*origSig = adcOut;

11
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

adcOut = *adcValue;
adcOut &= 0x0fff;
adcOut ^= 0x0800;

*noiseSig = adcOut;
alteredSig = *origSig + *noiseSig;

outValue = 0;

for(filtCount = 0; filtCount < 32; filtCount++)

outValue += *(noiseSig + filtCount) * *(kern + filtCount);

noiseEst = outValue >> 12;

errorSig = alteredSig - noiseEst;

for(filtCount = 31; filtCount >= 0; filtCount--)

{
*(kern + filtCount) = *(kern + filtCount) + (2 * 0.0000001 * errorSig) *
*(noiseSig + filtCount);
*(noiseSig + filtCount + 1) = *(noiseSig + filtCount);
}
outCh1 = alteredSig;

//*dacCh1 = adcOut;
*dacCh1 = outCh1;

outCh2 = errorSig;

//*dacCh2 = adcOut;
*dacCh2 = outCh2;
}
return 0;
}

2.b PERIODOGRAM

#include "math.h"
#define ORDER 128
#define M_PI 3.1415926535897932384626433832795
#define no_of_samples 8

void square calc(int *w,int *o); void

root(int *o_out,int *o_output); void
auto_corr(int *,int *,unsigned int);
void normalize(int *a1_input,int *n_a_output,unsigned int num_of_points);
unsigned int max_find(int *a_input);

12
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

//int in[25] = {1,4,3,23,2,55,8,8,44,32,68,2,99,5,1,58,45};

//int in[25] = {1,7,3,4,2,6,12,8};
//int in[32] =
{1024,1223,1415,1592,1747,1874,1969,2027,2047,2027,1969,1874,1747,1592,1415,
1223,1024,825,633,456,301,174,79,21,1,21,79,174,301,456,633,825,
//};
//int in[32] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,
//20,21,22,23,24,25,26,27,28,29,30,31,32};
//int in[8]={
//100,200,300,400,500,600,700,800,
//};
/*int in[8]={
100,700,300,400,200,600,1200,800,
};*/
int in[8]={
1,27,73,4,65,86,87,8,
};
/*
int in[32]={
100,200,300,400,500,600,700,800,900,1000,
1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,
2100,2200,2300,2400,2500,2600,2700,2800,2900,3000,
3100,3200
};
*/
unsigned int num_of_points,max_th;
main()
{
int *x,temp,N,N2,inv=0,*output,*input,*a_input,*out,*n_a_input;
int ir,ii,tr,ti,ar,ai,br,bi;
int i,j,k,l,le1,p,m;
int twid[900];
max_th = 0;
input = (int *)0x80000000;
a_input = (int *)0x80004000;
n_a_input = (int *)0x80005000;
x = (int *)0x80001000;
out = (int *)0x80002000;
output = (int *)0x80003000;
for(i=0;i<no_of_samples;i++){
*input++ = in[i];
}

for(i=no_of_samples;i<ORDER/2;i++)
*input++ = 0;

input = (int *)0x80000000;

auto_corr(input,a_input,64);
a_input = (int *)0x80004000;
max_th = max_find(a_input);

13
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

if(max_th==1)
{ normalize(a_input,n_a_input,ORDER
); n_a_input = (int *)0x80005000;
for(i=0;i<128;i++){
*x++ = *n_a_input++;
*x++ = 0;}
}
else{
a_input = (int *)0x80005000;
for(i=0;i<128;i++){
*x++ = *a_input++;
*x++ = 0;}
}
x = (int *)0x80001000;
N = 128;
N2 = (N << 1);
twid[0] = 0x100;
twid[1] = 0x0;
twid[2] = 0x100;
twid[3] = 0x0;
twid[4] = 0x100;
twid[5] = 0x0;
twid[6] = 0x100;
twid[7] = 0x0;
twid[8] = 0x100;
twid[9] = 0x0;
twid[10] = 0x100;
twid[11] = 0x0;
twid[12] = 0x100;
twid[13] = 0x0;
twid[14] = 0x100;
twid[15] = 0x0;
twid[16] = 0x100;
twid[17] = 0x0;
twid[18] = 0x100;
twid[19] = 0x0;
twid[20] = 0x100;
twid[21] = 0x0;
twid[22] = 0x100;
twid[23] = 0x0;
twid[24] = 0x100;
twid[25] = 0x0;
twid[26] = 0x100;
twid[27] = 0x0;
twid[28] = 0x100;
twid[29] = 0x0;
twid[30] = 0x100;
twid[31] = 0x0;
twid[32] = 0x100;
twid[33] = 0x0;

14
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[34] = 0x100;
twid[35] = 0x0;
twid[36] = 0x100;
twid[37] = 0x0;
twid[38] = 0x100;
twid[39] = 0x0;
twid[40] = 0x100;
twid[41] = 0x0;
twid[42] = 0x100;
twid[43] = 0x0;
twid[44] = 0x100;
twid[45] = 0x0;
twid[46] = 0x100;
twid[47] = 0x0;
twid[48] = 0x100;
twid[49] = 0x0;
twid[50] = 0x100;
twid[51] = 0x0;
twid[52] = 0x100;
twid[53] = 0x0;
twid[54] = 0x100;
twid[55] = 0x0;
twid[56] = 0x100;
twid[57] = 0x0;
twid[58] = 0x100;
twid[59] = 0x0;
twid[60] = 0x100;
twid[61] = 0x0;
twid[62] = 0x100;
twid[63] = 0x0;
twid[64] = 0x100;
twid[65] = 0x0;
twid[66] = 0x100;
twid[67] = 0x0;
twid[68] = 0x100;
twid[69] = 0x0;
twid[70] = 0x100;
twid[71] = 0x0;
twid[72] = 0x100;
twid[73] = 0x0;
twid[74] = 0x100;
twid[75] = 0x0;
twid[76] = 0x100;
twid[77] = 0x0;
twid[78] = 0x100;
twid[79] = 0x0;
twid[80] = 0x100;
twid[81] = 0x0;
twid[82] = 0x100;
twid[83] = 0x0;

15
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[84] = 0x100;
twid[85] = 0x0;
twid[86] = 0x100;
twid[87] = 0x0;
twid[88] = 0x100;
twid[89] = 0x0;
twid[90] = 0x100;
twid[91] = 0x0;
twid[92] = 0x100;
twid[93] = 0x0;
twid[94] = 0x100;
twid[95] = 0x0;
twid[96] = 0x100;
twid[97] = 0x0;
twid[98] = 0x100;
twid[99] = 0x0;
twid[100] = 0x100;
twid[101] = 0x0;
twid[102] = 0x100;
twid[103] = 0x0;
twid[104] = 0x100;
twid[105] = 0x0;
twid[106] = 0x100;
twid[107] = 0x0;
twid[108] = 0x100;
twid[109] = 0x0;
twid[110] = 0x100;
twid[111] = 0x0;
twid[112] = 0x100;
twid[113] = 0x0;
twid[114] = 0x100;
twid[115] = 0x0;
twid[116] = 0x100;
twid[117] = 0x0;
twid[118] = 0x100;
twid[119] = 0x0;
twid[120] = 0x100;
twid[121] = 0x0;
twid[122] = 0x100;
twid[123] = 0x0;
twid[124] = 0x100;
twid[125] = 0x0;
twid[126] = 0x100;
twid[127] = 0x0;
twid[128] = 0x100;
twid[129] = 0x0;
twid[130] = 0x100;
twid[131] = 0x0;
twid[132] = 0x100;
twid[133] = 0x0;

16
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[134] = 0x100;
twid[135] = 0x0;
twid[136] = 0x100;
twid[137] = 0x0;
twid[138] = 0x100;
twid[139] = 0x0;
twid[140] = 0x100;
twid[141] = 0x0;
twid[142] = 0x100;
twid[143] = 0x0;
twid[144] = 0x100;
twid[145] = 0x0;
twid[146] = 0x100;
twid[147] = 0x0;
twid[148] = 0x100;
twid[149] = 0x0;
twid[150] = 0x100;
twid[151] = 0x0;
twid[152] = 0x100;
twid[153] = 0x0;
twid[154] = 0x100;
twid[155] = 0x0;
twid[156] = 0x100;
twid[157] = 0x0;
twid[158] = 0x100;
twid[159] = 0x0;
twid[160] = 0x100;
twid[161] = 0x0;
twid[162] = 0x100;
twid[163] = 0x0;
twid[164] = 0x100;
twid[165] = 0x0;
twid[166] = 0x100;
twid[167] = 0x0;
twid[168] = 0x100;
twid[169] = 0x0;
twid[170] = 0x100;
twid[171] = 0x0;
twid[172] = 0x100;
twid[173] = 0x0;
twid[174] = 0x100;
twid[175] = 0x0;
twid[176] = 0x100;
twid[177] = 0x0;
twid[178] = 0x100;
twid[179] = 0x0;
twid[180] = 0x100;
twid[181] = 0x0;
twid[182] = 0x100;
twid[183] = 0x0;

17
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[184] = 0x100;
twid[185] = 0x0;
twid[186] = 0x100;
twid[187] = 0x0;
twid[188] = 0x100;
twid[189] = 0x0;
twid[190] = 0x100;
twid[191] = 0x0;
twid[192] = 0x0;
twid[193] = 0xffffff00;
twid[194] = 0x0;
twid[195] = 0xffffff00;
twid[196] = 0x0;
twid[197] = 0xffffff00;
twid[198] = 0x0;
twid[199] = 0xffffff00;
twid[200] = 0x0;
twid[201] = 0xffffff00;
twid[202] = 0x0;
twid[203] = 0xffffff00;
twid[204] = 0x0;
twid[205] = 0xffffff00;
twid[206] = 0x0;
twid[207] = 0xffffff00;
twid[208] = 0x0;
twid[209] = 0xffffff00;
twid[210] = 0x0;
twid[211] = 0xffffff00;
twid[212] = 0x0;
twid[213] = 0xffffff00;
twid[214] = 0x0;
twid[215] = 0xffffff00;
twid[216] = 0x0;
twid[217] = 0xffffff00;
twid[218] = 0x0;
twid[219] = 0xffffff00;
twid[220] = 0x0;
twid[221] = 0xffffff00;
twid[222] = 0x0;
twid[223] = 0xffffff00;
twid[224] = 0x0;
twid[225] = 0xffffff00;
twid[226] = 0x0;
twid[227] = 0xffffff00;
twid[228] = 0x0;
twid[229] = 0xffffff00;
twid[230] = 0x0;
twid[231] = 0xffffff00;
twid[232] = 0x0;
twid[233] = 0xffffff00;

18
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[234] = 0x0;
twid[235] = 0xffffff00;
twid[236] = 0x0;
twid[237] = 0xffffff00;
twid[238] = 0x0;
twid[239] = 0xffffff00;
twid[240] = 0x0;
twid[241] = 0xffffff00;
twid[242] = 0x0;
twid[243] = 0xffffff00;
twid[244] = 0x0;
twid[245] = 0xffffff00;
twid[246] = 0x0;
twid[247] = 0xffffff00;
twid[248] = 0x0;
twid[249] = 0xffffff00;
twid[250] = 0x0;
twid[251] = 0xffffff00;
twid[252] = 0x0;
twid[253] = 0xffffff00;
twid[254] = 0x0;
twid[255] = 0xffffff00;
twid[256] = 0x100;
twid[257] = 0x0;
twid[258] = 0x100;
twid[259] = 0x0;
twid[260] = 0x100;
twid[261] = 0x0;
twid[262] = 0x100;
twid[263] = 0x0;
twid[264] = 0x100;
twid[265] = 0x0;
twid[266] = 0x100;
twid[267] = 0x0;
twid[268] = 0x100;
twid[269] = 0x0;
twid[270] = 0x100;
twid[271] = 0x0;
twid[272] = 0x100;
twid[273] = 0x0;
twid[274] = 0x100;
twid[275] = 0x0;
twid[276] = 0x100;
twid[277] = 0x0;
twid[278] = 0x100;
twid[279] = 0x0;
twid[280] = 0x100;
twid[281] = 0x0;
twid[282] = 0x100;
twid[283] = 0x0;

19
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[284] = 0x100;
twid[285] = 0x0;
twid[286] = 0x100;
twid[287] = 0x0;
twid[288] = 0xb5;
twid[289] = 0xffffff4b;
twid[290] = 0xb5;
twid[291] = 0xffffff4b;
twid[292] = 0xb5;
twid[293] = 0xffffff4b;
twid[294] = 0xb5;
twid[295] = 0xffffff4b;
twid[296] = 0xb5;
twid[297] = 0xffffff4b;
twid[298] = 0xb5;
twid[299] = 0xffffff4b;
twid[300] = 0xb5;
twid[301] = 0xffffff4b;
twid[302] = 0xb5;
twid[303] = 0xffffff4b;
twid[304] = 0xb5;
twid[305] = 0xffffff4b;
twid[306] = 0xb5;
twid[307] = 0xffffff4b;
twid[308] = 0xb5;
twid[309] = 0xffffff4b;
twid[310] = 0xb5;
twid[311] = 0xffffff4b;
twid[312] = 0xb5;
twid[313] = 0xffffff4b;
twid[314] = 0xb5;
twid[315] = 0xffffff4b;
twid[316] = 0xb5;
twid[317] = 0xffffff4b;
twid[318] = 0xb5;
twid[319] = 0xffffff4b;
twid[320] = 0x0;
twid[321] = 0xffffff00;
twid[322] = 0x0;
twid[323] = 0xffffff00;
twid[324] = 0x0;
twid[325] = 0xffffff00;
twid[326] = 0x0;
twid[327] = 0xffffff00;
twid[328] = 0x0;
twid[329] = 0xffffff00;
twid[330] = 0x0;
twid[331] = 0xffffff00;
twid[332] = 0x0;
twid[333] = 0xffffff00;

20
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[334] = 0x0;
twid[335] = 0xffffff00;
twid[336] = 0x0;
twid[337] = 0xffffff00;
twid[338] = 0x0;
twid[339] = 0xffffff00;
twid[340] = 0x0;
twid[341] = 0xffffff00;
twid[342] = 0x0;
twid[343] = 0xffffff00;
twid[344] = 0x0;
twid[345] = 0xffffff00;
twid[346] = 0x0;
twid[347] = 0xffffff00;
twid[348] = 0x0;
twid[349] = 0xffffff00;
twid[350] = 0x0;
twid[351] = 0xffffff00;
twid[352] = 0xffffff4b;
twid[353] = 0xffffff4b;
twid[354] = 0xffffff4b;
twid[355] = 0xffffff4b;
twid[356] = 0xffffff4b;
twid[357] = 0xffffff4b;
twid[358] = 0xffffff4b;
twid[359] = 0xffffff4b;
twid[360] = 0xffffff4b;
twid[361] = 0xffffff4b;
twid[362] = 0xffffff4b;
twid[363] = 0xffffff4b;
twid[364] = 0xffffff4b;
twid[365] = 0xffffff4b;
twid[366] = 0xffffff4b;
twid[367] = 0xffffff4b;
twid[368] = 0xffffff4b;
twid[369] = 0xffffff4b;
twid[370] = 0xffffff4b;
twid[371] = 0xffffff4b;
twid[372] = 0xffffff4b;
twid[373] = 0xffffff4b;
twid[374] = 0xffffff4b;
twid[375] = 0xffffff4b;
twid[376] = 0xffffff4b;
twid[377] = 0xffffff4b;
twid[378] = 0xffffff4b;
twid[379] = 0xffffff4b;
twid[380] = 0xffffff4b;
twid[381] = 0xffffff4b;
twid[382] = 0xffffff4b;
twid[383] = 0xffffff4b;

21
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[384] = 0x100;
twid[385] = 0x0;
twid[386] = 0x100;
twid[387] = 0x0;
twid[388] = 0x100;
twid[389] = 0x0;
twid[390] = 0x100;
twid[391] = 0x0;
twid[392] = 0x100;
twid[393] = 0x0;
twid[394] = 0x100;
twid[395] = 0x0;
twid[396] = 0x100;
twid[397] = 0x0;
twid[398] = 0x100;
twid[399] = 0x0;
twid[400] = 0xec;
twid[401] = 0xffffff9f;
twid[402] = 0xec;
twid[403] = 0xffffff9f;
twid[404] = 0xec;
twid[405] = 0xffffff9f;
twid[406] = 0xec;
twid[407] = 0xffffff9f;
twid[408] = 0xec;
twid[409] = 0xffffff9f;
twid[410] = 0xec;
twid[411] = 0xffffff9f;
twid[412] = 0xec;
twid[413] = 0xffffff9f;
twid[414] = 0xec;
twid[415] = 0xffffff9f;
twid[416] = 0xb5;
twid[417] = 0xffffff4b;
twid[418] = 0xb5;
twid[419] = 0xffffff4b;
twid[420] = 0xb5;
twid[421] = 0xffffff4b;
twid[422] = 0xb5;
twid[423] = 0xffffff4b;
twid[424] = 0xb5;
twid[425] = 0xffffff4b;
twid[426] = 0xb5;
twid[427] = 0xffffff4b;
twid[428] = 0xb5;
twid[429] = 0xffffff4b;
twid[430] = 0xb5;
twid[431] = 0xffffff4b;
twid[432] = 0x61;
twid[433] = 0xffffff14;

22
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[434] = 0x61;
twid[435] = 0xffffff14;
twid[436] = 0x61;
twid[437] = 0xffffff14;
twid[438] = 0x61;
twid[439] = 0xffffff14;
twid[440] = 0x61;
twid[441] = 0xffffff14;
twid[442] = 0x61;
twid[443] = 0xffffff14;
twid[444] = 0x61;
twid[445] = 0xffffff14;
twid[446] = 0x61;
twid[447] = 0xffffff14;
twid[448] = 0x0;
twid[449] = 0xffffff00;
twid[450] = 0x0;
twid[451] = 0xffffff00;
twid[452] = 0x0;
twid[453] = 0xffffff00;
twid[454] = 0x0;
twid[455] = 0xffffff00;
twid[456] = 0x0;
twid[457] = 0xffffff00;
twid[458] = 0x0;
twid[459] = 0xffffff00;
twid[460] = 0x0;
twid[461] = 0xffffff00;
twid[462] = 0x0;
twid[463] = 0xffffff00;
twid[464] = 0xffffff9f;
twid[465] = 0xffffff14;
twid[466] = 0xffffff9f;
twid[467] = 0xffffff14;
twid[468] = 0xffffff9f;
twid[469] = 0xffffff14;
twid[470] = 0xffffff9f;
twid[471] = 0xffffff14;
twid[472] = 0xffffff9f;
twid[473] = 0xffffff14;
twid[474] = 0xffffff9f;
twid[475] = 0xffffff14;
twid[476] = 0xffffff9f;
twid[477] = 0xffffff14;
twid[478] = 0xffffff9f;
twid[479] = 0xffffff14;
twid[480] = 0xffffff4b;
twid[481] = 0xffffff4b;
twid[482] = 0xffffff4b;
twid[483] = 0xffffff4b;

23
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[484] = 0xffffff4b;
twid[485] = 0xffffff4b;
twid[486] = 0xffffff4b;
twid[487] = 0xffffff4b;
twid[488] = 0xffffff4b;
twid[489] = 0xffffff4b;
twid[490] = 0xffffff4b;
twid[491] = 0xffffff4b;
twid[492] = 0xffffff4b;
twid[493] = 0xffffff4b;
twid[494] = 0xffffff4b;
twid[495] = 0xffffff4b;
twid[496] = 0xffffff14;
twid[497] = 0xffffff9f;
twid[498] = 0xffffff14;
twid[499] = 0xffffff9f;
twid[500] = 0xffffff14;
twid[501] = 0xffffff9f;
twid[502] = 0xffffff14;
twid[503] = 0xffffff9f;
twid[504] = 0xffffff14;
twid[505] = 0xffffff9f;
twid[506] = 0xffffff14;
twid[507] = 0xffffff9f;
twid[508] = 0xffffff14;
twid[509] = 0xffffff9f;
twid[510] = 0xffffff14;
twid[511] = 0xffffff9f;
twid[512] = 0x100;
twid[513] = 0x0;
twid[514] = 0x100;
twid[515] = 0x0;
twid[516] = 0x100;
twid[517] = 0x0;
twid[518] = 0x100;
twid[519] = 0x0;
twid[520] = 0xfb;
twid[521] = 0xffffffcf;
twid[522] = 0xfb;
twid[523] = 0xffffffcf;
twid[524] = 0xfb;
twid[525] = 0xffffffcf;
twid[526] = 0xfb;
twid[527] = 0xffffffcf;
twid[528] = 0xec;
twid[529] = 0xffffff9f;
twid[530] = 0xec;
twid[531] = 0xffffff9f;
twid[532] = 0xec;
twid[533] = 0xffffff9f;

24
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[534] = 0xec;
twid[535] = 0xffffff9f;
twid[536] = 0xd4;
twid[537] = 0xffffff72;
twid[538] = 0xd4;
twid[539] = 0xffffff72;
twid[540] = 0xd4;
twid[541] = 0xffffff72;
twid[542] = 0xd4;
twid[543] = 0xffffff72;
twid[544] = 0xb5;
twid[545] = 0xffffff4b;
twid[546] = 0xb5;
twid[547] = 0xffffff4b;
twid[548] = 0xb5;
twid[549] = 0xffffff4b;
twid[550] = 0xb5;
twid[551] = 0xffffff4b;
twid[552] = 0x8e;
twid[553] = 0xffffff2c;
twid[554] = 0x8e;
twid[555] = 0xffffff2c;
twid[556] = 0x8e;
twid[557] = 0xffffff2c;
twid[558] = 0x8e;
twid[559] = 0xffffff2c;
twid[560] = 0x61;
twid[561] = 0xffffff14;
twid[562] = 0x61;
twid[563] = 0xffffff14;
twid[564] = 0x61;
twid[565] = 0xffffff14;
twid[566] = 0x61;
twid[567] = 0xffffff14;
twid[568] = 0x31;
twid[569] = 0xffffff05;
twid[570] = 0x31;
twid[571] = 0xffffff05;
twid[572] = 0x31;
twid[573] = 0xffffff05;
twid[574] = 0x31;
twid[575] = 0xffffff05;
twid[576] = 0x0;
twid[577] = 0xffffff00;
twid[578] = 0x0;
twid[579] = 0xffffff00;
twid[580] = 0x0;
twid[581] = 0xffffff00;
twid[582] = 0x0;
twid[583] = 0xffffff00;

25
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[584] = 0xffffffcf;
twid[585] = 0xffffff05;
twid[586] = 0xffffffcf;
twid[587] = 0xffffff05;
twid[588] = 0xffffffcf;
twid[589] = 0xffffff05;
twid[590] = 0xffffffcf;
twid[591] = 0xffffff05;
twid[592] = 0xffffff9f;
twid[593] = 0xffffff14;
twid[594] = 0xffffff9f;
twid[595] = 0xffffff14;
twid[596] = 0xffffff9f;
twid[597] = 0xffffff14;
twid[598] = 0xffffff9f;
twid[599] = 0xffffff14;
twid[600] = 0xffffff72;
twid[601] = 0xffffff2c;
twid[602] = 0xffffff72;
twid[603] = 0xffffff2c;
twid[604] = 0xffffff72;
twid[605] = 0xffffff2c;
twid[606] = 0xffffff72;
twid[607] = 0xffffff2c;
twid[608] = 0xffffff4b;
twid[609] = 0xffffff4b;
twid[610] = 0xffffff4b;
twid[611] = 0xffffff4b;
twid[612] = 0xffffff4b;
twid[613] = 0xffffff4b;
twid[614] = 0xffffff4b;
twid[615] = 0xffffff4b;
twid[616] = 0xffffff2c;
twid[617] = 0xffffff72;
twid[618] = 0xffffff2c;
twid[619] = 0xffffff72;
twid[620] = 0xffffff2c;
twid[621] = 0xffffff72;
twid[622] = 0xffffff2c;
twid[623] = 0xffffff72;
twid[624] = 0xffffff14;
twid[625] = 0xffffff9f;
twid[626] = 0xffffff14;
twid[627] = 0xffffff9f;
twid[628] = 0xffffff14;
twid[629] = 0xffffff9f;
twid[630] = 0xffffff14;
twid[631] = 0xffffff9f;
twid[632] = 0xffffff05;
twid[633] = 0xffffffcf;

26
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[634] = 0xffffff05;
twid[635] = 0xffffffcf;
twid[636] = 0xffffff05;
twid[637] = 0xffffffcf;
twid[638] = 0xffffff05;
twid[639] = 0xffffffcf;
twid[640] = 0x100;
twid[641] = 0x0;
twid[642] = 0x100;
twid[643] = 0x0;
twid[644] = 0xfe;
twid[645] = 0xffffffe7;
twid[646] = 0xfe;
twid[647] = 0xffffffe7;
twid[648] = 0xfb;
twid[649] = 0xffffffcf;
twid[650] = 0xfb;
twid[651] = 0xffffffcf;
twid[652] = 0xf4;
twid[653] = 0xffffffb6;
twid[654] = 0xf4;
twid[655] = 0xffffffb6;
twid[656] = 0xec;
twid[657] = 0xffffff9f;
twid[658] = 0xec;
twid[659] = 0xffffff9f;
twid[660] = 0xe1;
twid[661] = 0xffffff88;
twid[662] = 0xe1;
twid[663] = 0xffffff88;
twid[664] = 0xd4;
twid[665] = 0xffffff72;
twid[666] = 0xd4;
twid[667] = 0xffffff72;
twid[668] = 0xc5;
twid[669] = 0xffffff5e;
twid[670] = 0xc5;
twid[671] = 0xffffff5e;
twid[672] = 0xb5;
twid[673] = 0xffffff4b;
twid[674] = 0xb5;
twid[675] = 0xffffff4b;
twid[676] = 0xa2;
twid[677] = 0xffffff3b;
twid[678] = 0xa2;
twid[679] = 0xffffff3b;
twid[680] = 0x8e;
twid[681] = 0xffffff2c;
twid[682] = 0x8e;
twid[683] = 0xffffff2c;

27
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[684] = 0x78;
twid[685] = 0xffffff1f;
twid[686] = 0x78;
twid[687] = 0xffffff1f;
twid[688] = 0x61;
twid[689] = 0xffffff14;
twid[690] = 0x61;
twid[691] = 0xffffff14;
twid[692] = 0x4a;
twid[693] = 0xffffff0c;
twid[694] = 0x4a;
twid[695] = 0xffffff0c;
twid[696] = 0x31;
twid[697] = 0xffffff05;
twid[698] = 0x31;
twid[699] = 0xffffff05;
twid[700] = 0x19;
twid[701] = 0xffffff02;
twid[702] = 0x19;
twid[703] = 0xffffff02;
twid[704] = 0x0;
twid[705] = 0xffffff00;
twid[706] = 0x0;
twid[707] = 0xffffff00;
twid[708] = 0xffffffe7;
twid[709] = 0xffffff02;
twid[710] = 0xffffffe7;
twid[711] = 0xffffff02;
twid[712] = 0xffffffcf;
twid[713] = 0xffffff05;
twid[714] = 0xffffffcf;
twid[715] = 0xffffff05;
twid[716] = 0xffffffb6;
twid[717] = 0xffffff0c;
twid[718] = 0xffffffb6;
twid[719] = 0xffffff0c;
twid[720] = 0xffffff9f;
twid[721] = 0xffffff14;
twid[722] = 0xffffff9f;
twid[723] = 0xffffff14;
twid[724] = 0xffffff88;
twid[725] = 0xffffff1f;
twid[726] = 0xffffff88;
twid[727] = 0xffffff1f;
twid[728] = 0xffffff72;
twid[729] = 0xffffff2c;
twid[730] = 0xffffff72;
twid[731] = 0xffffff2c;
twid[732] = 0xffffff5e;
twid[733] = 0xffffff3b;

28
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[734] = 0xffffff5e;
twid[735] = 0xffffff3b;
twid[736] = 0xffffff4b;
twid[737] = 0xffffff4b;
twid[738] = 0xffffff4b;
twid[739] = 0xffffff4b;
twid[740] = 0xffffff3b;
twid[741] = 0xffffff5e;
twid[742] = 0xffffff3b;
twid[743] = 0xffffff5e;
twid[744] = 0xffffff2c;
twid[745] = 0xffffff72;
twid[746] = 0xffffff2c;
twid[747] = 0xffffff72;
twid[748] = 0xffffff1f;
twid[749] = 0xffffff88;
twid[750] = 0xffffff1f;
twid[751] = 0xffffff88;
twid[752] = 0xffffff14;
twid[753] = 0xffffff9f;
twid[754] = 0xffffff14;
twid[755] = 0xffffff9f;
twid[756] = 0xffffff0c;
twid[757] = 0xffffffb6;
twid[758] = 0xffffff0c;
twid[759] = 0xffffffb6;
twid[760] = 0xffffff05;
twid[761] = 0xffffffcf;
twid[762] = 0xffffff05;
twid[763] = 0xffffffcf;
twid[764] = 0xffffff02;
twid[765] = 0xffffffe7;
twid[766] = 0xffffff02;
twid[767] = 0xffffffe7;
twid[768] = 0x100;
twid[769] = 0x0;
twid[770] = 0xff;
twid[771] = 0xfffffff4;
twid[772] = 0xfe;
twid[773] = 0xffffffe7;
twid[774] = 0xfd;
twid[775] = 0xffffffdb;
twid[776] = 0xfb;
twid[777] = 0xffffffcf;
twid[778] = 0xf8;
twid[779] = 0xffffffc2;
twid[780] = 0xf4;
twid[781] = 0xffffffb6;
twid[782] = 0xf1;
twid[783] = 0xffffffaa;

29
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[784] = 0xec;
twid[785] = 0xffffff9f;
twid[786] = 0xe7;
twid[787] = 0xffffff93;
twid[788] = 0xe1;
twid[789] = 0xffffff88;
twid[790] = 0xdb;
twid[791] = 0xffffff7d;
twid[792] = 0xd4;
twid[793] = 0xffffff72;
twid[794] = 0xcd;
twid[795] = 0xffffff68;
twid[796] = 0xc5;
twid[797] = 0xffffff5e;
twid[798] = 0xbd;
twid[799] = 0xffffff55;
twid[800] = 0xb5;
twid[801] = 0xffffff4b;
twid[802] = 0xab;
twid[803] = 0xffffff43;
twid[804] = 0xa2;
twid[805] = 0xffffff3b;
twid[806] = 0x98;
twid[807] = 0xffffff33;
twid[808] = 0x8e;
twid[809] = 0xffffff2c;
twid[810] = 0x83;
twid[811] = 0xffffff25;
twid[812] = 0x78;
twid[813] = 0xffffff1f;
twid[814] = 0x6d;
twid[815] = 0xffffff19;
twid[816] = 0x61;
twid[817] = 0xffffff14;
twid[818] = 0x56;
twid[819] = 0xffffff0f;
twid[820] = 0x4a;
twid[821] = 0xffffff0c;
twid[822] = 0x3e;
twid[823] = 0xffffff08;
twid[824] = 0x31;
twid[825] = 0xffffff05;
twid[826] = 0x25;
twid[827] = 0xffffff03;
twid[828] = 0x19;
twid[829] = 0xffffff02;
twid[830] = 0xc;
twid[831] = 0xffffff01;
twid[832] = 0x0;
twid[833] = 0xffffff00;

30
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[834] = 0xfffffff4;
twid[835] = 0xffffff01;
twid[836] = 0xffffffe7;
twid[837] = 0xffffff02;
twid[838] = 0xffffffdb;
twid[839] = 0xffffff03;
twid[840] = 0xffffffcf;
twid[841] = 0xffffff05;
twid[842] = 0xffffffc2;
twid[843] = 0xffffff08;
twid[844] = 0xffffffb6;
twid[845] = 0xffffff0c;
twid[846] = 0xffffffaa;
twid[847] = 0xffffff0f;
twid[848] = 0xffffff9f;
twid[849] = 0xffffff14;
twid[850] = 0xffffff93;
twid[851] = 0xffffff19;
twid[852] = 0xffffff88;
twid[853] = 0xffffff1f;
twid[854] = 0xffffff7d;
twid[855] = 0xffffff25;
twid[856] = 0xffffff72;
twid[857] = 0xffffff2c;
twid[858] = 0xffffff68;
twid[859] = 0xffffff33;
twid[860] = 0xffffff5e;
twid[861] = 0xffffff3b;
twid[862] = 0xffffff55;
twid[863] = 0xffffff43;
twid[864] = 0xffffff4b;
twid[865] = 0xffffff4b;
twid[866] = 0xffffff43;
twid[867] = 0xffffff55;
twid[868] = 0xffffff3b;
twid[869] = 0xffffff5e;
twid[870] = 0xffffff33;
twid[871] = 0xffffff68;
twid[872] = 0xffffff2c;
twid[873] = 0xffffff72;
twid[874] = 0xffffff25;
twid[875] = 0xffffff7d;
twid[876] = 0xffffff1f;
twid[877] = 0xffffff88;
twid[878] = 0xffffff19;
twid[879] = 0xffffff93;
twid[880] = 0xffffff14;
twid[881] = 0xffffff9f;
twid[882] = 0xffffff0f;
twid[883] = 0xffffffaa;

31
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

twid[884] = 0xffffff0c;
twid[885] = 0xffffffb6;
twid[886] = 0xffffff08;
twid[887] = 0xffffffc2;
twid[888] = 0xffffff05;
twid[889] = 0xffffffcf;
twid[890] = 0xffffff03;
twid[891] = 0xffffffdb;
twid[892] = 0xffffff02;
twid[893] = 0xffffffe7;
twid[894] = 0xffffff01;
twid[895] = 0xfffffff4;

if(inv == 1)
{
for(i=0;i<180;i++)
{
if((i%2) != 0)
{
twid[i] = (-1)*twid[i];
}
}
}

j = 1;
for(i=1;i<N2;i+=2)
{

if(j>i)
{
{temp=x[j];x[j]=x[i];x[i]=temp;}
{temp=x[j-1];x[j-1]=x[i-1];x[i-1]=temp;}
}
m = N2>>1;
while(m >= 2 && j>m)
{
j-=m;
m>>=1;
}
j+=m;
}
k = 0;
for(l=2;l<=N;l=l<<1)
{
le1 = 2*l;
for(p=0;p<l;p+=2)
{
i = p;
while(i<N2)
{

32
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

j = i + l;
ir = x[j];
ii = x[j+1];
tr = twid[k++];
ti = twid[k++];
x[j] = (ir*tr) - (ii*ti);
x[j+1] = (ir*ti) + (ii*tr);
x[j] = x[j] >> 8;
x[j+1] = x[j+1] >> 8;
ar = x[i];
ai = x[i+1];
br = x[j];
bi = x[j+1]; x[i]
= ar + br; x[i+1]
= ai + bi; x[j] =
ar - br; x[j+1] =
ai - bi;
i = i + le1;
}
}
}
if(inv == 1)
{
for(i=0;i<N2;i++)
x[i] = x[i]/N;
}

x = (int *)0x80001000;
out = (int *)0x80002000;

square calc(x,out);
while(1);
}

void square calc(int *w,int *o){

long t1,t2,t3,t4,c;

for(c=0;c<ORDER;c++){
t1 = *w++;
t2 = *w++;
t1 = t1 * t1;
t2 = t2 * t2;
t3 = t1 + t2;
t4 = sqrt(t3);
*o++ = (int)t4;
}
return;
}

33
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

void auto_corr(int *x_in,int *x_in_xx,unsigned int ac_n){

unsigned int ac_local,ac_index,ac_count,i,index;

int sum,temp,*xx;

// xx = (float *)malloc(2*ac_n);
xx = (int *)0x80090000;

ac_count = ac_n-1;

for(ac_index=0;ac_index<ac_count;ac_index++){
xx[ac_index] = 0;
xx[ac_index+ac_n+ac_count] = 0;}

// ac_local = 0;
for(ac_index=0;ac_index<ac_n;ac_index++){
xx[ac_index+ac_count] = x_in[ac_index];
}

for(index=0;index<(2*ac_n)-1;index++){ sum=0;
for(ac_index=0;ac_index<ac_n;ac_index++){
temp = x_in[ac_index] * xx[ac_index];
sum = sum + temp;
x_in_xx[index] = sum;
}

for(i=0;i<(2*ac_count)+ac_n;i++)
xx[i] = xx[i+1];
}

// for make 2n-1 + 1

x_in_xx[index] = 0;

return;

void normalize(int *nor_a_input,int *n_a_output,unsigned int nor_n){

unsigned int nor_i;

for(nor_i=0;nor_i<nor_n;nor_i++){
n_a_output[nor_i] = nor_a_input[nor_i]/128;
}
return;
}

34
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

unsigned int max_find(int *a_input){

unsigned int mf_i,mf_threshold = 5000,ret_val=0;

for(mf_i=0;mf_i<ORDER;mf_i++){

if(a_input[mf_i]>mf_threshold){
ret_val = 1;
break;}
}

return(ret_val);

2.c MULTIRATE MULTIFILTER

#include "deci3.h"
#include "deci4.h"
#include <stdio.h>

/* Specifications for the filters used: fs = 8 KHz, fp1 = fp2 = 700 Hz, fs1 = 3000 Hz,
fs2 = 1000 Hz, dp1 = dp2 = 0.005, ds1 = ds2 = 0.001, N1 = 8, N2 = 37, M1 = M2 =
L2 = L1 = 2.

For every 4 samples read from the adc the following approximate times apply without
using any additional delays:

samples 1 and 3: 16 us, sample 2: 28 us, sample 4: 0.1 ms

sample 1 = indexSamp 1
sample 2 = indexSamp 2
sample 3 = indexSamp 3
sample 4 = indexSamp 0

This means that without using additional delays the samples are not read at the 8 Khz
rate.

Therefore appropriate delays are added for samples 1, 2, 3 and 4 so that each sample
would be read at a rate close to 8 KHz (0.125 ms).

*/
typedef unsigned int Uint32;
typedef int Int32;
typedef short Int16;
typedef unsigned short Uint16;
typedef unsigned char Uchar;
35
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Uint32 *inDeciM1;
Uint32 *inDeciM2;
Uint32 *inInterpL2;
Uint32 *inInterpL1;

Uint32 *storeL1;
Uint32 *outL1;

Int16 *fInterpL2;
Int16 *fInterpL1;
Uint16 adcOut;
Uint32 valueL1;
Int32 outValue;
Int32 filtCount;
Uchar indexL2;
Uchar indexL1;
Uchar indexInit;
Uchar indexSamp;
int deciM1(void);
int deciM2(void);
int interpL2(void);
int interpL1(void);

int main(void)
{

Uint32 *socValue;
Uint32 *adcValue;
Uint32 *dacValue;

Uint32 socRead;
Uchar *led;
Int32 tCount;

Uint32 countM1;
Uint32 countM2;
Uint32 countL1;
Uint32 countL2;

Uint32 *inTest;

socValue = (Uint32 *)0x9004000c;

adcValue = (Uint32 *)0x90040008;
dacValue = (Uint32 *)0x90040008;

fInterpL2 = (Int16 *)0x0000a000;

fInterpL1 = (Int16 *)0x0000b000;

36
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

inDeciM1 = (Uint32 *)0x00011000;

inDeciM2 = (Uint32 *)0x00012000;
inInterpL2 = (Uint32 *)0x00013000;
inInterpL1 = (Uint32 *)0x00014000;

storeL1= (Uint32 *)0x00016000;

outL1 = (Uint32 *)0x00017000;

led = (Uchar *)0x90040016;

inTest = (Uint32 *)0x00015000;

for(filtCount = 0; filtCount < 50; filtCount++)

*(inTest + filtCount) = filtCount + 0x300;

for(filtCount = 0; filtCount < 37; filtCount++)

*(fInterpL2 + filtCount) = *(fDeciM2 + filtCount) * 2;

for(filtCount = 0; filtCount < 8; filtCount++)

*(fInterpL1 + filtCount) = *(fDeciM1 + filtCount) * 2;

for(filtCount = 0; filtCount < 200; filtCount++)

{
*(inDeciM1 + filtCount) = 0;
*(inDeciM2 + filtCount) = 0;
*(inInterpL2 + filtCount) = 0;
*(inInterpL1 + filtCount) = 0;
}

indexL2 = 1;
indexL1 = 1;

countM1 = 1;
countM2 = 0;
countL2 = 0;
countL1 = 0;

indexSamp = 1;

while(1)
{

if(indexSamp == 0)
for(tCount = 0; tCount < 200; tCount++);
else if ((indexSamp == 1) || (indexSamp == 3))
for(tCount = 0; tCount < 900; tCount++);
else if (indexSamp == 2)
for(tCount = 0; tCount < 700; tCount++);

37
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

socRead = *socValue;
adcOut = *adcValue;

adcOut &= 0x0fff;

adcOut ^= 0x0800;

*inDeciM1 = adcOut;

if(countM1 == 2)
{ deciM1();
countM1 = 0;
countM2++;
}

if(countM2 == 2)
{ deciM2();
countM2 = 0;
}

if((countM1 == 0) && (countM2 == 0))

{
while(countL2 < 2)
{
interpL2();

for(filtCount = 36; filtCount >= 0; filtCount--)

*(inInterpL2 + filtCount + 1) = *(inInterpL2 + filtCount);

indexInit = 1;
countL2++;
}
}

storeL1= (Uint32 *)0x00016000;

if((countM1 == 0) && (countM2 == 0) && (countL2 == 2))

{
while(countL1 < 4)
{

if(countL1 == 0)
{
valueL1 = *storeL1;
*inInterpL1 = valueL1;
}

else if(countL1 == 2)

38
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

{
valueL1 = *(storeL1 + 1);
*inInterpL1 = valueL1;
}

interpL1();

for(filtCount = 7; filtCount >= 0; filtCount--)

*(inInterpL1 + filtCount + 1) = *(inInterpL1 + filtCount);

countL1++;
}
}

outL1 = (Uint32 *)0x00017000;

if(indexInit == 0)
outValue = 0x800;
else
outValue = *(outL1 + indexSamp);

*dacValue = outValue;

indexSamp++;

countL1 = 0;
countL2 = 0;

for(filtCount = 7; filtCount >= 0; filtCount--)

*(inDeciM1 + filtCount + 1) = *(inDeciM1 + filtCount);

countM1++;

if(indexSamp == 4)
indexSamp = 0;

return 0;

int deciM1(void)
{
for(filtCount = 36; filtCount >= 0; filtCount--)
*(inDeciM2 + filtCount + 1) = *(inDeciM2 + filtCount);

outValue = 0;

39
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

for(filtCount = 0; filtCount < 8; filtCount++)

outValue += *(inDeciM1 + filtCount) * *(fDeciM1 + filtCount);

outValue >>= 14;

*inDeciM2 = outValue;

return 0;
}
int deciM2(void)
{
outValue = 0;

for(filtCount = 0; filtCount < 37; filtCount++)

outValue += *(inDeciM2 + filtCount) * *(fDeciM2 + filtCount);

outValue >>= 14;

*inInterpL2 = outValue;

return 0;
}
int interpL2(void)
{
indexL2 ^= 0x01;

if(indexL2 == 0)
filtCount = 0;
else
filtCount = 1;

outValue = 0;

while(filtCount < 37)

{
outValue += *(inInterpL2 + filtCount) * *(fInterpL2 + filtCount);
filtCount += 2;
}

outValue >>= 16;

*storeL1++ = outValue;

return 0;

}
int interpL1(void)
{

40
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

indexL1 ^= 0x01;

if(indexL1 == 0)
filtCount = 0;
else
filtCount = 1;

outValue = 0;

while(filtCount < 8)
{
outValue += *(inInterpL1 + filtCount) * *(fInterpL1 + filtCount);
filtCount += 2;
}

outValue >>= 16;

*outL1++ = outValue;
return 0;

RESULT:

Thus a program for adaptive filter, periodogram and

multistage multirate system using DSP processor are executed.
41
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SIMULATION OF QMF USING SIMULATION PACKAGE

Ex.No:3a
Date:

AIM
To design a QMF using simulation package(Matlab)

SOFTWARE REQUIRED

PC, MATLAB

ALGORITHM
Start the program.
Get the denominator coefficient.
Get the input sequence.
Get the intial condition vector.
Calculate first all pass, second all pass and time reversed output of
cascade.
Stop the program.

THEORY

In digital signal processing, a quadrature mirror filter is a filter

most commonly used to implement a filter bank that splits an input signal
into two bands. The resulting high-pass and low-pass signals are often
reduced by a factor of 2, giving a critically sampled two-channel
representation of the original signal.

Multirate filter banks are so named because they effectively alter

the sampling rate of a digital system, as indicated by the decimators
(downsamplers) following the analysis filters, A0 and A1, and the
expanders (upsamplers) preceding the synthesis filters, S0 and S1.
Properly designed analysis and synthesis filters combined with the
properties of decimation and expansion allow filter banks to partition a
wideband input signal into multiple frequency bands (often called
subbands or channels) and to recombine these subband signals back into
the original signal. In the case of Figure a, the analysis filters, A 0 and A1,
are typically complementary lowpass and highpass filters that mirror each
other about the digital freque

one fourth the sampling frequency.

42
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Figure. (a) Block diagram of a simple two-channel multirate system, and (b)
approximate magnitude responses of analysis filters, A0 and A1

PROGRAM

clear all;
a=input('Enter the denominator coefficient:');
N=length(a)-1;
k=[0:N];
b(1+k)=a(1+N-k);
x1=input('Enter the input seq:');
M=length(x1);
zi=input('Enter the intial condition vector:');
N=length(zi);
[yf1,zf1]=filter(b,a,x1,zi);
zf2=fliplr(zf1);
x2=fliplr(yf1);
yf2=filter(b,a,x2,zf2);
yf3=fliplr(yf2);
disp('Input=');
disp(x1);
disp('Output of first all pass=');
disp(yf1);
disp('Output of second all pass=');
disp(yf2);
disp('Time reversed output of cascade=');
disp(yf3);

43
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

OUTPUT
Enter the denominator coefficient:[1 3 5 7]
Enter the input seq:[4 6 8 0]
Enter the intial condition vector:[20 40 60]
Input=
4 6 8 0

Output of first all pass=

48 -42 44 -196

Output of second all pass=

-680 2048 -2034 684

Time reversed output 684 -2034 2048 -680

RESULT:
Thus the QMF was designed using simulation package and
its output is verified.

44
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SIMULATION OF DECIMATION AND INTERPOLATION

USING MATLAB
Ex.No:3b
Date:

AIM
To simulate decimation and interpolation by using simulation
package(Matlab).

SOFTWARE REQUIRED

MATLAB

THEORY

Digital Interpolation by a Factor of L

Consider a band-limited discrete-time signal x(m) with a base-band
spectrum X(f) as shown in Figure 1. The sampling rate can be increased
by a factor of L through interpolation of L1 samples between every two
samples of x(m). In the following it is shown that digital interpolation by
a factor of L can be achieved through a twostage process of:
(a) Insertion of L1 zeros in between every two samples and
(b) Low-pass filtering of the zero-inserted signal by a filter with a cutoff
frequency of Fs/2L, where Fs is the sampling rate.

45
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Digital Decimation by a Factor of L

Consider a band-limited discrete-time signal x(m) with a base-band
spectrum X(f). The sampling rate can be decreased by a factor of L
through discarding of L1 samples for every L samples of x(m). In the
following it is shown that digital decimation by a factor of L can be
achieved through a two-stage process of:
(a) Low-pass filtering of the zero-inserted signal by a filter with a cutoff
frequency of Fs/2L, where Fs is the sampling rate. This is the anti-
alisaing process.
(b) Discarding of L1 samples for every L samples.

PROGRAM
f=1;
n=0:1/30:1;
x=10*sin(2*pi*f*n);
subplot(3,1,1);
stem(x),title('sine wave');
xlabel('n--->');
ylabel('amp---->');
y=interp(x,2);
subplot(3,1,2);
stem(y);
title('interpolated wave');
xlabel('n------>');
ylabel('amp---->');
y1=decimate(x,2);
subplot(3,1,3);
stem(y1);
title('decimated wave');
xlabel('n--->');
ylabel('amp--->');

46
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

OUTPUT
sine wave
10
amp---->

-10
0 5 10 15 20 25 30 35
n--->
interpolated wave
10
amp---->

-10
0 10 20 30 40 50 60 70
n------>
decimated wave
10
amp--->

-10
0 2 4 6 8 10 12 14 16
n--->

RESULT
Thus the decimation and interpolation was designed using
simulation package and its output is verified.

47
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

MODELING OF SEQUENTIAL DIGITAL SYSTEM USING VERILOG

Ex:No:4
Date:

AIM
To design the following sequential circuits and to verify its
input & output characteristics using verilog(Xilinx).
a )SR Flipflop b) JK Flipflop c) D-flipflop,
d) T-flipflop, e) Register f) Shift Register
g) PIPO shift register h)synchronous counter i)asynchoronous counter
j) up counter k) Down counter l) Up doun counter
m) ring counter

SOFTWARE REQUIRED
Xilinx

PROCEDURE

Open project navigator.

Go to the file and click the new project
Type the project name
The property wizard is open to check all properties such as
product, categories, family, device etc. then click next
Create new source, the wizard appears then click next
Project summary is displayed then click next
Go to the project and click new source
Then type the full name XXXX as well as select verilog module
then click next
Define module window here we assign the input and output
clicks next and click finish
Type the program and save it
Make sure that the source is in BEHAVIOUR
Synthesize the program and check for errors.
Creation of test bench waveform
Open project new source, then select test bench waveform and
give a file name click next.
Then click the ISE simulator and view the signal window
Force the input data corresponding circuit.
Simulate the program using ISE simulator.

48
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

THEORY

SR Flipflop

Its inputs, Set and Reset, provide the means for changing the state,
Q, of the circuit. When both inputs, R and S, are equal to 0 the latch
maintains its existing state. This state may be either Qa = 0 and Qb = 1,
or Qa = 1and Qb = 0, which is indicated in the truth table by stating that
the Qa and Qb outputs have values 0/1 and 1/0, respectively. Observe that
Qa and Qb are complements of each other in this case. When R = 0 and S
= 1, the latch is set into a state where Qa = 1 and Qb = 0.When R = 1 and
S = 0, the latch is reset into a state where Qa = 0 and Qb = 1. The fourth
possibility is to have R = S = 1. In this case both Qa and Qb will be 0.

D Flipflop
It has a single data input, called D, and it stores the value on this
input, under the control of a clock signal. It is called a gated D latch.
shows the circuit for a gated D latch. It is based on the gated SR latch, but
instead of using the S and R inputs separately, it has just one data input,

49
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

D. For convenience we have labeled the points in the circuit that are
equivalent to the S and R inputs. If D = 1, then S = 1 and R = 0, which
forces the latch into the state Q = 1. If D = 0, then S = 0 and R = 1, which
causes Q = 0. Of course, the changes in state occur only when Clk = 1. It
is important to observe that in this circuit it is impossible to have the
troublesome
situation where S = R = 1. In the gated D latch, the output Q merely
tracks the value of the input D while Clk = 1. As soon as Clk goes to 0,
the state of the latch is frozen until the next time the clock signal goes to
1. Therefore, the gated D latch stores the value of the D input seen at the
time the clock changes from 1 to 0.

T Flipflop

50
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

By including some simple logic circuitry to drive its input, the D

flip-flop may appear to be a different type of storage element. An
interesting modification is presented in Figure . This circuit uses a
positive-edge-triggered D flip-flop.The feedback connections make the
input signal D equal to either the value of Q or Q under the control of the
signal that is labeled T. On each positive edge of the clock, the flip-flop
may change its state Q(t). If T = 0, then D = Q and the state will remain
the same, that is, Q(t + 1) = Q(t). But if T = 1, then D = Q and the new
state will be Q(t + 1) = Q(t). Therefore, the overall operation of the circuit
is that it retains its present state if T = 0, and it reverses its present state if
T = 1. The operation of the circuit is specified in the form of a truth table
in Figure
Any circuit that implements this truth table is called a T flip-flop.
The name T flip-flopderives from the behavior of the circuit, which
toggles its state when T = 1. The togglefeature makes the T flip-flop a
useful element for building counter circuits

JK Flipflop

Instead of using a single control input, T, we can use two inputs, J and K,
as indicated in Figure. For this circuit the input D is defined as
D = JQ + KQ

51
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

A corresponding truth table is given in Figure. The circuit is called

a JK flip-flop. It combines the behaviors of SR and T flip-flops in a useful
way. It behaves as the SR flip-flop, where J = S and K = R, for all input
values except J = K = 1. For the latter case, which has to be avoided in
the SR flip-flop, the JK flip-flop toggles its state like the T flip-flop. The
JK flip-flop is a versatile circuit. It can be used for straight storage
purposes, just like the D and SR flip-flops. But it can also serve as a T
flip-flop by connecting the J and K inputs together.

Registers
A flip-flop stores one bit of information. When a set of n flip-flops
is used to store n bits of information, such as an n-bit number, we refer to
these flip-flops as a register. A common clock is used for each flip-flop in
a register. he term register is merely a convenience for referring to n-bit
structures consisting of flip-flops.
Shift Register

Fig. shows a four-bit shift register that is used to shift its contents
one bitposition to the right. The data bits are loaded into the shift register
in a serial fashion using the In input. The contents of each flip-flop are
transferred to the next flip-flop at each positive edge of the clock.

52
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Counters
Design circuits that can increment or decrement a count by 1.
Counter circuits are used in digital systems for many purposes. They may
count the number of occurrences of certain events, generate timing
intervals for control of various tasks in a system, keep track of time
elapsed between specific events, and so on.
counter circuits can be designed using T and D flip-flops.

Asynchronous counters
Only the first flip-flop is clocked by an external clock. All
subsequent flip-flops are clocked by the output of the preceding flip-
flop.Asynchronous counters are slower than synchronous counters
because of the delay in the transmission of the pulses from flip-flop to
flip-flop.Asynchronous counters are also called ripple-counters because
of the way the clock pulse ripples it way through the flip-flops.

Synchronous Counters
The asynchronous counters are simple, but not very fast. If a
counter with a larger number of bits is constructed in this manner, then
the delays caused by the cascaded clocking scheme may become too long
to meet the desired performance
requirements. We can build a faster counter by clocking all flip-flops at
the same time, using the approach described below.

A 4-bit synchronous counter built from D-flipflops with carry-input

(count-enable) and carry-output. In this circuit, the single clock signal is
directly connected to all flipflops, so that all flipflops change state at the
same time.

Ex: Ring counter

It is possible to devise a counterlike circuit in which each flip-flop

reaches the state
Qi = 1 for exactly one count, while for all other counts Qi = 0. Then Qi
indicates directly an occurrence of the corresponding count. Actually,
since this does not represent binary numbers, it is better to say that the

53
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

outputs of the flips-flops represent a code. Such a circuit can be

constructed from a simple shift register, as indicated in Figure. The Q
output of the last stage in the shift register is fed back as the input to the
first stage, which creates a ring like structure. If a single 1 is injected into
the ring, this 1 will be shifted through the ring at successive clock cycles.
For example, in a four-bit structure, the possible codes
Q0Q1Q2Q3 will be 1000, 0100, 0010, and 0001

UP COUNTER
N
A synchronous binary counter counts from 0 to 2 -1, where N is
the number of bits/flip-flops in the counter. Each flip-flop is used to
represent one bit. The flip-flop in the lowest-order position is
complemented/toggled with every clock pulse and a flip-flop in any other
position is complemented on the next clock pulse provided all the bits in
the lower-order positions are equal to 1.

Take for example A4 A3 A2 A1 = 0011. On the next count, A4 A3 A2 A1 =

0100. A1, the lowest-order bit, is always complemented. A2 is
complemented because all the lower-order positions (A1 only in this case)
are 1's. A3 is also complemented because all the lower-order positions, A2
and A1 are 1's. But A4 is not complemented the lower-order positions, A3
A2 A1 = 011, do not give an all 1 condition. To implment a synchronous
counter, we need a flip-flop for every bit and an AND gate for every bit
except the first and the last bit. The diagram below shows the
implementation of a 4-bit synchronous up-counter.

54
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

In a binary up counter, a particular bit, except for the first bit, toggles if
all the lower-order bits are 1's. The opposite is true for binary down
counters. That is, a particular bit toggles if all the lower-order bits are 0's
and the first bit toggles on every pulse.

Taking an example, A4 A3 A2 A1 = 0100. On the next count, A4 A3 A2 A1

= 0011. A1, the lowest-order bit, is always complemented. A2 is
complemented because all the lower-order positions (A1 only in this case)
are 0's. A3 is also complemented because all the lower-order positions, A2
and A1 are 0's. But A4 is not complemented the lower-order positions, A3
A2 A1 = 011, do not give an all 0 condition.

Down Counter

The implementation of a synchronous binary down counter is exactly the

same as that of a synchronous binary up counter except that the inverted
output from each flip-flop is used. All the methods used improve a binary
up counter can be similarly applied here.

55
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Up/down counter

A counter that can change state in either direction, under the control of an
up/down selector input, is known as an up/down counter. When the
selector is in the up state, the counter increments its value. When the
selector is in the down state, the counter decrements the count.

3-bit Synchronous Binary Up/Down Counter

From the diagram, we can see that COUNT-UP and COUNT-DOWN are
used as control inputs to determine whether the normal flip-flop outputs
or the inverted ones are fed into the J-K inputs of the following flip-flops.
If neither is at logic level 1, the counter doesn't count and if both are at
logic level 1, all the bits of the counter toggle at every clock pulse. The
OR gate allows either of the two outputs which have been enabled to be
fed into the next flip-flop. As with the binary up and binary down
counter, the speed up techniques apply.

56
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

PROGRAM

4.a SR Flipflop
module srff(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk)
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end
endcase
end
endmodule

4.b.JK Flipflop

module jk(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=~q; q1=~q1; end
endcase

57
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

end
endmodule

4.c.D Flipflop
module dff(d, clk, q, qbar);
input d;
input clk;
output q;
output qbar;
reg q,qbar;
always@(posedge clk)
begin
q=d;
qbar=~d;
end
endmodule

4.d.T Flipflop
module tff(reset, clk, t, qn1);
input reset;
input clk;
input t;
output qn1;
reg qn1;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
qn1=0;
end
else
begin

58
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

qn1=~t;
end end
endmodule

4.f.4-bit Shift Register

module shift4(R, L, w, Clock, Q);
input [3:0] R;
input L, w, Clock;
output [3:0] Q;
reg [3:0] Q;
always @(posedge Clock)
if (L)
Q <= R;
else
begin
Q[0] <= Q[1];
Q[1] <= Q[2];
Q[2] <= Q[3];
Q[3] <= w;
end
endmodule

4.g.PIPO shift register

module pipo(din,clk,rst,dout);
input [3:0] din;
input clk,rst;
output [3:0] dout;
reg [3:0] dout;
always @(posedge clk or negedge rst)
begin
if(!rst)

59
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

begin
dout <= 4'b0;
end
else
begin
dout <= din;
end end
endmodule

4.h.Synchronous counter-2 bit

module Count2Bit(Clock, Clear, out);
input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))out=2'b00;
else out=out+1;
endmodule

4.i. Asynchronous Counter

module Ripple_Counter(Count,RST,A0,A1,A2,A3);
output A0,A1,A2,A3;
input Count,RST;
//add d0, d1, d2, d3 as instance for each D_FF:
D_FF d0(~A0,A0,Count,RST);
D_FF d1(~A1,A1,A0,RST);
D_FF d2(~A2,A2,A1,RST);
D_FF d3(~A3,A3,A2,RST);
endmodule

60
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

module D_FF(D,Q,CLK,RST);
output Q;
input D,CLK,RST;
reg Q;
always @ (posedge CLK or negedge RST)
if(~RST) Q=1'b0;
else Q=D;
endmodule

4.j. Up Counter
module upcounter(count,clk,n);
output [3:0] count;
input clk;
input [3:0] n;
reg [3:0] count;
initial
count=4'b0000;
always @(negedge clk)
count=(count==n)? 4'b0000:count+1'b1;
endmodule

4.k.Down Counter
module downcounter(count,clk,n);
output [3:0] count;
input clk;
input [3:0] n;
reg [3:0] count;
initial
count=4'b0000;
always @(negedge clk)
61
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

count=(count==4'b0000)? n:count-1'b1;
endmodule

4.l. Updown Counter

module up_dn(clk, u_d, n, a);
input clk;
input u_d;
input [3:0] n;
output [3:0] a;
reg [3:0] a;
initial a=4'b0000;
always @(negedge clk) a=(u_d)?((a==n)?4'b0000:a+1'b1):
((a==4'b0000)?n:a-1'b1); endmodule

4.m.Ring Counter
module dff(q,d,c);
output q;
input d,c;
reg q;
initial
q=1'b1;
always @ (posedge c)
q=d;
endmodule
module dff1(q,d,clk);
output q;
input d,clk;
reg q;
initial
q=1'b0;
62
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

always @ (posedge clk)

q=d;
endmodule
module ring(q,clk);
inout [3:0]q;
input clk;
dff u1(q[0],q[3],clk);
dff1 u2(q[1],q[0],clk);
dff1 u3(q[2],q[1],clk);
dff1 u4(q[3],q[2],clk);
endmodule

RESULT
Thus the sequential circuits are designed using verilog and its
output are verified.

63
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

MODELING OF SEQUENTIAL DIGITAL SYSTEM USING VHDL

Ex:No:5
Date:

AIM:-
To design the following sequential circuits and to verify its
input & output characteristics using verilog(Xilinx).
a )SR Flipflop b) JK Flipflop c) D-flipflop d) T-
flipflop

SOFTWARE REQUIRED:-
Xilinx

PROCEDURE
Open project navigator.
Go to the file and click the new project
Type the project name
The property wizard is open to check all properties such as
product, categories, family, device etc. then click next
Create new source, the wizard appears then click next
Project summary is displayed then click next
Go to the project and click new source
Then type the full name XXXX as well as select vhdl module
then click next
Define module window here we assign the input and output
clicks next and click finish
Type the program and save it
Make sure that the source is in BEHAVIOUR
Synthesize the program and check for errors.
Creation of test bench waveform
Open project new source, then select test bench waveform and
give a file name click next.
Then click the ISE simulator and view the signal window
Force the input data corresponding circuit.
Simulate the program using ISE simulator.

64
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SR Flipflop

Its inputs, Set and Reset, provide the means for changing the state, Q, of
the circuit. When both inputs, R and S, are equal to 0 the latch maintains
its existing state. This state may be either Qa = 0 and Qb = 1, or Qa =
1and Qb = 0, which is indicated in the truth table by stating that the Qa
and Qb outputs have values 0/1 and 1/0, respectively. Observe that Qa
and Qb are complements of each other in this case. When R = 0 and S =
1, the latch is set into a state where Qa = 1 and Qb = 0.When R = 1 and S
= 0, the latch is reset into a state where Qa = 0 and Qb = 1. The fourth
possibility is to have R = S = 1. In this case both Qa and Qb will be 0.

D Flipflop
It has a single data input, called D, and it stores the value on this
input, under the control of a clock signal. It is called a gated D latch.
shows the circuit for a gated D latch. It is based on the gated SR latch, but
instead of using the S and R inputs separately, it has just one data input,
D. For convenience we have labeled the points in the circuit that are
equivalent to the S and R inputs. If D = 1, then S = 1 and R = 0, which

65
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

forces the latch into the state Q = 1. If D = 0, then S = 0 and R = 1, which

causes Q = 0. Of course, the changes in state occur only when Clk = 1. It
is important to observe that in this circuit it is impossible to have the
troublesome situation where S = R = 1. In the gated D latch, the output Q
merely tracks the value of the input D while Clk = 1. As soon as Clk goes
to 0, the state of the latch is frozen until the next time the clock signal
goes to 1. Therefore, the gated D latch stores the value of the D input
seen at the time the clock changes from 1 to 0.

T Flipflop

66
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

By including some simple logic circuitry to drive its input, the D

flip-flop may appear to be a different type of storage element. An
interesting modification is presented in Figure . This circuit uses a
positive-edge-triggered D flip-flop.The feedback connections make the
input signal D equal to either the value of Q or Q under the control of the
signal that is labeled T. On each positive edge of the clock, the flip-flop
may change its state Q(t). If T = 0, then D = Q and the state will remain
the same, that is, Q(t + 1) = Q(t). But if T = 1, then D = Q and the new
state will be Q(t + 1) = Q(t). Therefore, the overall operation of the circuit
is that it retains its present state if T = 0, and it reverses its present state if
T = 1. The operation of the circuit is specified in the form of a truth table
in Figure
Any circuit that implements this truth table is called a T flip-flop.
The name T flip-flopderives from the behavior of the circuit, which
toggles its state when T = 1. The togglefeature makes the T flip-flop a
useful element for building counter circuits

JK Flipflop

Instead of using a single control input, T, we can use two inputs, J and K,
as indicated in Figure. For this circuit the input D is defined as
D = JQ + KQ

A corresponding truth table is given in Figure. The circuit is called a JK

flip-flop. It

67
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

combines the behaviors of SR and T flip-flops in a useful way. It behaves

as the SR flip-flop, where J = S and K = R, for all input values except J =
K = 1. For the latter case, which has to be avoided in the SR flip-flop, the
JK flip-flop toggles its state like the T flip-flop. The JK flip-flop is a
versatile circuit. It can be used for straight storage purposes, just like the
D and SR flip-flops. But it can also serve as a T flip-flop by connecting
the J and K inputs together.

PROGRAM
5.aSR Flipflop
library ieee;
use ieee.std_logic_1164.all;
entity RS_FF is port (clk,rst,R,S:in std_logic;
Q, Qbar:inout std_logic);
end RS_FF;
----------------------------------------------------
architecture arch_RS_FF of RS_FF is
Begin
process(R,S,clk,rst)
begin
if(rst='1')then
Q<='Z';
Qbar<='Z';
elsif(clk'event and clk='1')then
if(S='0' and R='0')then
Q<=Q;
Qbar<=not Q;
elsif(S='0' and R='1')then
Q<='0';
Qbar<='1';
elsif(S='1' and R='0')then
Q<='1';
Qbar<='0';
elsif(S='1' and R='1')then
Q<='Z';
Qbar<='Z';
end if;
end if;
end process;
end arch_RS_FF;

68
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

5.b.JK Flipflop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JK_FF is
port (clk,rst,J,K:in std_logic;
Q, Qbar:inout std_logic);
end JK_FF;
----------------------------------------------------
architecture arch_JK_FF of JK_FF is
Begin
process(J,K,clk,rst)
begin
if(rst='1')then
Q<='Z';
Qbar<='Z';
elsif(clk'event and clk='1')then
if(J='0' and K='0')then
Q<=Q;
Qbar<=not Q;
elsif(J='0' and K='1')then
Q<='0';
Qbar<='1';
elsif(J='1' and K='0')then
Q<='1';
Qbar<='0';
elsif(J='1' and K='1')then
Q<=not Q;
Qbar<=Q;
end if;
end if;
end process;
end arch_JK_FF;

69
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

5.c.D Flipflop
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------
entity dff is port (clk,reset,d:in std_logic;
q:out std_logic);
end dff;
-----------------------------------------------
architecture arch_dff of dff is
begin
process (d,clk,reset)
begin
if(reset='1') then
q<='0';
elsif(clk'event and clk='1') then
q<=d;
end if;
end process;
end arch_dff;

5.d.T Flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is port (clk,reset,t:in std_logic;
q:out std_logic);
end tff;
architecture arch_tff of tff is

70
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

begin
process (t,clk,reset)
begin
if (reset='1') then
q<='0';
elsif (clk'event and clk='1') then
q<=not t;
end if;
end process;
end arch_tff;

RESULT
Thus the sequential circuits are designed using vhdl and its output
are verified.

71
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

DESIGN AND IMPEMENTATION OF ALU USING FPGA

Ex:No:6
Date:

AIM
To design and implement ALU verify its input & output
characteristics using FPGA(Xilinx).

APPARATUS/SOFTWARE REQUIRED
Xilinx Software
FPGA Kit
PC

THEORY

Arithmetic and Logic Unit (ALU) is a digital circuit that

performs arithmetic and logical operations. The ALU is a fundamental
building block of the central processing unit of a computer, and even the
simplest microprocessors contain one for purposes such as maintaining
timers. The processors found inside modern CPUs and graphics
processing units (GPUs) accommodate very powerful and very complex
ALUs; a single component may contain a number of ALUs.

PROCEDURE

Open project navigator.

Go to the file and click the new project
Type the project name
The property wizard is open to check all properties such as
product, categories, family, device etc. then click next
Create new source, the wizard appears then click next
Project summary is displayed then click next
Go to the project and click new source
Then type the full name XXXX as well as select verilog module
then click next
Define module window here we assign the input and output
clicks next and click finish
Type the program and save it

72
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

Select the synthesis implementation.It has to process if we have no

error.
Assign pin packages from user constraint.
Generate programming file.
Dowload the program to FPGA Kit and execute.

PROGRAM
6.b 2 bit-ALU
module alu(a, b, f, c);
input [1:0] a;
input [1:0] b;
input [1:0] f;
output [1:0] c;
reg [1:0] c;
always@(a or b or f)
begin
case(f)
2'b00: c=a+b;
2'b01: c=a-b;
2'b10: c=a&b;
2'b11: c=a|b;
endcase
end
endmodule

6.b 3-bit ALU

module alu(a, b, c, sel);
input a;
input b;
input [2:0]sel;
output c;
reg c;
always @(a or b or sel)
case (sel)
3'b000 : begin
c=a+b;
end
3'b001 : begin
c=a-b;
end
73
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

3'b010 : begin
c=a*b;
end
3'b011 : begin
c=a&b;
end
3'b100 : begin
c=a|b;
end
3'b101 : begin
c=a^b;
end
3'b110 : begin
c=~b;
end
3'b111 : begin
c=1'b0;
end
endcase
endmodule

RESULT
Thus ALU was designed using Verilog(Xilinx) and
implemented using FPGA its and output is verified.

74
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SIMULATION OF NMOS, PMOS & CMOS CITCUITS USING SPICE

ExNo:7
Date:

AIM

To design a NMOS,PMOS,CMOS inverter circuit and obtain its

waveform using pspice

APPARATUS /SOFTWARE REQUIRED

PSPICE software
PC

THEORY

NMOS Transistors

N-type metal-oxide-semiconductor logic uses n-type metal-oxide-

semiconductor field effect transistors (MOSFETs) to implement logic
gates and other digital circuits. NMOS transistors have four modes of
operation: cut-off (or sub-threshold), triode, saturation (sometimes called
active), and velocity saturation.

The n-type MOSFETs are arranged in a so-called "pull-down

network" (PDN) between the logic gate output and negative supply
voltage, while a resistor is placed between the logic gate output and the
positive supply voltage. The circuit is designed such that if the desired
output is low, then the PDN will be active, creating a current path
between the negative supply and the output.

PMOS Transistors

P-type metal-oxide-semiconductor logic uses p-type metal-oxide-

semiconductor field effect transistors (MOSFETs) to implement logic
gates and other digital circuits. PMOS transistors have four modes of
operation: cut-off (or subthreshold), triode, saturation (sometimes called
75
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

active), and velocity saturation.The p-type MOSFETs are arranged in a

so-called "pull-up network" (PUN) between the logic gate output and
positive supply voltage, while a resistor is placed between the logic gate
output and the negative supply voltage. The circuit is designed such that
if the desired output is high, then the PUN will be active, creating a
current path between the positive supply and the output.

While PMOS logic is easy to design and manufacture (a MOSFET

can be made to operate as a resistor, so the whole circuit can be made
with PMOS FETs), it has several shortcomings as well. The worst
problem is that a DC current flows through a PMOS logic gate when the
PUN is active, that is whenever the output is high. This leads to static
power dissipation even when the circuit sits idle.

Also, PMOS circuits are slow to transition from high to low. When
transitioning from low to high, the transistors provide low resistance, and
the capacitative charge at the output accumulates very quickly (similar to
charging a capacitor through a very low resistor). But the resistance
between the output and the negative supply rail is much greater, so the
high to low transition takes longer (similar to discharge a capacitor
through a high resistor value). Using a resistor of lower value will speed
up the process but also increases static power dissipation. Additionally,
the asymmetric input logic levels make PMOS circuits susceptible to
noise.

Though initially easier to manufacture, PMOS logic was later

supplanted by NMOS logic because NMOS is faster than PMOS. Modern
fabs use CMOS, which uses both PMOS and NMOS transistors together.
Static CMOS logic leverages the advantages of both by using NMOS and
PMOS together in the wafer.

CMOS Inverter

Complementary metaloxidesemiconductor (CMOS) is a

technology for constructing integrated circuits. CMOS technology is used
in microprocessors, microcontrollers, static RAM, and other digital logic
76
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

circuits. CMOS technology is also used for several analog circuits such as
image sensors (CMOS sensor), data converters, and highly integrated
transceivers for many types of communication. CMOS is also sometimes
referred to as complementary-symmetry metaloxidesemiconductor (or
COS-MOS). The words "complementary-symmetry" refer to the fact that
the typical digital design style with CMOS uses complementary and
symmetrical pairs of p-type and n-type metal oxide semiconductor field
effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise

immunity and low static power consumption. Since one transistor of the
pair is always off, the series combination draws significant power only
momentarily during switching between on and off states. Consequently,
CMOS devices do not produce as much waste heat as other forms of
logic, for example transistor-transistor logic (TTL) or NMOS logic,
which normally have some standing current even when not changing
state. CMOS also allows a high density of logic functions on a chip. It
was primarily for this reason that CMOS became the most used
technology to be implemented in VLSI chips. The phrase "metaloxide
semiconductor" is a reference to the physical structure of certain field-
effect transistors, having a metal gate electrode placed on top of an oxide
insulator, which in turn is on top of a semiconductor material.

PROCEDURE
1)Launch PSpice Schematic Student by left-clicking your mouse on
StartPSpice StudentSchematics.
2) Click on menu FileNew, a new blank schematic sheet will appear as
below. Now you can design your circuit schematic on it.click on menu
FileSavetype it in File name row. Then click Save.

77
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

1. Design your circuit in schematics. This can be divided into following

substeps.
1.click on menu DrawGet new part
or click on the small shortcut icon of Get New Part Type the part
name
click Place and Close
VDC simple analog voltage source, R Resistor,
GND_ANALOGanalog ground

Mbreak: indicating its a MOS transistor,

N: indicating its NMOS,
P indicationg its a PMOS
3 or 4: indicating its 3 terminal or 4 terminal. 3 terminal
symbol is actually a 4-terminal symbol with its bulk (B) shorted to
source (S).
D: indicating its depleted device (threshold voltage Vth<0). If
D is not specified, its an enhanced NMOS device (threshold
voltage Vth>0). Generally we use enhanced instead of depleted
devices.
2). First insert all the parts without considering their values (for example,
place a resistor without considering the resistance value of it, etc.).
3). Make the necessary rotations for the parts, and move the parts to
appropriate locations.
4). Make all the necessary wire connections.Please click on the small
Draw Wire
Icon press the ESC button on your keyboard to exit wire
mode, and then click to selected the wrong wire and press delete button
on your keyboard to delete it.
Eg: Md,Ms,Mg in the transistor and click OK
5). Mark the nodes you are interested in with labels.
Eg: Md,Ms,Mg in the transistor and click OK

78
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

6). Set the values for all the parts, for example, the resistance values of
resistors, the width (W) and length (L) of transistor, etc.
7)click to select the part, and then click menu EditAttributes, you
would be
able to get the popup window. Give the value and click OK

2. Define the SPICE parameter for NMOS and PMOS transistors.

1. click the NMOS transistor M1 so that its color turns to red. Then click
menu EditModel, a popup window appear as follow.
2. click Edit Instance Model (ModelEditor) to open the model editor
window please delete the line of:
.model MbreakN-X NMOS
and replace it with:
.MODEL MbreakN-X NMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5
+ PHI = 0.7 VTO = 0.8 DELTA = 3.0
+ UO = 650 ETA = 3.0E-6 THETA = 0.1
+ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3
+ RSH = 0 NFS = 1E12 TPG = 1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5

for PMOS transistor

.MODEL MbreakP-X PMOS LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6
+ PHI = 0.7 VTO = -0.9 DELTA = 0.1
+ UO = 250 ETA = 0 THETA = 0.1
+ KP = 40E-6 VMAX = 5E4 KAPPA = 1
+ RSH = 0 NFS = 1E12 TPG = -1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10
+ CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5

3)click menu of ModelEditor window: FileSave as to save it as a

model library file in the same directory as your schematic file.
Note: Please ensure that you click on menu FileSave as instead of
FileSave, otherwise you will see following error. Please dont click
FileSave, instead, please click on FileSaveas.
4)Click on menu FileExit, you will close the ModelEditor window.

79
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

3. Setup analysis

1)click menuAnalysisSetup, a new popup window appears as below.

Since we need to perform transient analysis, please check Transient,DC
sweep,etc
2)change the Print Step to 0.1ms, the Final Time to 10ms.Now click
OK and click Close to close both popup windows.

4. Run the simulation.

click menu AnalysisSimulate. PSPICE will perform the transient

simulation and open an OrCAD PSPICE A/D Student Demo window.

5. Observe the simulation results (traces of signals) in OrCAD PSpice

A/D Demo.
1) click menu TraceAdd Traces in OrCAD PSpice A/D Demo. click
OK, and you will see the waveform window
To find VDS
VDS=V(Md)-V(Ms), Md and Ms are the node labels we marked before.

1)Click menu PlotAdd Plot to Window, a new blank plot will appear
in the window.
2)The SEL>> sign beside the blank plot indicates its the active plot,
that is, newly added signal trace will be displayed in thisplot.
3) Now click menu TraceAdd trace, in the popup window, click
V(Md) in left column,and then click - sign in the right column
(Analog Operations and Functions column), then againclick V(Ms) in the
left column, you will see expression V(Md)-V(Ms) shows up in the
TraceExpression line.

6. observe the values of voltage or current of each node directly in

schematic window.Please click on the windows task bar of Pspice
Schematics to come back to our schematicswindow, and click on the
V and I icons,

80
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

NMOS

OUTPUT

81
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

PMOS

OUTPUT

82
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

CMOS

RESULT
Thus the NMOS,PMOS, CMOSinverter circuits are designed and
its output waveforms are obtained using PSPICE.

83
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

SYSTEM DESIGN USING 16-BIT MICROPROCESSOR

Ex.NO:8
Date:

AIM
To write a program to interface STEPPER MOTOR, TRAFFIC LIGHT
CONTROLLER with 16-bit microprocessor.

APPARATUS REQUIRED
8086 kit
Stepper motor
Traffic light kit
Keyboard and power cables.

THEORY

STEPPER MOTOR INTERFACE

A motor in which the rotor is able to assume only discrete

stationary angular position is a stepper motor. The basic two -
phase motor has two pairs of stator poles with its own windings.
The excitation of any one winding generates a northand South Pole gets
induced at the diametrically opposite sides.T h e s t a t o r f r a m e
iscontinuous and magnetic field passes t
hrough
t h e cylindrical annular ring. The rotor magnetic system has two
end faces. The leftface is magnetized permanently as south pole
and right face as north pole. North pole structure is twisted with
respect to south pole structure such that south poleco mes in
between two north poles.Step angle is the mini mu m degree of
rotationassociated with single step. Revolution is the number of steps
needed to completeone rotation or 360 degree.

Traffic light controller

Traffic light controller interface module is designed to simulate the

function of four way traffic light controller. Combinations of red, amber
and green LEDs are provided to indicate Halt, Wait and Go signals for
vehicles. Combination of red and green LEDs are provided for
pedestrian crossing. 36 LEDs are arranged in the form of an intersection.

84
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

A typical junction is represented on the PCB with comprehensive

legend printing. At the left corner of each road, a group of five LEDs
(red, amber and 3 green) are arranged in the form of a T-section to
control the traffic of that road. Each road is named North (N), South(S),
East (E) and West (W). LEDs L1, L10, L19 & L28 (Red) are for the stop
signal for the vehicles on the road N, S, W, & E respectively. L2, L11,
L20 & L29 (Amber) indicates wait state for vehicles on the road N, S, W,
& E respectively. L3, L4 & L5 (Green) are for left, strait and right turn
for the vehicles on road S. similarly L12-L13-L14, L23-L22-L21 & L32-
L31-L30 simulates same function for the roads E, N, W respectively. A
total of 16 LEDs (2 Red & 2 Green at each road) are provided for
pedestrian crossing. L7-L9.L16-L18, L25-L27 & L34-L36 (Green) when
on allows pedestrians to cross and L6-L8, L15-L17, L24-L26 & L33-L35
(Red) when on alarms the pedestrians to wait.
To minimize the hardware pedestrians indicator LEDs (both red and
green are connected to same port lines (PC4 to PC7) with red inverted.
Red LEDs L10 & L28 are connected to port lines PC2 & PC3 while L1
& L19 are connected to lines PC0 & PC1 after inversion. All other LEDs
(amber and green) are connected to port A & B.

PROCEDURE
STEPPER MOTOR
Start the program
Get the counter value and stop the program.
Get the stepping rotation vale for clockwise direction
Similarly process for anti-clockwise direction.
Stop the program.

TRAFFIC LIGHT CONTROLLER

Start the program
Assign starting port controls
Execute the kit after entering program
Introduce delay for every signal operation
Stop the program after completing the verification of all directions.

85
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

86
 ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

P
R 8.a.STEP
O PER
G MOTOR
R INTERFA
A CE
ADDRESS LABEL MNEMONICS OPCODE COMMENTS
M
1000 START MVI DI, C7 Mov data from table
TABLE to DI
1001 C7
1002 10
1003 18
1004 MOV CL, 04 C6 Mov data 04 to CL
1005 CL
1006 04
1007 LOOP 1 MOV AL,[DI] 8A Mov data [DI] to
AL reg
1008 05
1009 OUT C0, AL E6 O/P the AL reg data
to C0
100A C0
100B MOV DX, C7 Mov data 1010 to
1010 DX
100C C2
100D 10
100E 10
100F DELAY DEC DX 4A Decrement the DX
reg
1010 JNZ DELAY 75 Jump on no zero
1011 FD
1012 INC DI 47 Increment DI reg
1013 LOOP LOOP1 E2
1014 F2
1015 JMP START E9 Jump to start
address
1016 E8
1017 FF

87
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

8b.TRAFFIC LIGHT CONTROLLER

ADDRESS LABEL MNEMONICS

1000 START MOV AL,80H
1003 OUT CNTRL,AL
1005 REPEAT MOV BX, LOOKUP
1009 MOV SI, LABEL
100D CALL OUT
1010 MOV AL,[SI]
1012 OUT PORTA, AL
1014 CALL DELAY1
1017 INC SI
1018 INC BX
1019 CALL OUT
101C MOV AL,[SI]
101E OUT PORTB, AL
1020 CALL DELAY1
1023 INC SI
1024 INC BX
1025 CALL OUT
1028 MOV AL,[SI]
102A OUT PORTC, AL
102C CALL DELAY1
102F INC SI
1030 INC BX
1031 CALL OUT
1034 MOV AL,[SI]
1036 OUT PORTC, AL
1038 INC SI
1039 MOV AL,[SI]
103B OUTPORTA,AL
103D CALL DELAY 1
1040 JMP REPAEAT
1043 MOV AL,[BX]
1045 OUT PORTC,AL
1047 INC BX
1048 MOV AL,[BX]
104A OUT PORTB,AL
104C INC BX
104D MOV AL,[BX]
88
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

104F OUT PORTA,AL

1051 CALL DELAY1
1054 RET
1055 MOV DI, 0004
1059 MOV DX,FFFF
105D DEC DX
105E JNZ AI
1060 DEC DI
1064 DELAY 1 MOV DI,00015H
1068 B0: MOV DX,0FFFFH
106C B1: DEC DX
106D JNZ BI
106F DEC DI
1070 JNZ BI
1072 RET

RESULT
Thus program to perform stepper motor interface,traffic light
controller interface with 8086 was executed and verified.

89
ESD-1 LAB MANUAL M.E.APPLIED ELECTRONICS

89