AUTOMATIC MULTILEVEL CAR PARKING BY USE OF SENSOR

SYSTEM

A THESIS

Submitted by

KHUSHBOO SHRIWAS SHRUTIKA LUHURE

SONAM SARANKAR RUSHDA KAUSAR

in partial fulfillment of the requirements for the degree of

BACHELOR OF ENGINEERING

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

ENGINEERING

RASHTRASANT TUKDOJI MAHARAJ NAGPUR UNIVERSITY

NAGPUR

APRIL 2017
 CERTIFICATE

This is to certify that the project entitled AUTOMATIC MULTILEVEL

CAR PARKING BY USE OF SENSOR SYSTEM, which is being submitted here

with for the award of the Degree of Bachelor of Engineering in the department of

Electronics and Telecommunication Engineering of Anjuman College of Engineering

and Technology, Sadar, Nagpur (Affiliated to Rashtrasant Tukadoji Maharaj Nagpur

University, Nagpur). This is the result of original research and project work

contributed by KHUSHBOO SHRIWAS, SHRUTIKA LUHURE, SONAM

SARANKAR, RUSHDA KAUSAR under our supervision and guidance. The work

embodied in this report has not formed earlier for the basis of the award of any degree

of compatible certificate or similar title of this for other degree/diploma/examining

body or university to the best of knowledge and belief.

Prof. Tirupati Goskula Prof. Mohd. Nasiruddin

Guide Guide
Public Relation Officer <Academic
Electronics & Telecomm. Designation>
A.C.E.T. Electronics & Telecomm.
Nagpur A.C.E.T.
Nagpur

Dr. Sajid Anwar

Principal
A.C.E.T., Nagpur
 ABSTRACT

This project has shown the concept of automatic car parking system,
which can automatically sense the entry and exit of the cars, number of cars
displayed on the LCD. The control system will play a major role in organizing
the entry to and exit from the parking lots. This automated car parking system
reduces the time taken to check the space for the vehicles. In this paper we use
the Infra-red sensors which are placed on each of the floor, to sense the cars. In
the modern world, where parking-space has become a very big problem, it has
become very important to avoid the wastage of space in modern big Automatic
multi-level car parking system helps to minimize the car parking area companies
and apartments. The parking lots have an elevator to carry cars to different floors
according to the vacancies. The system is developed using 89S52
microcontroller.

ACKNOWLEDGEMENT
 Completing a task is never a one mans effort. Several prominent people have
helped in the present project work; their collective efforts have led in presentation of
this Dissertation work, it is hard task to mention them all. It is an immense pleasure in
expressing genuine and profound gratitude towards the guide <Prof. Tirupati
Goskula> and for their valuable suggestions, guidance, constant support, and
encouragement during completion of this dissertation work. I am grateful to <Prof.
Mohd. Nasiruddin>, H.O.D, Department of Electronics and Telecommunication
Engineering, Anjuman College of Engineering and Technology, Sadar, Nagpur for
their valuable suggestions and guidance.
I am obliged to Dr. Sajid Anwar, Principal, Anjuman College of Engineering
and Technology, Sadar, Nagpur, without whose support and encouragement, the work
couldnt have been completed in the craze that now it has been distinguished and
accomplished. I am grateful to all the teaching and non-teaching staff of Electronics
and Telecommunication Engineering department for their timely help.
At this onset, I desire to avail the opportunity to express appreciation towards,
my friends and good wishes for their constant support. Last but not the least the
backbone of my success and confidence lies solely on the blessing of my parents and
my family. I would like to specially thank my mother <Name of Mother> and my
father <Name of Father> for their constant support and blessing as it is all because of
them I could do in spite of all the hardships.

------------------
Syed Irfan Ali
VIIIth Semester B.E. in
Electronics & Telecomm. Engineering
A.C.E.T, Nagpur
 TABLE OF CONTENTS

CHAPTER NO. TITLE PAGE NO.

ABSTRACT 3

LIST OF FIGURES 7

LIST OF ABBREVIATIONS 8

1 INTRODUCTION TO AUTOMATIC MULTILEVEL CAR

PARKING BY USE OF SENSOR SYSTEM 9
1.1 INTRODUCTION 9
1.2 THEORY OF CAR PARKING 9
1.3 TYPES OF CAR PARKING 10
1.4 LITERATURE 10

2 MULTILEVEL CAR PARKING SYSTEM 12

2.1 METHODOLOGY 12
2.1.1 WORKING 13
3.1 POWER SUPPLY 14
3.2 MICROCONTROLLER 15
3.2.1 Block and Pin diagram of Microcontroller 15
3.2.2 Pin Description: 16
3.2.3 Architecture of 89C51 19
3.2.4 ADVANTAGES OF MICROCONTROLLERS: 20
3.3 INTRODUCTION TO ATMEL MICROCONTROLLER 20
3.3.1 POWER MODES OF ATMEL 89C51
ICROCONTROLLER: 21
3.3.1.1 IDLE MODE: 21
3.3.1.2 POWER DOWN MODE: 21
3.3.1.3 POWER ON RESET: 21
3.3.2 MEMORY ORGANIZATION: 22
3.3.2.1 PROGRAM MEMORY: 22
3.3.2.2 DATA MEMORY: 23
3.3.3 ADDRESSING MODES: 24
 3.3.3.1 DIRECT ADDRESSING: 24
3.3.3.2 INDIRECT ADDRESSING: 24
3.3.3.3 INDEXED ADDRESSING: 24
3.3.3.4 REGISTER INSTRUCTION: 25
3.3.3.5 REGISTER - SPECIFIC INSTRUCTION: 25
3.3.3.6 IMMEDIATE CONSTANTS: 25
PSW4: 26
REGISTER BANK SELECT 26
PSW5: 26
3.3.3.7 INTERRUPTS 27
3.3.3.8 OSCILLATOR AND CLOCK CIRCUIT: 28
3.3.3.9 CPU TIMING: 29
3.3.3.10Applications of Microcontrollers 29
3.4 LCD 30
3.5 IR SENSOR 31
3.6 DC MOTOR 32
3.7 BUZZER 36
3.7.1 Circuit description: 36
3.7.2 Alarm description: 37
3.8 ADVANTAGES & DISADVANTAGES OF MULTILEVEL CAR
PARK SYSTEM 38
3.8.1 Advantages 38
3.8.2 Disadvantages 38
3.9 APPLICATIONS 39
3.10 CONCLUSION 39

REFERENCES 40

LIST OF FIGURES
FIGURENO TITLE
PAGE NO.
2.1 Basic block diagram 12
3.1 Power supply
14
3.2.1 Pin diagram of microcontroller 15
3.2.3 Architecture of microcontroller
19
3.4 Pin diagram of LCD 30
3.5 Circuit diagram of IR Sensor 31
3.6.1 2 pole DC motor 32
3.6.3 3 pole DC motor 33
3.6.5 Coreless DC motor 35
3.7.1 Circuit diagram of buzzer 36

LIST OF ABBREVIATIONS
ALU - Arithmetic Logic Unit

ANSI - American National Standards Institute

CPU - Central Processing Unit

CP - Compression Ratio

RGA - Relative Gain Array

 CHAPTER 1

INTRODUCTION TO AUTOMATIC MULTILEVEL CAR

PARKING BY USE OF SENSOR SYSTEM

This chapter emphasize the significance and characterization of liquid

mixtures using ultrasonic method. A brief review of literature pertaining to the present
work is also presented.

1.1 INTRODUCTION

The advancement and progress of nations is measured by the possibility of their

use and application of latest invented technologies in all aspects of life. Control
engineering is one of the aspects which have been given a great deal by many
researchers. It became to a great concerns in many areas such as industry, agriculture,
medicine, education and infrastructure. Automatic control systems have emerged as an
integrated part in telecommunications, electricity, fuel and other applications. This
paper is devoted to the use of control systems in parking systems. The control system
will play a major role in organizing the entry to and exit from the parking lots. It also
presents the design of multi-level parking lots which occupies less need on the ground
and contains the large number of cars.

1.2 THEORY OF CAR PARKING

The need of using technologies became inevitable. In the modern world, where
parking-space has become a very big problem, it has become very important to avoid
the wastage of space in modern big Automatic multilevel car parking system helps to
minimize the car parking area companies and apartments etc.
1.3 TYPES OF CAR PARKING

There are two types of car parking systems: traditional and automated. In
the long term, automated car parking systems are likely to be more cost effective when
compared to traditional parking garages. Automatic multi-storey automated car park
systems are less expensive per parking slot, since they tend to require less building
volume and less ground area than a conventional facility with the same capacity. Both
automated car parking systems and automated parking garage systems reduce
pollution. This research is devoted to the automated multilevel car parking system. A
multilevel car parking is essentially a building with number of floors or layers for the
cars to be parked. The different levels are accessed through interior or exterior ramps.
An automated car parking has mechanized lifts which transport the car to the different
levels at a certain position. Therefore, these car parks need less building volume and
less ground space and thus save on the cost of the building. This system proves to be
useful in reducing wastage of space where more than 100 cars need to be parked. This
system enables the parking of vehicles, floor after floor and thus reducing the space
used. Here any number of cars can be parked according to the requirement. These
makes the systems modernized and even a space-saving one.

1.4 LITERATURE

The earliest known multi-level car park was built in 1918. It was built for
the Hotel La Salle in Chicago, IL at 215 West Washington Street in the West Loop
area of downtown. It was designed by Holabird and Roche. The Hotel La Salle was
demolished in 1976, but the parking structure remained because it had been
designated as preliminary landmark status and the structure was located several blocks
from the hotel it was built to service. The Hotel LaSalle multi-level was demolished in
2005 after failing to receive landmark status from the city of Chicago. Jupiter Realty
Corp. of Chicago is constructing a 49-level apartment tower in its place with
construction underway as of March 2008.
 During the 1920s and 1930s a series of other patents were granted but it
was not until the late 1940s that the Bowser, Pigeon Hole and Roto Park systems
became operational and installed in numerous locations. Some of these early systems
were vertical elevator lift modules that placed cars on upper levels of a structure to be
moved by attendant and others mechanical devices that could move vehicles into
slots in a framework built around a central corridor. Capacities ranged typically
from less than 100 spaces to more than 600. Automated car parks rely on similar
technology that is used for mechanical handling and document retrieval. The driver
leaves the car in an entrance module. It is then transported to a parking slot by a robot
trolley.
For the driver, the process of parking is reduced to leaving the car inside an
entrance module. At peak periods a wait may be involved before entering or leaving.
The wait is due to the fact that loading passengers and luggage occurs at the entrance
and exit location rather than at the parked stall. This loading blocks the entrance or
exit from being available to others. Whether the retrieval of vehicles is faster in an
automatic car park or a self park car park depends on the layout and number.
 CHAPTER 2

MULTILEVEL CAR PARKING SYSTEM

In this project, Automatic Car Parking System, we have built a system

which will automatically sense the entry and exit of cars through the gate and then
display the number of cars on the LCD.
In this project we have taken a model of car parking system.

2.1 METHODOLOGY

Block diagram:

Figure 2.1: Basic block diagram

2.1.1 WORKING

A microcontroller has been used to sense the movement of cars and check
whether there is a capacity for cars to park. We use two dc motors, one is for gate and
other is for lifting the lifter carrying the car. Gate is open when motor is rotated
clockwise and closed when motor rotated in anticlockwise. It is also possible to open a
gate when any car enters in the parking lot or close the door when a car exits from it.
We use Infra-red sensors, which are mounted on each floor.
Simultaneously, it will display the number of cars present in the parking lot on a LCD
screen and opens the gate if there is a space for the car to park. When all the spaces
are occupied then LCD displays NO vacant space and the gate is not open. The
sensing of entry and exit of cars is done through infrared transmitters and receivers.
The infrared transmitter is mounted on one side and the receiver is placed directly
against the transmitter.
When a car arrives, the infrared beam is blocked by the car and the
receiver is devoid of infrared. Message is sent to the microcontroller according to it
the car is parked. The procedure for the exit of cars is much similar to that of entry.
We use RFID card and RFID card reader. Whenever the car enters in the parking area
it must show the card to the card reader and detect the card. Then the gate is open car
enter into the parking area, gate is closed after some delay.
 CHAPTER 3 COMPONENT DESCRIPTION

Our Car parking system is composed of power supply, microcontroller

(89s52), IR sensors, DC motors, 16X2 LCD, Buzzer.

3.1 POWER SUPPLY

The ac voltage, typically 220V RMS, is connected to a transformer, which

steps that ac voltage down to the level of the desired dc output. A diode rectifier then
provides a full-wave rectified voltage that is initially filtered by a simple capacitor
filter to produce a dc voltage. This resulting dc voltage usually has some ripple or ac
voltage variation. A regulator circuit removes the ripples and also remains the same
dc value even if the input dc voltage varies. This voltage regulation is usually
obtained using one of the popular voltage regulator IC units.

FIGURE 3.1: POWER SUPPLY

3.2 MICROCONTROLLER

A microcontroller is a Computer-On-A-Chip, or, if you prefer, a single-

chip computer. Micro suggests that the device is small, and controller tells you that the
device' might be used to control objects, processes, or events. Another term to
describe a microcontroller is embedded controller, because the microcontroller and its
support circuits are often built into, or embedded in, the devices they control.

Today microcontrollers are very commonly used in wide variety of

intelligent products. For example most personal computers keyboards and
implemented with a microcontroller. It replaces Scanning, Debounce, Matrix
Decoding, and Serial transmission circuits. Many low cost products, such as Toys,
Electric Drills, Microwave Ovens, VCR and a host of other consumer and industrial
products are based on microcontrollers.

The microcontroller contains full implementation of a standard

MICROPROCESSOR, ROM, RAM, I/0, CLOCK, TIMERS, and also SERIAL
PORTS. Microcontroller also called "system on a chip" or "single chip microprocessor
system" or "computer on a chip".

3.2.1 Block and Pin diagram of Microcontroller

FIGURE 3.2.1: PIN DIAGRAM OF MICROCONTROLLER

3.2.2 Pin Description:

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin
can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as
high impedance inputs. Port 0 may also be configured to be the multiplexed low order
address/data bus during accesses to external program and data memory. In this mode
P0 has internal pull-ups. Port 0 also receives the code bytes during Flash
programming, and outputs the code bytes during program verification. External pull-
ups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
1 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 1 also receives the low-order address bytes during Flash
programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
2 pins that are externally being pulled low will source current (IIL) because of the
internal pull-ups. Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when
emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX
@ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also
receives the high-order address bits and some control signals during Flash
programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally being pulled low will source current (IIL) because of the
pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as
listed below:

RST

Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG)
during Flash programming. In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency, and may be used for external timing or clocking purposes.
Note, however, that one ALE pulse is skipped during each access to external Data
Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location

8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if
the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory. When
the AT89C51 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each
access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the

device to fetch code from external program memory locations starting at 0000H up to
FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched
on reset. EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during
Flash programming, for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.

XTAL2

Output from the inverting oscillator amplifier. It should be noted that when
idle is terminated by a hard ware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to
external memory.

3.2.3 Architecture of 89C51

FIGURE 3.2.3:ARCHITECTURE OF MICROCONTROLLER

3.2.4 ADVANTAGES OF MICROCONTROLLERS:

If a system is developed with a microprocessor, the designer has to go for

external memory such as RAM, ROM or EPROM and peripherals and hence the size
of the PCB will be large enough to hold all the required peripherals. But, the micro
controller has got all these peripheral facilities on a single chip so development of a
similar system with a micro controller reduces PCB size and cost of the design.

One of the major differences between a micro controller and a

microprocessor is that a controller often deals with bits , not bytes as in the real world
application, for example switch contacts can only be open or close, indicators should
be lit or dark and motors can be either turned on or off and so forth.

3.3 INTRODUCTION TO ATMEL MICROCONTROLLER

SERIES: 89C51 Family, TECHNOLOGY: CMOS

The major Features of 8-bit Micro controller ATMEL 89C51:

8 Bit CPU optimized for control applications

Extensive Boolean processing (Single - bit Logic ) Capabilities.

On - Chip Flash Program Memory

On - Chip Data RAM

Bi-directional and Individually Addressable I/O Lines

Multiple 16-Bit Timer/Counters

Full Duplex UART

Multiple Source / Vector / Priority Interrupt Structure

On - Chip Oscillator and Clock circuitry.

On - Chip EEPROM
 SPI Serial Bus Interface

Watch Dog Timer

3.3.1 POWER MODES OF ATMEL 89C51 ICROCONTROLLER:

To exploit the power savings available in CMOS circuitry. Atmel s Flash

micro controllers have two software-invited reduced power modes.

3.3.1.1 IDLE MODE:

The CPU is turned off while the RAM and other on - chip peripherals
continue operating. In this mode current draw is reduced to about 15 percent of the
current drawn when the device is fully active.

3.3.1.2 POWER DOWN MODE:

All on-chip activities are suspended while the on chip RAM continues to
hold its data. In this mode, the device typically draws less than 15 Micro Amps and
can be as low as 0.6 Micro Amps

3.3.1.3 POWER ON RESET:

When power is turned on, the circuit holds the RST pin high for an amount
of time that depends on the capacitor value and the rate at which it charges.

To ensure a valid reset, the RST pin must be held high long enough to allow
the oscillator to start up plus two machine cycles. On power up, VCC should rise
within approximately 10ms. The oscillator start-up time depends on the oscillator
frequency. For a 10 MHz crystal, the start-up time is typically 1ms.With the given
circuit, reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall
below 0V. However, this voltage is internally l limited and will not harm the device.
3.3.2 MEMORY ORGANIZATION:

* Logical Separation of Program and Data Memory *

All Atmel Flash micro controllers have separate address spaces for program
and data memory as shown in Fig 1.The logical separation of program and data
memory allows the data memory to be accessed by 8 bit addresses. This can be more
quickly stored and manipulated by an 8 bit CPU Nevertheless 16 Bit data memory
addresses can also be generated through the DPTR register.

Program memory can only be read. There can be up to 64K bytes of directly
addressable program memory. The read strobe for external program memory is the
Program Store Enable Signal (PSEN) Data memory occupies a separate address space
from program memory. Up to 64K bytes of external memory can be directly addressed
in the external data memory space. The CPU generates read and write signals, RD and
WR, during external data memory accesses. External program memory and external
data memory can be combined by an applying the RD and PSEN signals to the inputs
of AND gate and using the output of the fate as the read strobe to the external
program/data memory.

3.3.2.1 PROGRAM MEMORY:

The map of the lower part of the program memory, after reset, the CPU
begins execution from location 0000h. Each interrupt is assigned a fixed location in
program memory. The interrupt causes the CPU to jump to that location, where it
executes the service routine. External Interrupt 0 for example, is assigned to location
0003h. If external Interrupt 0 is used, its service routine must begin at location 0003h.
If the I interrupt in not used its service location is available as general-purpose
program memory.

The interrupt service locations are spaced at 8 byte intervals 0003h for
External interrupt 0, 000Bh for Timer 0, 0013h for External interrupt 1,001Bh for
Timer1, and so on. If an Interrupt service routine is short enough (as is often the case
in control applications) it can reside entirely within that 8-byte interval. Longer
service routines can use a jump instruction to skip over subsequent interrupt locations.
If other interrupts are in use. The lowest addresses of program memory can be either
in the on-chip Flash or in an external memory. To make this selection, strap the
External Access (EA) pin to either VCC or GND. For example, in the AT89C51 with
4K bytes of on-chip Flash, if the EA pin is strapped to VCC, program fetches to
addresses 0000h through 0FFFh are directed to internal Flash. Program fetches to
addresses 1000h through FFFFh are directed to external memory.

3.3.2.2 DATA MEMORY:

The Internal Data memory is dived into three blocks namely, Refer Fig

The lower 128 Bytes of Internal RAM.

The Upper 128 Bytes of Internal RAM.
Special Function Register
Internal Data memory Addresses are always 1 byte wide, which implies an
address space of only 256 bytes. However, the addressing modes for internal RAM
can in fact accommodate 384 bytes. Direct addresses higher than 7Fh access one
memory space, and indirect addresses higher than 7Fh access a different Memory
Space.

The lowest 32 bytes are grouped into 4 banks of 8 registers. Program

instructions call out these registers as R0 through R7. Two bits in the Program Status
Word (PSW) Select, which register bank, is in use. This architecture allows more
efficient use of code space, since register instructions are shorter than instructions that
use direct addressing.

The next 16-bytes above the register banks form a block of bit addressable
memory space. The micro controller instruction set includes a wide selection of single
- bit instructions and this instruction can directly address the 128 bytes in this area.
These bit addresses are 00h through 7Fh. either direct or indirect addressing can
access all of the bytes in lower 128 bytes. Indirect addressing can only access the
upper 128. The upper 128 bytes of RAM are only in the devices with 256 bytes of
RAM.
The Special Function Register includes Ports latches, timers, peripheral
controls etc., direct addressing can only access these register. In general, all Atmel
micro controllers have the same SFRs at the same addresses in SFR space as the
AT89C51 and other compatible micro controllers. However, upgrades to the
AT89C51 have additional SFRs. Sixteen addresses in SFR space are both byte and bit
Addressable. The bit Addressable SFRs are those whose address ends in 000B. The bit
addresses in this area are 80h through FFh.

3.3.3 ADDRESSING MODES:

3.3.3.1 DIRECT ADDRESSING:

In direct addressing, the operand specified by an 8-bit address field in the

instruction. Only internal data RAM and SFRs can be directly addressed.

3.3.3.2 INDIRECT ADDRESSING:

In Indirect addressing, the instruction specifies a register that contains the

address of the operand. Both internal and external RAM can indirectly address.

The address register for 8-bit addresses can be either the Stack Pointer or R0 or
R1 of the selected register Bank. The address register for 16-bit addresses can be only
the 16-bit data pointer register, DPTR.

3.3.3.3 INDEXED ADDRESSING:

Program memory can only be accessed via indexed addressing this addressing
mode is intended for reading look-up tables in program memory. A 16 bit base register
(Either DPTR or the Program Counter) points to the base of the table, and the
accumulator is set up with the table entry number. Adding the Accumulator data to the
base pointer forms the address of the table entry in program memory.
 Another type of indexed addressing is used in the case jump instructions. In
this case the destination address of a jump instruction is computed as the sum of the
base pointer and the Accumulator data.

3.3.3.4REGISTER INSTRUCTION:

The register banks, which contains registers R0 through R7, can be accessed by
instructions whose opcodes carry a 3-bit register specification. Instructions that access
the registers this way make efficient use of code, since this mode eliminates an
address byte. When the instruction is executed, one of four banks is selected at
execution time by the row bank select bits in PSW.

3.3.3.5REGISTER - SPECIFIC INSTRUCTION:

Some Instructions are specific to a certain register. For example some

instruction always operates on the Accumulator, so no address byte is needed to point
OT ir. In these cases, the opcode itself points to the correct register. Instruction that
register to Accumulator as A assemble as Accumulator - specific Opcodes.

3.3.3.6IMMEDIATE CONSTANTS:

The value of a constant can follow the opcode in program memory For
example. MOV A, #100 loads the Accumulator with the decimal number 100. The
same number could be specified in hex digit as 64h.

PROGRAM STATUS WORD:

Program Status Word Register in Atmel Flash Micro controller

CY AC F0 RS1 RS0 OV --- P

PSW 7 PSW 0
 PSW 6 PSW 1

PSW 5 PSW 2

PSW 4 PSW 3

PSW 0:

Parity of Accumulator Set By Hardware To 1 if it contains an Odd number of

1s, Otherwise it is reset to 0.

PSW1:

User Definable Flag

PSW2:

Overflow Flag Set By Arithmetic Operations

PSW3:

Register Bank Select

PSW4:

REGISTER BANK SELECT

PSW5:

General Purpose Flag.

PSW6:

Auxiliary Carry Flag Receives Carry Out from

Bit 1 of Addition Operands

PSW7:

Carry Flag Receives Carry Out From Bit 1 of ALU Operands.

The Program Status Word contains Status bits that reflect the current sate of the
CPU. The PSW shown if Fig resides in SFR space. The PSW contains the Carry Bit,
The auxiliary Carry (For BCD Operations) the two - register bank select bits, the
Overflow flag, a Parity bit and two user Definable status Flags.

The Carry Bit, in addition to serving as a Carry bit in arithmetic operations also
serves the as the Accumulator for a number of Boolean Operations .The bits RS0
and RS1 select one of the four register banks. A number of instructions register to
these RAM locations as R0 through R7.The status of the RS0 and RS1 bits at
execution time determines which of the four banks is selected.

The Parity bit reflect the Number of 1s in the Accumulator .P=1 if the
Accumulator contains an even number of 1s, and P=0 if the Accumulator contains an
even number of 1s. Thus, the number of 1s in the Accumulator plus P is always even.
Two bits in the PSW are uncommitted and can be used as general-purpose status flags.

3.3.3.7INTERRUPTS

The AT89C51 provides 5 interrupt sources: Two External interrupts, two-timer

interrupts and a serial port interrupts. The External Interrupts INT0 and INT1 can each
either level activated or transistion - activated, depending on bits IT0 and IT1 in
Register TCON. The Flags that actually generate these interrupts are the IE0 and IE1
bits in TCON. When the service routine is vectored to hardware clears the flag that
generated an external interrupt only if the interrupt WA transition - activated. If the
interrupt was level - activated, then the external requesting source (rather than the on-
chip hardware) controls the requested flag. Tf0 and Tf1 generate the Timer 0 and
Timer 1 Interrupts, which are set by a rollover in their respective Timer/Counter
Register (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-
chip hardware clears the flag that generated it when the service routine is vectored to.
The logical OR of RI and TI generate the Serial Port Interrupt. Neither of these flag is
cleared by hardware when the service routine is vectored to. In fact, the service
routine normally must determine whether RI or TI generated the interrupt an the bit
must be cleared in software.

In the Serial Port Interrupt is generated by the logical OR of RI and TI. Neither
of these flag is cleared by hardware when the service routine is vectored to. In fact, the
service routine normally must determine whether RI to TI generated the interrupt and
the bit must be cleared in software.

IE: INTERRUPT ENABLE REGISTER

EA - ET2 ES ET1 EX1 ET0 EX0

Enable bit = 1 enabled the interrupt

Enable bit = 0 disables it.

3.3.3.8OSCILLATOR AND CLOCK CIRCUIT:

XTAL1 and XTAL2 are the input and output respectively of an inverting
amplifier which is intended for use as a crystal oscillator in the pierce configuration,
in the frequency range of 1.2 MHz to 12 MHz. XTAL2 also the input to the internal
clock generator.
To drive the chip with an internal oscillator, one would ground XTAL1 and
XTAL2. Since the input to the clock generator is divide by two flip flop there are no
requirements on the duty cycle of the external oscillator signal. However, minimum
high and low times must be observed.

The clock generator divides the oscillator frequency by 2 and provides a tow
phase clock signal to the chip. The phase 1 signal is active during the first half to each
clock period and the phase 2 signals are active during the second half of each clock
period.
 3.3.3.9CPU TIMING:

A machine cycle consists of 6 states. Each stare is divided into a phase / half,
during which the phase 1 clock is active and phase 2 half. Arithmetic and Logical
operations take place during phase1 and internal register - to register transfer take
place during phase 2

3.3.3.10 Applications of Microcontrollers

Microcontrollers are designed for use in sophisticated real time applications

such as

a. Industrial Control
b. Instrumentation and
c. Intelligent computer peripherals

They are used in industrial applications to control

Motor

Robotics

Discrete and continuous process control

In missile guidance and control

In medical instrumentation

Oscilloscopes

Telecommunication

Automobiles

For Scanning a keyboard

Driving an LCD

For Frequency measurements

Period Measurements
3.4 LCD

LCD (Liquid Crystal Display) screen is an electronic display module and find
a wide range of applications. A 16x2 LCD display is very basic module and is very
commonly used in various devices and circuits. These modules are preferred over
seven segments and other multi segment LEDs. The reasons being: LCDs are
economical; easily programmable; have no limitation of displaying special & even
custom characters (unlike in seven segments), animations and so on.

A 16x2 LCD means it can display 16 characters per line and there are 2 such
lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two
registers, namely, Command and Data.

The command register stores the command instructions given to the LCD. A
command is an instruction given to LCD to do a predefined task like initializing it,
clearing its screen, setting the cursor position, controlling display etc. The data register
stores the data to be displayed on the LCD. The data is the ASCII value of the
character to be displayed on the LCD.

Pin Diagram:
 FIGURE 3.4: PIN DIAGRAM OF LCD

3.5 IR SENSOR

Infrared transmitter is one type of LED which emits infrared rays generally
called as IR Transmitter. Similarly IR Receiver is used to receive the IR rays
transmitted by the IR transmitter. One important point is both IR transmitter and
receiver should be placed straight line to each other.

The transmitted signal is given to IR transmitter whenever the signal is

high, the IR transmitter LED is conducting it passes the IR rays to the receiver. The IR
receiver is connected with comparator. The comparator is constructed with LM 358
operational amplifier. In the comparator circuit the reference voltage is given to Non
inverting input terminal. The inverting input terminal is connected IR receiver. When
interrupt the IR rays between the IR transmitter and receiver, the IR receiver is not
conducting. So the comparator Non inverting input terminal voltage is higher then
inverting input. Now the comparator output is in the range of 0V. This voltage is given
to microcontroller and LED will OFF.

When IR transmitter passes the rays to receiver, the IR receiver is

conducting due to that non inverting input voltage is Higher than inverting input. Now
the comparator output is +5Volt so the output is given to microcontroller so LED will
glow. This circuit is mainly used to for counting application, interrupt detector etc.
The combination of these circuits in this single PCB board.

figure 3.5: circuit diagram of IR sensor

3.6 DC MOTOR

In any electric motor, operation is based on simple electromagnetism. A

current-carrying conductor generates a magnetic field; when this is then placed in an
external magnetic field, it will experience a force proportional to the current in the
conductor, and to the strength of the external magnetic field. As you are well aware of
from playing with magnets as a kid, opposite (North and South) polarities attract,
while like polarities (North and North, South and South) repel. The internal
configuration of a DC motor is designed to harness the magnetic interaction between a
current-carrying conductor and an external magnetic field to generate rotational
motion.

Let's start by looking at a simple 2-pole DC electric motor (here red

represents a magnet or winding with a "North" polarization, while green represents a
magnet or winding with a "South" polarization).

FIGURE 3.6.1: 2 POLE DC MOTOR

Every DC motor has six basic parts -- axle, rotor (armature), stator,
commutator, field magnet(s), and
brushes. In most common DC
motors, the external magnetic field is
produced by high- strength
permanent magnets. The stator is the
stationary part of the motor - this
includes the motor casing, as well as
two or more permanent
magnet pole pieces. The rotor
consists of windings (generally on a
core), the windings being electrically
connected to the commutator. The
above diagram shows a common motor layout - with the rotor inside the stator (field)
magnets.
 The geometry of the brushes, commutator contacts, and rotor windings are
such that when power is applied, the polarities of the energized winding and the stator
magnet(s) are misaligned, and the rotor will rotate until it is almost aligned with the
stator's field magnets. As the rotor reaches alignment, the brushes move to the next
commutator contacts, and energize the next winding. In real life, though, DC motors
will always have more than two poles (three is a very common number). In particular,
this avoids "dead spots" in the commutator. Meanwhile, with a two-pole motor, there
is a moment where the commutator shorts out the power supply. Yet another
disadvantage of such a simple motor is that it would exhibit a high amount of torque
"ripple" .

FIGURE 3.6.2:
So since most small DC motors are of a three-pole design, let's tinker with
the workings of one via an interactive animation .

FIGURE 3.6.3: 3-POLE DC MOTOR

 A few things from this -- namely, one pole is fully energized at a time (but
two others are "partially" energized). As each brush transitions from one commutator
contact to the next, one coil's field will rapidly collapse, as the next coil's field will
rapidly charge up (this occurs within a few microsecond).

The use of an iron core armature (as in the Mabuchi, above) is quite
common, and has a number of advantages. First off, the iron core provides a strong,
rigid support for the windings -- a particularly important consideration for high-torque
motors. The core also conducts heat away from the rotor windings, allowing the motor
to be driven harder than might otherwise be the case. Iron core construction is also
relatively inexpensive compared with other construction types.

FIGURE 3.6.4:
But iron core construction also has several disadvantages. The iron
armature has a relatively high inertia which limits motor acceleration. This
construction also results in high winding inductances which limit brush and
commutator life.

In small motors, an alternative design is often used which features a

'coreless' armature winding. This design depends upon the coil wire itself for
structural integrity. As a result, the armature is hollow, and the permanent magnet can
be mounted inside the rotor coil. Coreless DC motors have much lower armature
inductance than iron-core motors of comparable size, extending brush and
commutator life.
 FIGURE 3.6.5: CORELESS DC MOTOR
The coreless design also allows manufacturers to build smaller motors;
meanwhile, due to the lack of iron in their rotors, coreless motors are somewhat prone
to overheating. As a result, this design is generally used just in small, low-power
motors. Beamers will most often see coreless DC motors in the form of pager motors.

Again, disassembling a coreless motor can be instructive -- in this case,

my hapless victim was a cheap pager vibrator motor. The guts of this disassembled
motor are available (on 10 lines / cm graph paper). This is (or more accurately, was) a
3-pole coreless DC motor.

3.7 BUZZER

A buzzer or beeper is a signalling device, usually electronic, typically

used in automobiles, household appliances such as a microwave oven, or game shows.
It most commonly consists of a number of switches or sensors connected to a control
unit that determines if and which button was pushed or a preset time has lapsed, and
usually illuminates a light on the appropriate button or control panel, and sounds a
warning in the form of a continuous or intermittent buzzing or beeping sound.

3.7.1 Circuit description:

 FIGURE 3.7.1: CIRCUIT DIAGRAM OF BUZZER
The circuit is designed to control the buzzer. The buzzer ON and OFF is
controlled by switching transistor (BC 547). The buzzer is connected in the transistor
collector terminal.

When high pulse (5 Volt) signal is given to base of the transistor, the
transistor is conducting and closes the collector and emitter terminal. Hence the
buzzer was already getting a volt power supply in the positive terminal. At that time
the buzzer gets the negative supply. So the circuit will close and the Buzzer will ON.

When low pulse is given to base of transistor, it will turn OFF. So buzzer
will also OFF because it doesnt get negative power supply. This type of transistor
arrangement is called driver circuit. We cant connect any load to the Micro-controller
output terminals. That is why we need a driver circuit.

3.7.2 Alarm description:

5 Volt passive beeper

1. This small sound module can be driven by an Arduino output pin.

2. A pulse of current will make it click. A series of pulses will cause it to output
a tone, and you can control the frequency.

3. With the Arduino TONE library, many different sounds can be made. It is not a
full-range speaker.
3.8 ADVANTAGES & DISADVANTAGES OF MULTILEVEL CAR
PARK SYSTEM

3.8.1 Advantages

This system is more versatile and fast automatic parking system. The
advantages of multilevel parking system are:
- Maximum utilization of ground space.
- Quick entry and exit due to the independent operation of lifts.
- designed for driver convenience.
- Partial breakdown doesn't affect the other parts.
- Governed by computers.
- Multiple safety guarantee of the drivers and the cars too.
- Average vehicle retrieve time is less than 2 minutes.
- require less building volume and less ground area.

3.8.2 Disadvantages

The disadvantages of multi-level car parking system are:

- Expensive as the whole parking and retrieval operation is multi-level.
 -Any fault in the multi-level car parking system will lead to the great
haphazard and inconvenience to the people.
- The power consumption is high to run such system.
- This system is more complex to build.
- Customers have to pay large fares to park their vehicles in multi-level car
parking system.
- Construction cost is very high.

3.9 APPLICATIONS

Public Parking
Airports
Hotels, Malls
Apartments
Office buildings

3.10 CONCLUSION

Automatic multi-stored car parking system is very good substitute for car
parking area. This Automated car parking system enables the parking of vehicles and
thus reduces the time taken to check the space to be used by displaying the spot where
the space for parking is available on an LCD display by using IR sensors at the
entrance. This Automatic Car Parking enables the parking of vehicles-floor after floor
and thus reducing the space used.
 REFERENCES

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Automatic Car Parking System With Least distances Parking Space in Wireless Sensor
Networks, IJSRP, Volume 2, Issue 10, October 2012.

[2] M. M. Rashid, A. Musa, M. Ataur Rahman and N. Farahana, A. Farhana,

Automatic Parking Management System, IJMLC Vol. 2, No. 2, April 2012.

[3] R. Mithari, S.Vaze, and S. Sanamdikar, Automatic Multistoried Car Parking

System, IJITAM, Volume-1, Issue-6, March, 2014.

[4] M.A.Mazidi, Janice, Gillispie Mazidi, The 8051 Microcontroller And Embedded
System.

[5] M. Ahmed, W.G.Wei, Study on Automated Car Parking System Based on

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