1

-------------Standard data type------------- constant const4: enu_type3 :=

Signal a: BIT; (("0000","0000","1111"));
signal a: BIT_VECTOR(7 downto 0); -----Record: collection of different
Signal a: BOOLEAN; --true & false types---
Signal a: BOOLEAN_VECTOR(7 downto 0); Type memory_access is record
-- -(2^31 -1) --> (2^31-1) address_: integer range 0 to 255;
Signal a: integer range 0 to 15; -- -2ti -> block_: integer range 0 to 3;
2ti data: bit_vector(15 downto 0);
Signal a: natural range 0 to 15; -- 0 -> 2ti end record;
(32 bit) variable a: memory_access:=(12,1,X"0000");
signal a: positive range 1 to 16; -- 1 -> 2 a.address_ = 13;
ti (32 bit) --------- Type conversions ----------------
(integer_vector: VHDL 2008) --qualified expression: resolve ambiguous
signal a: character; -- situations
'a','b','c',..,'NUL', sum <= a + unsigned'(1000);
signal a: string(1 to 4); -- "VHDL" --type_name'(expression)
--other type: REAL, REAL_VECTOR, TIME, sig <= signed(slv); --type casting
TIME_VECTOR slv <= std_logic_vector(sig); -- type
--------Standard-logic data type------------ casting: unsigned
-- U,X,0,1,Z,W,L,H,- : -: don't care -- std_logic_vector <-> signed/unsigned <->
signal a: std_logic; integer
signal a: std_logic_vector(15 downto 0); -------- Attribute ------------
--------- Signed/Unsigned ------------------ 'LEFT; 'RIGHT;'LOW;'HIGH; 'EVENT; 'POS;
signal a: signed(7 downto 0); 'RANGE;'LENGTH
--------------Operators--------------------- -------concurrent statements--------------
NOT, AND, NAND, OR, NOR, XOR, XNOR x <= '0' when rst = '0' else
+,-,*,/, abs, rem, mod, add_carry '1' when rst = '0' and a = '1'
=,/=,>,<,>=,<=,maximum, minimum else
sll,srl,sla,sra,ror,rol -- x ssl a --a: '-'; --dont' care
integer with control select
shift_left,shift_right x <= '0' when '0',
to_unsigned, to_signed, to_slv '1' when '1',
(to_stdlogicvector), 'z' when others;
to_integer,to_real, to_string gen: for i in 0 to 7 generate
concatenation: & x(i) <= a(i) XOR b(i);
others => '0'; end generate;
--Note: numeric_bit: unsigned/signed
(base=BIT) gen: if a=b generate
--Note: numeric_std: end generate;
unsigned/signed(base=std_logic) -------sequential statements-----------
--------User-Defined Scalar if condition then
Type------------- ...
Type temperature is range 0 to 273; elsif (...) then
--integer types ...
Type state IS (S0,S1,S2); -- enumerated type else
signal a: temperature; end if;
signal state: machine_state;
------User-Defined Array Type-------------- case data is
Type int_type1 is array (positive range <>) when "000" => count := count + 1;
of integer; when "001" => count := count + 2;
constant const1: int_type1(1 to when others => count := 0;
4):=(1,2,3,4,5); end case;
Type int_type2 is array(1 to 2) of
int_type1; clk'event and clk = '1'
constant const2: int_type2(1 to 2) wait until (clk'event and clk = '1') --wait
:=((1,2,3,4),(2,3,4,5)); until condition;
Type enu_type1 is array(7 downto 0) of wait on clk; --wait on sensitivity_list;
std_logic; wait for 10 ns;
constant const3: enu_type1 := ("10101010"); loop -- unconditional loop
Type enu_type2 is array(1 to 4) of wait until clk ='1';
std_logi_vector(7 downto 0); count := couint + 1;
Type enu_type3 is array(1 to 3, 1 to 4) of end loop;
BIT;
2

for i in 0 to 5 loop -- i in data'range loop configuration config1 of test is

count := count + 1; for arch1
end loop; end for;
end configuration;
while (i < 10) loop -------BLOCK-----------
count := count + 1; --for: code partition: easy to read and
end loop; organized
Controller: BLOCK --used inside the
EXIT; --exit when condition architecture
next when i=skip; -- next when condition begin
-- concurrent statements
--System-level VHDL: Package, Component end block controller;
--------
--function, procedure --guarded expression is true to allow the
package my_package is --package declaration statement
type matrix is array (1 to 3, 1 to 3) of --inside the block can be evaluated
BIT; blk: block(clk='1') begin
signal x: matrix; a <= guarded d;
constant max1: integer := 255; end block blk;
end package -------subprogram: function & procedure ----
package my_pkg is --similiar to PROCESS, only sequential code
constant flag: std_logic; are allowed
function down_edge(signal s: --if, wait, loop, case
std_logic) return boolean; assert(a'length=b'length)
end my_pkg; report "mismatch" & " error" &
------- "checking" & " testing"
package body my_pkg is severity failure;
constant flag: std_logic :='1'; --failure|error|warning|note
function down_edge(signal s: --- function: sequential code only ---
std_logic) return boolean is function positive_edge(signal s: std_logic)
begin return boolean is
return (s'event and s = '0'); --declare variables
end down_edge; begin
end my_pkg; return(s'event and s='1');
--use in the project end function;
use work.my_pgk.all; --used in: package,entity,
----------- component --------- architecture,process,block
component nand3 is --common defined in package (for libraries)
port(a1,a2,a3: in std_logic; b: out package my_subprogram is
std_logic); function positive_edge(signal s:
end component std_logic) return boolean;
nand_gate: nand3 port map(x1,x2,x3,y); end package;
nand_gate2: nand3 port package body my_subprogram is
map(a1=>x1,a2=>x2,a3=>x3,b=>y); function positive_edge(signal s:
----------- std_logic) return boolean
component and_gate is begin
generic(n: positive := 8); return (s'event and s='1');
port(a: in bit_vector(1 to n); b: out end function;
bit); end package body;
end component; --function call
a1: and_gate generic map(16) port map(x,y); if positive_edge(clk) then...
a2: and_gate generic map(n => 16) port --positional mapping vs. nominal mapping
map(a=>x,b=>y); my_function(x1,x2); -- positional mapping
---------- configuration ----- my_function(a=>x1,b=>x2); -- nominal mapping
Entity test ... ---------
end test; --procedure: return more than 1 value
package my_subprog is
architecture arch1... procedure min_max(signal a,b,c: in
end arch1; integer;
signal min,max: out
architecture arch2... integer);
end arch2; end package;
3

package body my_subprog is if(Reset = '1') then

procedure min_max(signal a,b,c: in current_state <= S0;
integer range 0 to 255; elsif (clk'event and clk = '1') then
signal current_state <=
min,max: in integer range 0 to 255) next_state;
is begin end if;
.... end process;
end procedure; -- update next state
end my_subprog; process(X, current_state) is begin
--overloaded function Case current_state is
function "+"(a,b: std_logic_vector) return when S0 =>
std_logic_vector is if(X = '1') then
--declare next_state <= S0;
begin else
next_state <= S1;
end function "+"; end if;
--mealy machine --
architecture Behavioral of When others =>
Moore_Seq_Circuit_name is next_state <= S0; --just in
type STATE_TYPE is case
(S0,S1,S2,S3,S4,S5,S6); end case;
signal current_state, next_state : end process;
STATE_TYPE; -- update output
begin Y <= '1' when state_condition else
-- update current state '0';
process(rst, clk) is begin end Behavioral;
if(rst = '1') then
current_state <= S0; use std.textio.all;
elsif (clk'event and clk = '1') then architecture Behavioral of writeToFile1 is
current_state <= next_state; File f: text open write_mode is "test.txt";
end if; begin
end process; process
-- update next state variable l: LINE;
process(X, current_state) is begin variable str1: string(1 to 5) := "Time:";
Case current_state is variable t: Time := 2000ns;
when S0 => begin
if(X = '1') then write(l,str1);write(l,t);
next_state <= S0; writeline(f,l);
else end process;
next_state <= S1; end Behavioral;
end if;
-- ---read file---
-- add more cases use std.textio.all;
-- architecture Behavioral of writeToFile1 is
When others => File f: text open read_mode is "test.txt";
next_state <= S0; -- just in signal t_out: time range 0 to 800ns;
case begin
end case; process
end process; variable l: LINE;
-- update output variable str1: string(1 to 5);
Y <= '1' when (current_state = and X= variable t: Time;
else '0'; begin
end Behavioral; if(not endfile(f)) then
--Moore machine readline(f,l);
architecture Behavioral of read(l,str1);read(l,t);
Moore_Seq_Circuit_name is --read(l,t,good_format);
type STATE_TYPE is --assert(good_format)
(S0,S1,S2,S3,S4,S5); -- report "bad value"
signal current_state, next_state : -- severity failure;
STATE_TYPE; t_out <=t;
begin end if;
-- update current state end process;
process(Reset, clk) is begin end Behavioral;
4

--- option 2
-signal generation for testbench-- reset <= '1' after 10ns, '0' after 20ns;
--- option 3
--after, wait for and now are used for reset <= '0';
constructing testbench wait for 10ns;
if(now<50ns) then reset <= '1';
wait for 50ns-NOW; wait for 10ns;
y <= x; reset <= '0';
end if; wait;
----g------enerate clk--------------- -------- generate signal --------
signal clk: std_logic := '0'; signal x: std_logic := '1';
--- option 1 --- option1
clk <= not clk after 10ns; x <= '1', '0' after 20ns,'1' after 30ns,
--- option 2 '0' after 40ns, '1' after 80ns;
wait for 10ns; --- option2
clk <= not clk; x='1'; wait for 20ns;x='0'; wait for 10ns;
--- option 3 --- option 3: template
wait for 10ns; constant template:std_logic_vector(1 to 9)
clk <= '1'; := "110100001";
wait for 10ns; for i In template'range loop
clk <= '0'; x <= template(i);
-------- generate reset------------- wait for 10ns;
signal reset:=std_logic :='0'; end loop;
--- option 1
reset <= '0','1' after 10 ns, '0' after
20ns;