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Ieee Ieee STD - Logic - 1164 Ieee STD - Logic - Arith

This document contains VHDL code that defines a testbench and module to drive a 7-segment display. The testbench applies a clock signal and iterates input values from 0-9 to the module. The module contains a process that decodes the 4-bit binary coded decimal (BCD) input into the corresponding 7-bit pattern for the 7-segment display based on the clock edge. It sets the 7-bit output to activate the correct segments for each digit 0-9.

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Dharccana Devi
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19 views

Ieee Ieee STD - Logic - 1164 Ieee STD - Logic - Arith

This document contains VHDL code that defines a testbench and module to drive a 7-segment display. The testbench applies a clock signal and iterates input values from 0-9 to the module. The module contains a process that decodes the 4-bit binary coded decimal (BCD) input into the corresponding 7-bit pattern for the 7-segment display based on the clock edge. It sets the 7-bit output to activate the correct segments for each digit 0-9.

Uploaded by

Dharccana Devi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS


signal clk : std_logic := '0';
signal bcd : std_logic_vector(3 downto 0) := (others => '0');
signal segment7 : std_logic_vector(6 downto 0);
constant clk_period : time := 1 ns;
BEGIN
uut: entity work.test PORT MAP (clk,bcd,segment7);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
for i in 0 to 9 loop
bcd <= conv_std_logic_vector(i,4);
wait for 2 ns;
end loop;
end process;

END;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit
decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of
segment7.
architecture Behavioral of test is

begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as
input.
when others=> segment7 <="1111111";
end case;
end if;

end process;

end Behavioral;

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