Input Output Reg Output Reg Output Reg Output Reg Output Reg Reg Reg Always Posedge Begin If Begin If Begin
Input Output Reg Output Reg Output Reg Output Reg Output Reg Reg Reg Always Posedge Begin If Begin If Begin
v Project: traffic_light
1 module traffic_light (clk, reset, sw1, sw2 clk_led, main_west , main_east , side_north ,
side_south );
2
3 input clk, reset, sw1, sw2;
4
5 output reg clk_led;
6 output reg [3:1]main_west ;
7 output reg [3:1]main_east ;
8 output reg [3:1]side_north ;
9 output reg [3:1]side_south ;
10
11 reg [25:0]counter;
12 reg [25:0]timer=1;
13
14 always @ (posedge clk)
15 begin
16 //reset button not pressed
17 if (~reset)
18 begin
19 //START SECTION 1: (on peak AND sensor value = 0)
20 if((sw1) && (~sw2))
21 begin
22 counter = 0;
23 timer = 1;
24 main_west = 3'b110;
25 main_east = 3'b110;
26 side_north = 3'b011;
27 side_south = 3'b011;
28 end
29 //END SECTION 1
30
31 //START SECTION 2: (off peak OR sensor value = 1)
32 if ((~sw1) || (sw2))
33
34 counter = counter + 1;
35
36 if (counter == 25000000 )
37 begin
38 clk_led = 1; //turn on clock indicator
39 timer = timer + 1; //accumulated time in seconds
40 end
41
42
43 if (counter == 50000000 )
44 begin
45 clk_led = 0; //turn off clock indicator
46 counter = 0; //reset counter
47 end
48
49 case(timer)
50 1://timer is 1 sec
51 begin
52 main_west = 3'b110;
53 main_east = 3'b110;
54 side_north = 3'b011;
55 side_south = 3'b011;
56 end
57 5://timer is 5 sec
58 begin
59 main_west = 3'b101;
60 main_east = 3'b101;
61 side_north = 3'b011;
62 side_south = 3'b011;
63 end
64 6://timer is 6 sec
65 begin
66 main_west = 3'b011;
67 main_east = 3'b011;
68 side_north = 3'b110;
69 side_south = 3'b110;
70
71 end
72 10://timer is 10 sec
73 begin
74 main_west = 3'b011;
75 main_east = 3'b011;
76 side_north = 3'b101;
77 side_south = 3'b101;
78
79 timer = 0;
80 end
81 endcase
82 //END SECTION 2
83
84 end
85
86
87 else
88 begin
89 counter = 0;
90 timer = 0;
91 main_west = 3'b111;
92 main_east = 3'b111;
93 side_north = 3'b111;
94 side_south = 3'b111;
95 end
96
97 end
98 endmodule