SVS COLLEGE OF ENGINEERING

COIMBATORE-642 109
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

OBSERVATION NOTE BOOK

EC6612 VLSI DESIGN LABORATORY

VI SEM ECE

Name ..

Roll No ..

Year/Sem ..

Branch ..

Subject ..

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB Page |1
SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB Page |2
 SVS COLLEGE OF ENGINEERING
COIMBATORE-642 109
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC6612 VLSI DESIGN LABORATORY

VI SEM ECE

Prepared by,

Mr. K. Manoharan,

Assistant Professor,

ECE Department,

SVS College of Engineering,

Coimbatore-642 109.

Academic Year: 2016-2017

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 INDEX

EX.NO NAME OF THE EXPERIMENTS PAGE NO

1. SIMULATION OF COMBINATIONAL LOGIC CIRCUITS 7

2. SIMULATION OF SEQUENTIAL CIRCUITS 13

3. SIMULATION OF STATE MACHINE USING STATECAD 19

SYNTHESIS OF COMBINATIONAL AND SEQUENTIAL

4. 23
CIRCUIT
PLACE & ROOT AND POST PLACE & ROOT
5. 27
SIMULATION AND STATIC TIMING ANALYSIS
HARDWARE FUSING AND TESTING OF
6. 33
COMBINATIONAL AND SEQUENTIAL CIRCUIT

7. SIMULATION OF DIFFERENTIAL AMPLIFIER 41

LAYOUT GENERATION AND PARASITIC

8. 43
EXTRACTION OF CMOS INVERTER
LAYOUT GENERATION AND PARASITIC
9. 47
EXTRACTION OF BASIC GATES
LAYOUT GENERATION AND PARASITIC
10. 49
EXTRACTION OF DIFFERENTIAL AMPLIFIER
STANDARD CELL BASED DIFFERENTIAL AMPLIFIER
11. 53
DESIGN
PLACEMENT AND ROUTING, POWER AND CLOCK
12. ROUTING, AND POST PLACEMENT AND ROUTING 57
SIMULATION
STATIC TIMING ANALYSIS OF DIFFERENTIAL
13. 61
AMPLIFIER

CONTENT BEYOND SYLLABUS

14. SCHEMATIC DESIGN ENTRY OF 4X1 MULTIPLEXER 63

15. LCD DISPLAY USING FPGA DEVICE 67

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 OBSERVATION NOTE BOOK

CONTENTS
Page Signature
S. No Date Experiments Marks
No of Staff

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8 BIT ADDER LOGIC DIAGRAM

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Exp. No. : 1
SIMULATION OF COMBINATIONAL LOGIC CIRCUITS
Date:

AIM:
To write a Verilog code for the basic logic gates, 8 bit adder and 4 bit multiplier and
simulate it using Xilinx Project Navigator .

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name (adder) and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select Behavioral simulation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source.
7. Select the Verilog Module and give the file name with extension .v click next and declare
ports and select direction click next and finish.
8. Write the Verilog Code and click File
Save.
9. Click verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
10. If the coding has error, it will be displayed in the console window with line number now
remove the errors with proper syntax.
11. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Test Bench Waveform and give the file name, click next and select source name click
next and finish.
12. Select the combinatorial and click finish. Now change the inputs by clicking input line
blue boxes on the graph and save & close the file.
13. Select the test bench file (.tbw) in the source window and expand Xilinx ISE simulator in
Process window and double click Generate expected simulation results.
14. Verify each output for different combinations of inputs.

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4X 4 MULTIPLIER

LOGIC DIAGRAM

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CODING:
BASIC LOGIC GATES:
module gates(a,b,c,d,e,f,g,h,i);
input a,b;
output c,d,e,f,g,h,i;
and(c,a,b);
or(d,a,b);
nor(e,a,b);
nand(f,a,b);
xor(g,a,b);
xnor(h,a,b);
not(i,a);
endmodule

8 BIT ADDER
module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule

module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule

4 BIT MULTIPLIER
module array4(a,b,m);
input [3:0]a,b;
output [7:0]m;
wire [24:1]w;
wire [15:0]p;
and a1(p[0],a[0],b[0]);
and a2(p[1],a[1],b[0]);
and a3(p[2],a[2],b[0]);
and a4(p[3],a[3],b[0]);
and a5(p[4],a[0],b[1]);
and a6(p[5],a[1],b[1]);
and a7(p[6],a[2],b[1]);
and a8(p[7],a[3],b[1]);

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OUTPUT
LOGIC GATES

8 BIT ADDER

4 BIT MULTIPLIER

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and a9(p[8],a[0],b[2]);
and a10(p[9],a[1],b[2]);
and a11(p[10],a[2],b[2]);
and a12(p[11],a[3],b[2]);
and a13(p[12],a[0],b[3]);
and a14(p[13],a[1],b[3]);
and a15(p[14],a[2],b[3]);
and a16(p[15],a[3],b[3]);

fulladder a17(1'b0,p[1],p[4],w[1],w[2]);
fulladder a18(1'b0,p[2],p[5],w[3],w[4]);
fulladder a19(1'b0,p[3],p[6],w[5],w[6]);
fulladder a20(p[8],w[2],w[3],w[7],w[8]);
fulladder a21(p[9],w[4],w[5],w[9],w[10]);
fulladder a22(p[10],p[7],w[6],w[11],w[12]);
fulladder a23(p[12],w[8],w[9],w[13],w[14]);
fulladder a24(p[13],w[10],w[11],w[15],w[16]);
fulladder a25(p[14],p[11],w[12],w[17],w[18]);
fulladder a26(1'b0,w[14],w[15],w[19],w[20]);
fulladder a27(w[16],w[17],w[20],w[21],w[22]);
fulladder a28(p[15],w[18],w[22],w[23],w[24]);

assign m[0]=p[0];
assign m[1]=w[1];
assign m[2]=w[7];
assign m[3]=w[13];
assign m[4]=w[19];
assign m[5]=w[21];
assign m[6]=w[23];
assign m[7]=w[24];
endmodule

module fulladder(a,b,c,s,ca);
input a,b,c;
output s,ca;
assign s=(a^b^c);
assign ca=((a&b)|(b&c)|(c&a));
endmodule

RESULT:
Thus the Verilog code for the basic logic gates, 8 bit adder and 4 bit multiplier are
simulated using Xilinx Project Navigator .

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D FLIP FLOP

JK FLIP FLOP

4 BIT COUNTER

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Exp. No. : 2
SIMULATION OF SEQUENTIAL CIRCUITS
Date:

AIM:
To write a Verilog code for D flip flop, JK flip flop and counter and simulate it using Xilinx
Project Navigator .

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select Behavioral simulation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source.
7. Select the Verilog Module and give the file name with extension .v click next and declare
ports and select direction click next and finish.
8. Write the Verilog Code and click File
Save.
9. Click verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
10. If the coding has error, it will be displayed in the console window with line number now
remove the errors with proper syntax.
11. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Test Bench Waveform and give the file name, click next and select source name click
next and finish.
12. Select the single clock option and select signal as clock and click finish. Now change the
inputs by clicking input line blue boxes on the graph and save & close the file.
13. Select the test bench file (.tbw) in the source window and expand Xilinx ISE simulator in
Process window and double click Generate expected simulation results.
14. Verify each output for different combinations of inputs.

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OUTPUT WAVEFORM

D FLIP FLOP

JK FLIP FLOP

COUNTER

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CODING:
D FLIPFLOP
module d_ff( d, clk, q, q_bar);
input d, clk;
output q, q_bar;
reg q;
reg q_bar;

always @ (posedge clk)

begin
q <= d;
q_bar <= !d;
end

endmodule

JK FLIP FLOP
module jk_ff(clk,j,k,q,qb);
input clk, j, k;
output q,qb;
reg q,qb;

always @(clk,j,k)
begin
if(clk==1)
begin
if(j==0 & k==1)
begin
q=0; qb=~q;
end

else if(j==1 & k==0)

begin
q=1; qb=~q;
end

else if(j==0 & k==0)

begin
q=q; qb=~q;
end

else if(j==1 & k==1)

q=~q; qb=~q;
end
end
endmodule

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 16
COUNTER
module counter (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

RESULT:
Thus the Verilog code for the D flip flop , JK flip flop and counter are simulated using
Xilinx Project Navigator .

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STATE DIAGRAM

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Exp. No. : 3
SIMULATION OF STATE MACHINE USING STATECAD
Date:

AIM:
To design a sequence detector state machine to detect the sequence 1111 and simulate it
using stateCAD in Xilinx Project Navigator.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Accessories

StateCAD
2. Click Draw State Machine
3. Select Geometric, Enter no of states and click next
4. Select synchronous and click next
5. Tick loop back and next and click finish.
6. Edit each state name, input and output values.
7. Save the file click File
Save
8. Options
configurations
Select Verilog click ok
9. Click Generate HDL open the file in the path and take a copy.
10. Click Optimize
Next
11. Select FPGA
Next
12. Select Speed
Next
13. Select Guarantee coverage
Next
14. Select enable buffering and tick Optimize port IO and retain unassigned outputs.
15. Select Verilog
Next
16. Select Xilinx XST
Next
17. Click Generate HDL.
18. Now compare the optimized verilog code with before optimization code.
19. Simulate the design by click state bench
20. Double click the inputs to change the logic value.
21. Click cycle to simulate the design.

CODING
module mano(CLK,inx,RESET,y);
input CLK;
input inx,RESET;
output y;
reg y,next_y;
reg S1,next_S1,S2,next_S2,S3,next_S3,S4,next_S4,SO,next_SO;
always @(posedge CLK)
begin

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OUTPUT

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 20
 if ( RESET ) S1 = 0;
else S1 = next_S1;
end
always @(posedge CLK)
begin
if ( RESET ) S2 = 0;
else S2 = next_S2;
end
always @(posedge CLK)
begin
if ( RESET ) S3 = 0;
else S3 = next_S3;
end
always @(posedge CLK)
begin
if ( RESET ) S4 = 0;
else S4 = next_S4;
end
always @(posedge CLK)
begin
if ( RESET ) SO = 1;
else SO = next_SO;
end
always @(posedge CLK)
begin
if ( RESET ) y = 0;
else y = next_y;
end
always @ (inx or RESET or S1 or S2 or S3 or S4 or SO)
begin
if ( ~RESET & inx & SO ) next_S1=1;
else next_S1=0;
if ( ~RESET & inx & S1 ) next_S2=1;
else next_S2=0;
if ( ~RESET & inx & S2 ) next_S3=1;
else next_S3=0;
if ( ~RESET & inx & S3 | ~RESET & inx & S4 ) next_S4=1;
else next_S4=0;
if ( ~inx & S1 | ~inx & S2 | ~inx & S3 | ~inx & S4 | ~inx & SO | RESET )
next_SO=1;
else next_SO=0;
if ( ~RESET & inx & S3 | ~RESET & inx & S4 ) next_y=1;
else next_y=0;
end
endmodule

RESULT:
Thus the sequence detector state machine to detect the sequence 1111 is simulated using
stateCAD in Xilinx Project Navigator .

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USER CONSTRAINTS :
NET "a[0]" LOC = "P130" ;
NET "a[1]" LOC = "P124" ;
NET "a[2]" LOC = "P118" ;
NET "a[3]" LOC = "P110" ;
NET "a[4]" LOC = "P101" ;
NET "a[5]" LOC = "P91" ;
NET "a[6]" LOC = "P72" ;
NET "a[7]" LOC = "P71" ;
NET "b[0]" LOC = "P174" ;
NET "b[1]" LOC = "P194" ;
NET "b[2]" LOC = "P169" ;
NET "b[3]" LOC = "P159" ;
NET "b[4]" LOC = "P154" ;
NET "b[5]" LOC = "P148" ;
NET "b[6]" LOC = "P142" ;
NET "b[7]" LOC = "P136" ;
NET "cin" LOC = "P138" ;
NET "cout" LOC = "P102" ;
NET "s[0]" LOC = "P116" ;
NET "s[1]" LOC = "P115" ;
NET "s[2]" LOC = "P113" ;
NET "s[3]" LOC = "P112" ;
NET "s[4]" LOC = "P109" ;
NET "s[5]" LOC = "P108" ;
NET "s[6]" LOC = "P107" ;
NET "s[7]" LOC = "P106" ;

SYNTHESIZE REPORT ADDER:

SYNTHESIZE REPORT COUNTER:

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Exp. No. : 4
SYNTHESIS OF COMBINATIONAL AND SEQUENTIAL
CIRCUIT
Date:

AIM:
To generate and analyze the synthesis report of combinational and sequential circuit using
Xilinx Project Navigator.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1
PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select synthesis / Implementation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Verilog Module and give the file name with extension .v click next and declare ports and
select direction click next and finish.
7. Write the Verilog Code and click File
Save.
8. Click Verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
9. If the coding has error, it will be displayed in the console window with line number, now
remove the errors with proper syntax.
10. Expand User constraints and double click Assign package and enter pin location using user
constraints information. If we want see our Pin assignment in FPGA zoom in Architecture
View or Package View
11. Double click Synthesize-XST in the process window.
12. After the HDL synthesizes, Expand Synthesize-XST, now we can view a RTL schematic
and Technology schematic. This schematic shows pre-optimized design in terms of generic
symbols, such as adders, multipliers, counters, AND gates, and OR gates we can view this
by double click View RTL Schematic.
13. Double click the schematic to internal view and Double click outside the schematic to
move one-level back.

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ADDER SCHEMATIC DIAGRAM

ADDER TECHNOLOGY SCHEMATIC DIAGRAM

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 14. The Technological schematic shows a representation of the design in terms of logic
elements optimized to the target device. Double click View Technology Schematic, it
shows LUTs(Look Up Table), carry logic, I/O buffers, and other technology-specific
components.
15. Double click the schematic to expand. Double click the LUT to inner view. This is a Gate
Level view of LUT, if we want see Truth Table and K-Map for your design just click the
respective tabs.
16. Click Generate post synthesis simulation model and view its report.

CODING:
8 BIT ADDER
module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule
module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule
COUNTER
module counter (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule
RESULT:
Thus the synthesize report was generate and analyze for the combinational and sequential
circuits using Xilinx Project Navigator.

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DESIGN SUMMARY

ROUTED DESIGN

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Exp. No. : 5
PLACE & ROOT AND POST PLACE & ROOT SIMULATION
AND STATIC TIMING ANALYSIS
Date:

AIM:
To implement Place and Root and Post Place and Root and perform static timing analysis
using Xilinx Project Navigator.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select synthesis / Implementation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Verilog Module and give the file name with extension .v click next and declare ports and
select direction click next and finish.
7. Write the Verilog Code and click File
Save.
8. Click Verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
9. If the coding has error, it will be displayed in the console window with line number, now
remove the errors with proper syntax.
10. Expand User constraints and double click Assign package and enter pin location using user
constraints information. If we want see our Pin assignment in FPGA zoom in Architecture
View or Package View
11. Double click Synthesize-XST in the process window.
12. Double Click Implementation Design. Now we can view the Implementation report.
13. After implementation we can see the Design Summary, we get the all details about our
design.
14. Expand implementation design and again expand Place & Route, now double click
View/Edit Routed design.

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POST PLACE AND ROUTE WAVEFORM

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 15. Click the different options in the Layer tool bar to ON/OFF pin wires, Pipes, Sites,
switchboxes, components and routes use zoom tools to view. We can see where our IOs
are placed in FPGA. Zoom it to view how Pins are placed in FPGA.
16. Now in the Source window change Synthesis / Implementation in drop-down menu to Post
route simulation.
17. Expand Xilinx ISE simulator and double click simulate post place and route model. We can
view the waveform.
18. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Accessories

Timing Analyzer.
19. File
open Design select the following path
Design File: D:\SVS\Mano\adder.ncd
Physical Constraints file: D:\SVS\Mano\adder.pcf and give ok.
20. Analyze
Against Timing constraints and give ok.
21. Now we can see the Pad to Pad delay time between each input to each output.

CODING:
8 BIT ADDER
module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule

module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 29
TIMING REPORT

Input Output Delay Input Output Delay

Pad Pad (ns) Pad Pad (ns)
a<0> cout 16.24 b<0> s<4> 12.72
a<0> s<0> 9.24 b<0> s<5> 14.58
a<0> s<1> 10.14 b<0> s<6> 15.37
a<0> s<2> 11.34 b<0> s<7> 16.27
a<0> s<3> 11.82 b<1> cout 15.77
a<0> s<4> 13.16 b<1> s<1> 10.26
a<0> s<5> 15.02 b<1> s<2> 10.87
a<0> s<6> 15.81 b<1> s<3> 11.35
a<0> s<7> 16.71 b<1> s<4> 12.69
a<1> cout 15.76 b<1> s<5> 14.55
a<1> s<1> 9.45 b<1> s<6> 15.34
a<1> s<2> 10.86 b<1> s<7> 16.24
a<1> s<3> 11.33 b<2> cout 13.54
a<1> s<4> 12.68 b<2> s<2> 9.80
a<1> s<5> 14.54 b<2> s<3> 9.12
a<1> s<6> 15.33 b<2> s<4> 10.47
a<1> s<7> 16.23 b<2> s<5> 12.32
a<2> cout 12.90 b<2> s<6> 13.12
a<2> s<2> 8.94 b<2> s<7> 14.02
a<2> s<3> 8.48 b<3> cout 13.00
a<2> s<4> 9.83 b<3> s<3> 8.53
a<2> s<5> 11.68 b<3> s<4> 9.93
a<2> s<6> 12.48 b<3> s<5> 11.78
a<2> s<7> 13.38 b<3> s<6> 12.58
a<3> cout 12.39 b<3> s<7> 13.48
a<3> s<3> 8.01 b<4> cout 11.51
a<3> s<4> 9.31 b<4> s<4> 8.57
a<3> s<5> 11.17 b<4> s<5> 10.29
a<3> s<6> 11.96 b<4> s<6> 11.08
a<3> s<7> 12.86 b<4> s<7> 11.98
a<4> cout 10.73 b<5> cout 10.55
a<4> s<4> 7.60 b<5> s<5> 8.14
a<4> s<5> 9.51 b<5> s<6> 10.12
a<4> s<6> 10.31 b<5> s<7> 11.02
a<4> s<7> 11.21 b<6> cout 9.05
a<5> cout 10.33 b<6> s<6> 8.62
a<5> s<5> 7.93 b<6> s<7> 9.52
a<5> s<6> 9.91 b<7> cout 8.19
a<5> s<7> 10.81 b<7> s<7> 8.50
a<6> cout 8.41 cin cout 15.89
a<6> s<6> 7.98 cin s<0> 8.84
a<6> s<7> 8.88 cin s<1> 9.74
a<7> cout 8.18 cin s<2> 10.99
a<7> s<7> 8.49 cin s<3> 11.47
b<0> cout 15.80 cin s<4> 12.81
b<0> s<0> 8.89 cin s<5> 14.67
b<0> s<1> 9.81 cin s<6> 15.46
b<0> s<2> 10.90 cin s<7> 16.36
b<0> s<3> 11.38

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COUNTER
module counter (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin

if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

RESULT:
Thus the implementation of Place and Root and Post Place and Root and static timing
analysis was carried out using Xilinx Project Navigator.

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USER CONSTRAINTS FOR ADDER:
NET "a[0]" LOC = "P130" ;
NET "a[1]" LOC = "P124" ;
NET "a[2]" LOC = "P118" ;
NET "a[3]" LOC = "P110" ;
NET "a[4]" LOC = "P101" ;
NET "a[5]" LOC = "P91" ;
NET "a[6]" LOC = "P72" ;
NET "a[7]" LOC = "P71" ;
NET "b[0]" LOC = "P174" ;
NET "b[1]" LOC = "P194" ;
NET "b[2]" LOC = "P169" ;
NET "b[3]" LOC = "P159" ;
NET "b[4]" LOC = "P154" ;
NET "b[5]" LOC = "P148" ;
NET "b[6]" LOC = "P142" ;
NET "b[7]" LOC = "P136" ;
NET "cin" LOC = "P138" ;
NET "cout" LOC = "P102" ;
NET "s[0]" LOC = "P116" ;
NET "s[1]" LOC = "P115" ;
NET "s[2]" LOC = "P113" ;
NET "s[3]" LOC = "P112" ;
NET "s[4]" LOC = "P109" ;
NET "s[5]" LOC = "P108" ;
NET "s[6]" LOC = "P107" ;
NET "s[7]" LOC = "P106" ;

USER CONSTRAINTS FOR MULTIPLIER

NET "a[0]" LOC = "P101" ;
NET "a[1]" LOC = "P91" ;
NET "a[2]" LOC = "P72" ;
NET "a[3]" LOC = "P71" ;
NET "b[0]" LOC = "P130" ;
NET "b[1]" LOC = "P124" ;
NET "b[2]" LOC = "P118" ;
NET "b[3]" LOC = "P110" ;
NET "m[0]" LOC = "P115" ;
NET "m[1]" LOC = "P113" ;
NET "m[2]" LOC = "P112" ;
NET "m[3]" LOC = "P109" ;
NET "m[4]" LOC = "P108" ;
NET "m[5]" LOC = "P107" ;
NET "m[6]" LOC = "P106" ;
NET "m[7]" LOC = "P102" ;

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 32
Exp. No. : 6
HARDWARE FUSING AND TESTING OF COMBINATIONAL
AND SEQUENTIAL CIRCUIT
Date:

AIM:
To Implement Hardware fusing and testing of 8 bit adder, 4 bit Multiplier and counter using
Xilinx Project Navigator.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select synthesis / Implementation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Verilog Module and give the file name with extension .v click next and declare ports and
select direction click next and finish.
7. Write the Verilog Code and click File
Save.
8. Click Verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
9. If the coding has error, it will be displayed in the console window with line number, now
remove the errors with proper syntax.
10. Expand User constraints and double click Assign package and enter pin location using user
constraints information. If we want see our Pin assignment in FPGA zoom in Architecture
View or Package View
11. Double click Synthesize-XST in the process window.
12. Double Click Implementation Design. Now we can view the Implementation report.
13. After implementation we can see the Design Summary, we get the all details about our
design.

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USER CONSTRAINTS FOR COUNTER
NET "clk" LOC = "P184";
NET "rst" LOC = "P175";
NET "dir" LOC = "P71";
NET "led[3]" LOC = "P123";
NET "led[2]" LOC = "P126";
NET "led[1]" LOC = "P127";
NET "led[0]" LOC = "P128";

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 34
 14. Double click Generate Programming File, Double click Configure Target Device and click
OK.
15. Double click Create PROM File in the ISE iMPACT window, Select Storage Target
Device as Xilinx Flash PROM and click forward.
16. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and
Location and click OK.
17. Select the corresponding .bit file and click Open, Click No to Add Another Device and
Click OK.
18. Double click Generate File.
19. Double click Boundary Scan and Right click on the window and select Initialize
Chain, Now Select the corresponding .mcs file and click open.
20. Click OK in the Device Programming Properties window, Download the Program on to the
kit by Right clicking on the device icon and select program.
21. Verify the output in the target device.

CODING:

8 BIT ADDER
module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;

wire c1,c2,c3,c4,c5,c6,c7;

fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule

module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule

4 BIT MULTIPLIER
module array4(a,b,m);
input [3:0]a,b;
output [7:0]m;
wire [24:1]w;
wire [15:0]p;

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 36
 and a1(p[0],a[0],b[0]);
and a2(p[1],a[1],b[0]);
and a3(p[2],a[2],b[0]);
and a4(p[3],a[3],b[0]);
and a5(p[4],a[0],b[1]);
and a6(p[5],a[1],b[1]);
and a7(p[6],a[2],b[1]);
and a8(p[7],a[3],b[1]);
and a9(p[8],a[0],b[2]);
and a10(p[9],a[1],b[2]);
and a11(p[10],a[2],b[2]);
and a12(p[11],a[3],b[2]);
and a13(p[12],a[0],b[3]);
and a14(p[13],a[1],b[3]);
and a15(p[14],a[2],b[3]);
and a16(p[15],a[3],b[3]);

fulladder a17(1'b0,p[1],p[4],w[1],w[2]);
fulladder a18(1'b0,p[2],p[5],w[3],w[4]);
fulladder a19(1'b0,p[3],p[6],w[5],w[6]);
fulladder a20(p[8],w[2],w[3],w[7],w[8]);
fulladder a21(p[9],w[4],w[5],w[9],w[10]);
fulladder a22(p[10],p[7],w[6],w[11],w[12]);
fulladder a23(p[12],w[8],w[9],w[13],w[14]);
fulladder a24(p[13],w[10],w[11],w[15],w[16]);
fulladder a25(p[14],p[11],w[12],w[17],w[18]);
fulladder a26(1'b0,w[14],w[15],w[19],w[20]);
fulladder a27(w[16],w[17],w[20],w[21],w[22]);
fulladder a28(p[15],w[18],w[22],w[23],w[24]);

assign m[0]=p[0];
assign m[1]=w[1];
assign m[2]=w[7];
assign m[3]=w[13];
assign m[4]=w[19];
assign m[5]=w[21];
assign m[6]=w[23];
assign m[7]=w[24];
endmodule

module fulladder(a,b,c,s,ca);
input a,b,c;
output s,ca;
assign s=(a^b^c);
assign ca=((a&b)|(b&c)|(c&a));
endmodule

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 37
PLL Oscillator Settings
1MH 3.6864MHZ 4MH 25.175MHz
20MHz 24MHz 48MHz 66MHz 80MHz 100MHz
z (-34ppm) z (17.4ppm)
S2 0 0 0 0 1 1 0 0 0 0
S1 0 0 0 1 0 1 0 0 0 0
S0 0 0 0 0 0 1 1 1 1 1
R6 0 0 0 0 0 1 0 0 0 0
R5 1 1 0 0 0 0 0 0 0 0
R4 0 1 0 0 0 0 0 0 0 0
R3 1 0 1 0 0 1 0 1 0 0
R2 1 0 0 0 0 0 0 0 0 0
R1 1 0 1 1 1 1 1 0 0 0
R0 0 1 0 0 0 0 1 0 1 1

V8 0 0 0 0 0 1 0 0 0 0
V7 0 0 0 0 0 0 0 0 0 0
V6 0 0 0 0 0 0 0 0 0 0
V5 0 1 0 0 0 0 0 0 0 0
V4 0 0 0 0 0 1 0 1 0 0
V3 0 0 0 0 0 0 0 1 0 0
V2 1 1 1 1 1 1 1 0 1 1
V1 0 1 0 0 0 1 0 0 0 1
V0 0 1 0 0 0 1 0 1 0 1

( VDW + 8)
CLK frequency = Input frequency * 2
(RDW + 2)(OD)

Where Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)

VCO Divider Word (VDW) = 4 to 511 (0,1,2,3 are not permitted)
Output Divider (OD) = values below

To generate 12 MHz, assume Crystal + frequency or Input frequency =20MHz In general,

VDW + 8
Clock Frequency = Input Frequency x 2
(RDW + 2) (OD)

4+8
Clock Frequency = 20 MHz x 2 = 12 MHz
(18 + 2)(2)

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 38
COUNTER
module counter4b(clk, rst, dir, led);//module declaration
output [3:0] led; // counter output
input clk, rst ,dir; // clock, reset & direction inputs of counter
reg [28:0] cntr = 0;
reg [3:0] led;
always @ (posedge clk)
begin
if (rst == 1'b0) // when rst switch is low,counter is reset.
begin
cntr <= 0;
led <= cntr[28:25];
end
else
begin
if (dir) // when dir is high
begin
cntr <= cntr + 1; // up count
led <= cntr[28:25];
end
else // when dir is low
begin
cntr <= cntr - 1 ; // down count
led <= cntr[28:25];
end
end
end

endmodule

RESULT:
Thus the Hardware fusing and testing of 8 bit adder, 4 bit Multiplier and counter using Xilinx
Project Navigator were implemented.

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 39
DIFFERENTIAL AMPLIFIER

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 40
Exp. No. : 7
SIMULATION OF DIFFERENTIAL AMPLIFIER
Date:

AIM:
To design and simulate the five transistor differential amplifier circuit and measure the Gain,
CMRR and ICMR using Tanner EDA tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE:

1. Open a schematic editor by using Start
Program files
Tanner EDA
Tanner
EDA Tools
S-Edit.
2. Create new design by Click file
New
New Design.
3. Enter the design name and select the path to save the design.
4. Create new cell view
Cell
new view
Select the parameters and give ok.
5. Click add available in library window and select the library file.
6. Select devices in the library drag required PMOS and NMOS components from the
symbol browser and design five transistor differential amplifier circuit.
7. Common mode Inputs are applied to the circuit.
8. To open T spice window click Tools
T- Spice.
9. Insert technology file and required comments using insert comment option in T-
Spice.
10. Run the simulation by clicking simulation
Run simulation.
11. Output waveform is viewed in the waveform viewer (W-edit) now verify the result.
12. Input and output voltages are measured and tabulated for common mode.
13. Step 7 to step 12 is repeated for the differential mode.
14. Now calculate the gain, ICMR, and CMRR.

RESULT:
Thus the simple five transistor differential amplifier was simulated and gain, ICMR, and
CMRR are calculated using Tanner EDA tools.

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 41
SCHEMATIC DIAGRAM

OUTPUT WAVEFORM

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 42
Exp. No. : 8
LAYOUT GENERATION AND PARASITIC EXTRACTION OF
CMOS INVERTER
Date:

AIM:
To design a CMOS layout and extract the parasitic capacitance and resistance using Cadence
EDA tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Cadence EDA Tools 1

PROCEDURE:
STEP 1: Create a library and build a schematic of an Inverter
 Execute Tools
Library Manager in the CIW (Command Interpreter Window) to open
Library Manager.
 In the Library Manager, execute File
New
Library. The new library form appears.
 In the New Library form, type MyDesignLib in the Name section.
 In the field of Directory section, verify that the path to the library is set to ~/
Database/cadence_analog_labs_615 and click OK.
 A Technology File for New library form appears, select option Attach to an existing
technology library and click OK.
 A Attach library to Technology Library form appears, select option gpdk180 from
the cyclic field and click OK
 After creating a new library we can verify it from the Library Manager
 If we right click on the MyDesignLib and select properties, we can find that gpdk180
library is attached as techLib to MyDesignLib.
STEP 2: Adding Components to schematic
 In the Inverter schematic window, click the Instance fixed menu icon to display
the Add Instance form.
 Click on the Browse button. This opens up a Library browser from which we can select
components and the symbol view.
 Move the cursor to the Schematic window and left click to place a component.
 Add the pins and wires to the Schematic as per the logic diagram and save the design.
STEP 3: Set up for transient analysis and run simulations on the Inverter Test design
STEP 4: Creating Layout View of Inverter
STEP 5: Add the Components to Layout
STEP 6: Make the interconnection and Creating Contacts/Vias. Finally save the design.
STEP 7: Physical Verification
i) Run the DRC
ii) Run the LVS (Compare the schematic net list and the layout net list)
iii) Run the Assura RCX

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LAY OUT DIAGRAM

PARASITIC EXTRACTION

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 44
Extracting the capacitance
 Extract the RC values from the layout and perform analog circuit simulation on the
designs extracted with RCX. Before using RCX to extract parasitic devices for
simulation, the layout should match with schematic completely to ensure that all parasites
will be backannoted to the correct schematic nets.
 From the layout window execute Assura
Run RCX.
 Change the following in the Assura parasitic extraction run form. Select Output type
under Setup tab as Extracted View.
 In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and
specify the Reference node for extraction.
 In the Filtering tab of the form, Enter Power Nets as Vdd, Vss Enter Ground Nets as Gnd
 Click OK in the Assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click Watch log file to see the output log file.
 When RCX completes, a dialog box appears which informs that Assura RCX run
Completed successfully. Click on close to terminate the RCX run.
 Double click on av_extracted option under View field. The av_extraced view of design
will pop up.
 Press shift-f to view values of the extracted resistance and capacitance in the av_extracted
view.

RESULT:
Thus the CMOS layout was drawn and the parasitic capacitance and resistance are extracted
using Cadence EDA tools.

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 45
LAYOUT DIAGRAM

INVERTER

TWO INPUT NAND GATE TWO INPUT NOR GATE

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 46
Exp. No. : 9
LAYOUT GENERATION AND PARASITIC EXTRACTION OF
BASIC GATES
Date:

AIM:
To design layout diagram of inverter, two input NAND gate and NOR gate and Simulate and
extract parasitic capacitances using Microwind tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Microwind 1

PROCEDURE:
1. Open microwind by double clicking microwind.
2. Create new design by Click on File
New.
3. Select model file by Click on File
Select Foundry and select the model file.
4. Draw the Metal 1 layer for Vdd and Vss with appropriate distance with width 3.
5. Draw P diffusion for PMOS transistor with width 2.
6. Draw N diffusion for NMOS transistor with width 2
7. Draw the polysillicon layer for each input to cross the N diffusion and P diffusion to form
NMOS and PMOS transistor.
8. Create nwell process for PMOS transistor.
9. Interconnect the MOS transistor as per the requirement.
10. Create contact cut for interconnection of different layers.
11. Click Analysis
Design Rule Check.
12. Correct the errors in the design.
13. To Run Simulation Click Simulate
Start Simulation.
14. View the output waveforms.
15. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation
parameters select MOS model and click extract.

RESULT:
Thus the layout diagram of inverter, two input NAND gate and NOR gate was simulated
and the parasitic capacitances were extracted using Microwind tools.

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 47
CIRCUIT DIAGRAM

Sample: nmos nmos1(d,s,g);

LAYOUT DIAGRAM

SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 48
Exp. No. : 10
LAYOUT GENERATION AND PARASITIC EXTRACTION OF
DIFFERENTIAL AMPLIFIER
Date:

AIM:
To design layout diagram of differential amplifier and extract the parasitic capacitance of the
circuit diagram using Microwind tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Microwind 1

PROCEDURE:

USING VERILOG CODING

1. Open microwind by double clicking microwind2.
2. Create new design by Click on File
New.
3. Select model file by Click on File
Select Foundry and select the model file.
4. Create new text file and type the five transistor differential amplifier net list and save as
verilog file.
5. Click on Compile
Compile Verilog File. Select the verilog text file and click on
Generate.
6. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation
parameters select Mos model and click extract.

CODING
module example( Vbias,Vin1,Vin2,Out);
input Vbias,Vin1,Vin2;
output Out;
pmos pmos1(n1,vdd,n1);
pmos pmos2(Out,vdd,n1);
nmos nmos1(n1,n2,Vin1);
nmos nmos2(Out,n2,Vin2);
nmos nmos3(n2,vss,Vbias);
endmodule

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 50
 DRAWING METHOD
1. Open microwind by double clicking microwind.
2. Create new design by Click on File
New.
3. Select model file by Click on File
Select Foundry and select the model file.
4. Draw the Metal 1 layer for Vdd and Vss with appropriate distance with width 3.
5. Draw P diffusion for PMOS transistor with width 2.
6. Draw N diffusion for NMOS transistor with width 2
7. Draw the polysillicon layer for each input to cross the N diffusion and P diffusion to form
NMOS and PMOS transistor.
8. Create nwell process for PMOS transistor.
9. Interconnect the MOS transistor as per the requirement.
10. Create contact cut for interconnection of different layers.
11. Click Analysis
Design Rule Check.
12. Correct the errors in the design.
13. To extract the parasitic capacitance of the circuit diagram click simulate
Simulation
parameters select model, parameters and Extractor options and click extract.
14. For different extractor options compare the extracted results.

RESULT:
Thus the layout diagram of differential amplifier was designed and the parasitic capacitances
of the circuit diagram were extracted using Microwind tools.

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SCHEMATIC DIAGRAM

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Exp. No. : 11
STANDARD CELL BASED DIFFERENTIAL AMPLIFIER
DESIGN
Date:

AIM:
To design and simulate the Standard cells based differential amplifier using Tanner EDA
tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE:

S- Edit

1. Open a schematic editor by using Start
Program files
Tanner EDA
Tanner EDA

Tools
S-Edit.

2. Create new design by Clicking File
New
New Design.

3. Drag the required PMOS and NMOS components from the Library and Draw the

Differential amplifier and save the design.

4. Create symbol for the Differential amplifier design.

5. Again create new design by Clicking File
New
New Design.

6. Create Differential amplifier core and Pad by inserting the instance of the created symbol

and the required pads and interconnect it. Connect NC for not used ports.

7. Export the schematic as in TPR format by File
Export
Export TPR in the path

D:\SVS\Mano\diff.tpr

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 54
L Edit

1. Launch L-Edit. Use File
New to create your design file (layout file).

2. Click Tools
SPR
Setup. In the SPR Setup dialog select the following files.

Standard Cell Library file: C:\Documents and Settings\Manoharan\My

Documents\Tanner EDA\Tanner Tools \L-Edit and LVS\SPR\Lights\ lightslb.tdb

Net list file: D:\SVS\Mano\diff.tpr

3. Click Initialize setup Icon in the SPR Setup Window.

4. Click Core setup Different optimizations options will be available to choose.

5. Click pad frame Setup Icon and Pad Route Setup Icon in the SPR Setup Window and

Click Ok.

6. Click Tools
SPR
Place and Route. In Standard Cell Place and Route window click

Run.

7. Click the Run button. Depending on your selected options, SPR will generate up to three

new cells: a core cell, a pad frame cell, and/or a chip cell

8. Verify the design using L-Edit design rule check by Tools
DRC.

9. Extract the net list by Tools
Extract.

10. Open the Extracted net list using T-spice and provide the voltage sources and insert

transient analysis comments and insert plot and measure commends and simulate it.

11. Measure the critical paths, average power consumption.

12. Save the design in GDSII format and send it to your vendor for fabrication.

RESULT:
Thus the differential amplifier using Standard cells is designed and simulated, using Tanner
EDA tools.

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 56
Exp. No. : 12 PLACEMENT AND ROUTING, POWER AND CLOCK
ROUTING, AND POST PLACEMENT AND ROUTING
Date: SIMULATION

AIM:
To change the placement and routing, power and clock routing, and post placement and
routing parameters and simulate the design using Tanner EDA tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Tanner EDA Tools 1

PROCEDURE:

S- Edit
1. Open a schematic editor by using Start
Program files
Tanner EDA
Tanner EDA
Tools
S-Edit.
2. Create new design by Clicking File
New
New Design.
3. Drag the required PMOS and NMOS components from the Library and Draw the
Differential amplifier and save the design.
4. Create symbol for the Differential amplifier design.
5. Again create new design by Clicking File
New
New Design.
6. Create Differential amplifier core and Pad by inserting the instance of the created symbol
and the required pads and interconnect it. Connect NC for not used ports.
7. Export the schematic as in TPR format by File
Export
Export TPR in the path
D:\SVS\Mano\diff.tpr

L EDIT
1. Launch L-Edit. Use File
New to create your design file (layout file).
2. Click Tools
SPR
Setup. In the SPR Setup dialog select the following files.
Standard Cell Library file: C:\Documents and Settings\Manoharan\My Documents\Tanner
EDA\Tanner Tools \L-Edit and LVS\SPR\Lights\ lightslb.tdb
Net list file: D:\SVS\Mano\diff.tpr
3. Click Initialize setup Icon in the SPR Setup Window.
4. Click Core setup Different optimizations options will be available to choose.
5. Select the appropriate option singly or in any combination. Depending on your standard
cell design, uncheck or check the Global input signal routing option.
6. Click pad frame Setup Icon and Pad Route Setup Icon in the SPR Setup Window and Click
Ok.
7. Click Tools
SPR
Place and Route. In Standard Cell Place and Route window click
Run.
8. Click the Run button. Depending on your selected options, SPR will generate up to three
new cells: a core cell, a pad frame cell, and/or a chip cell

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 58
 9. Verify the design using L-Edit design rule check by Tools
DRC.
10. Extract the net list by Tools
Extract.
11. Open the Extracted net list using T-spice and provide the voltage sources and insert
transient analysis comments and insert plot and measure commends and simulate it.
12. Save the design in GDSII format and send it to your vendor for fabrication.

PLACEMENT AND ROUTING OPTIONS

1. Choose Tools
SPR
Setup, click core setup change the layers parameter and design rule
parameters.
2. Choose Tools
SPR
Setup, click pad route setup change the layers parameter and
design rule parameters.

POWER AND CLOCK ROUTING OPTIONS

1. Choose Tools
SPR
Setup, click core setup change the power parameter.

POST PLACEMENT AND ROUTING OPTIONS

1. Click Mouse zoom option and zoom the core at required place and view the layout of each
cells in the design.

RESULT:
Thus the placement and routing, power and clock routing, and post placement and routing
parameters are changed and simulate using Tanner EDA tools.

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CIRCUIT DIAGRAM

LAYOUT DIAGRAM

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Exp. No. : 13
STATIC TIMING ANALYSIS OF DIFFERENTIAL AMPLIFIER
Date:

AIM:
To design the layout diagram of differential amplifier and measure static time using
Microwind tools.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Microwind 1

PROCEDURE:
1. Open microwind by double clicking microwind.
2. Create new design by Click on File
New.
3. Select model file by Click on File
Select Foundry and select the model file.
4. Draw the Metal 1 layer for Vdd and Vss with appropriate distance with width 3.
5. Draw P diffusion for PMOS transistor with width 2.
6. Draw N diffusion for NMOS transistor with width 2
7. Draw the polysillicon layer for each input to cross the N diffusion and P diffusion to form
NMOS and PMOS transistor.
8. Create nwell process for PMOS transistor.
9. Interconnect the MOS transistor as per the requirement.
10. Create contact cut for interconnection of different layers.
11. Click Analysis
Design Rule Check.
12. Correct the errors in the design.
13. To Run Simulation Click Simulate
Start Simulation.
14. View the output waveforms.
15. Measure the static timing information from the waveform.

RESULT:
Thus the layout diagram of differential amplifier was designed and static timing was
measured using Microwind tools.

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4X1 MULTIPLEXER

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Exp. No. : 14
SCHEMATIC DESIGN ENTRY OF 4X1 MULTIPLEXER
Date:

AIM:
To draw and implement 4x1 multiplexer using schematic entry using Xilinx Project
Navigator .

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as Schematic and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select Behavioral simulation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source.
7. Select the schematic and give the file name click next and finish.
8. Double click the source file in sources window.
9. Click Add symbol, search for required symbols and click to pick the symbol.
10. Draw the schematic diagram using add wire and use markers for input and output
connection and click File
Save.
11. Expand User constraints and double click Assign package and enter pin location using user
constraints information.
12. Double click Synthesize-XST in the process window.
13. Double Click Implementation Design. Now we can view the Implementation report.
14. After implementation we can see the Design Summary, we get the all details about our
design.
15. Double click Generate Programming File, Double click Configure Target Device and click
OK.
16. Double click Create PROM File in the ISE iMPACT window, Select Storage Target
Device as Xilinx Flash PROM and click forward.

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USER CONSTRAINTS :
NET "s1" LOC = "P130" ;
NET "s0" LOC = "P124" ;
NET "d0" LOC = "P118" ;
NET "d1" LOC = "P110" ;
NET "d2" LOC = "P101" ;
NET "d3" LOC = "P91" ;
NET "y" LOC = "P106" ;

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 17. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and
Location and click OK.
18. Select the corresponding .bit file and click Open, Click No to Add Another Device and
Click OK.
19. Double click Generate File.
20. Double click Boundary Scan and Right click on the window and select Initialize
Chain, Now Select the corresponding .mcs file and click open.
21. Click OK in the Device Programming Properties window, Download the Program on to the
kit by Right clicking on the device icon and select program.
22. Verify the output in the target device.

RESULT:
Thus the 4x1 multiplexer was drawn using schematic entry and implement using Xilinx
Project Navigator.

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USER CONSTRAINTS :

NET "clk" LOC = "p184" ;

NET "rs" LOC = "p83" ;
NET "cs" LOC = "p89" ;
NET "d[0]" LOC = "p90" ;
NET "d[1]" LOC = "p93" ;
NET "d[2]" LOC = "p94" ;
NET "d[3]" LOC = "p96" ;
NET "d[4]" LOC = "p97" ;
NET "d[5]" LOC = "p98" ;
NET "d[6]" LOC = "p99" ;
NET "d[7]" LOC = "p100" ;

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Exp. No. : 15
LCD DISPLAY USING FPGA DEVICE
Date:

AIM:
To write a Verilog code to interface LCD with FPGA kit and display the message SVS ECE
VLSI LAB using Xilinx Project Navigator.

APPARATUS REQUIRED:
S.No Name of the equipment/ software Quantity
1. PC with Windows 1
2. Xilinx Project Navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start
Program files
Xilinx ISE
Project Navigator
2. Click File
New Project
3. Enter the Project Name and select the Project location as
D:\SVS\Mano then select, Source type as HDL and click Next.
4. Select the Device and design flow as follows
Product Category : General Purpose
Family : Spartan3E
Device : XC3S250E
Package : PQ208
Speed : -4
Source Type : HDL
Synthesis Tools : XST(VHDL / Verilog)
Simulator : ISE Simulator
and click next three times and click finish.
5. In the Source window select synthesis / Implementation in drop-down menu
6. Right click on xc3s250e-4pq208 in the source window and select New source. Select the
Verilog Module and give the file name with extension .v click next and declare ports and
select direction click next and finish.
7. Write the Verilog Code and click File
Save.
8. Click Verilog file in source window expand Xilinx ISE simulator in Process window and
double click Check Syntax.
9. If the coding has error, it will be displayed in the console window with line number, now
remove the errors with proper syntax.
10. Expand User constraints and double click Assign package and enter pin location using user
constraints information.
11. Double click Synthesize-XST in the process window.
12. Double Click Implementation Design. Now we can view the Implementation report.
13. After implementation we can see the Design Summary, we get the all details about our
design.
14. Double click Generate Programming File, Double click Configure Target Device and click
OK.

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 68
 15. Double click Create PROM File in the ISE iMPACT window, Select Storage Target
Device as Xilinx Flash PROM and click forward.
16. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and
Location and click OK.
17. Select the corresponding .bit file and click Open, Click No to Add Another Device and
Click OK.
18. Double click Generate File.
19. Double click Boundary Scan and Right click on the window and select Initialize
Chain, Now Select the corresponding .mcs file and click open.
20. Click OK in the Device Programming Properties window, Download the Program on to the
kit by Right clicking on the device icon and select program.
21. Verify the output in the target device.

CODING:
module lcddisp(clk,rs,cs,d); //module port declaration
input clk; // system clock 20 MHz default
output rs; // register select
output cs; // chip select
output [7:0]d; // data bus lines
reg [3:0] i = 0 ;
reg [3:0] j = 0 ;
reg [25:0] sig;
reg [7:0] cmd [0:4] ; // array for storing lcd initialisation commands
reg [7:0] data[0:14]; // array for storing text "SVS ECE VLSI LAB"
reg rs;
reg cs;
reg [7:0] d;

always @ (posedge clk)

begin
cmd[0] <= 8'h38; //lcd initialisation commands
cmd[1] <= 8'h06;
cmd[2] <= 8'h01;
cmd[3] <= 8'h0f;
cmd[4] <= 8'h80;

data[0] <= 8'h53; // S

data[1] <= 8'h56; // V
data[2] <= 8'h53; // S
data[3] <= 8'h20; //
data[4] <= 8'h45; // E
data[5] <= 8'h43; // C
data[6] <= 8'h45; // E
data[7] <= 8'h20; //
data[8] <= 8'h56; //V
data[9] <= 8'h4C; // L
data[10] <= 8'h53; // S
data[11] <= 8'h49; // I
data[12] <= 8'h4C; // L

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SVS COLLEGE OF ENGINEERING / ECE / III ECE /EC 6612 VLSI DESIGN LAB P a g e | 70
 data[13] <= 8'h41; // A
data[14] <= 8'h42; // B

sig <= sig + 1;

case (sig[25:20])
6'b000000 :
rs <= 1'b0;
6'b000001 :
d <= cmd[i]; // lcd initialisation
6'b000010 :
cs <= 1'b1;
6'b000011 : begin
cs <= 1'b0;
i <= i + 1;
if (i < 4)
sig[25:20] <= 6'b000001;
else
begin
sig[25:20] <= 6'b000100;
j <= 0;
end
end
6'b000100 :
rs <= 1'b1;
6'b000101 :
d <= data[j]; // "VI MICROSYSTEMS"
6'b000110 :
cs <= 1'b1;
6'b000111 : begin
cs <= 1'b0;
j <= j + 1;
if (j < 14)
sig[25:20] <= 6'b000101;
else
begin
sig[25:20] <= 6'b000000;
i <= 0;
end
end
default : sig <= 0;
endcase
end
endmodule

RESULT:
Thus the LCD display was interfaced with FPGA kit and the given message SVS ECE VLSI
LAB were displayed using Xilinx Project Navigator.

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 For any suggestions
Please mail
[email protected]

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