Logic Synthesis

Primitive logic gates, universal gates

Truth tables and sum-of-products
Logic simplification
Karnaugh Maps, Quine-McCluskey
General implementation techniques:
muxes and look-up tables (LUTs)
Reminder: Lab #1 due this Thursday!
6.111 Fall 2016 Lecture 2 1
 Late Policies
Lab 1 check-offs sign-up on checkoff queue in lab FIFO during
staffed lab hours.
Please dont assume that you can wait until the last minute!
No check-offs on Friday or Saturday
Lab grade = Checkoff + Verilog grade (equal weighting)
On-time check-off:
20%/day late penalty (no penalty for Friday or Saturday)
Max penalty 80% reduction.
All labs must be checked off before you can start your final
project. Weve learned that if youre struggling with the labs, the
final project wont go very well.

Lpset must be submitted on time.

6.111 Fall 2016 Lecture 2 2

 Schematics & Wiring

IC power supply connections generally not

drawn. All integrated circuits need power!
Use standard color coded wires to avoid
confusion.
red: positive
black: ground or common reference point
Other colors: signals
Circuit flow, signal flow left to right
Higher voltage on top, ground negative voltage
on bottom
Neat wiring helps in debugging!

6.111 Fall 2016 3

 Wire Gauge
Wire gauge: diameter is inversely
proportional to the wire gauge number.
Diameter increases as the wire gauge
decreases. 2, 1, 0, 00, 000(3/0) up to 7/0.

Resistance
22 gauge .0254 in 16 ohm/1000 feet
12 gauge .08 in 1.5 ohm/1000 feet
High voltage AC used to reduce loss

1 cm cube of copper has a resistance of 1.68

micro ohm (resistance of copper wire scales
linearly : length/area)

6.111 Fall 2016 4

 CMOS Forever?

6.111 Fall 2016 Lecture 2 5

 *

* Intel
6.111 Fall 2016 Lecture 2 6
 Timing Specifications
Propagation delay (tPD): An upper bound on the delay
from valid inputs to valid
outputs (aka tPD,MAX)
VIN
VIH

VIL

Design goal:
minimize
VOUT < tPD < tPD propagation
delay
VOH

VOL

6.111 Fall 2016 Lecture 2 7

 Contamination Delay
an optional, additional timing spec

Contamination delay(tCD): A lower bound on the delay

from invalid inputs to invalid
outputs (aka tPD,MIN)

VIN
Do we really need
VIH tCD?
VIL
Usually not itll be
important when we
design circuits with
VOUT > tCD > tCD registers (coming
soon!)
VOH

If tCD is not
VOL specified, safe to
assume its 0.

6.111 Fall 2016 Lecture 2 8

 The Combinational Contract

A B tPD propagation delay

A B 0 1 tCD contamination delay
1 0

A
B

> tCD
Must be ___________

< tPD
Must be ___________
Note:
1. No Promises during
2. Default (conservative) spec: tCD = 0

6.111 Fall 2016 Lecture 2 9

 Functional Specifications
A B C Y
0 0 0 0
Output 1 if at 0 0 1 0
input A least 2 out of 3 of
my inputs are a 1. 0 1 0 0
input B Otherwise, output 0.
output Y
0 1 1 1
input C I will generate a valid
output in no more than 1 0 0 0
2 minutes after
seeing valid inputs 1 0 1 1
1 1 0 1
1 1 1 1
3 binary inputs
so 23 = 8 rows in our truth table

An concise, unambiguous technique for giving the functional

specification of a combinational device is to use a truth table to
specify the output value for each possible combination of input values
(N binary inputs -> 2N possible combinations of input values).

6.111 Fall 2016 Lecture 2 10

 Heres a Design Approach
1. Write out our functional spec as a truth
table
A B C Y 2. Write down a Boolean expression with
0 0 0 0 terms covering each 1 in the output:
0 0 1 0
0 1 0 0
0 1 1 1 Y A BC A BC A BC A BC
1 0 0 0
1 0 1 1
1 1 0 1 This approach creates equations of a
particular form called
1 1 1 1

SUM-OF-PRODUCTS
-its systematic!
-it works!
-its easy! Sum (+): ORs
-are we done yet???
Products (): ANDs

6.111 Fall 2016 Lecture 2 11

 S-O-P Building Blocks
A Z

INVERTER: A 0 1
Bubble indicates 1 0
inversion
A B Z
0 0 0
AND: A B
0 1 0
1 0 0
1 1 1

A B Z
0 0 0
OR: A B 0 1 1
1 0 1
1 1 1

6.111 Fall 2016 Lecture 2 12

 Straightforward Synthesis
Y A BC A BC A BC A BC
We can use
SUM-OF-PRODUCTS
to implement any logic
function.

Only need 3 gate types:

INVERTER, AND, OR

Propagation delay:
3 levels of logic
No more than 3 gate delays assuming gates with an arbitrary
number of inputs. But, in general, well only be able to use gates
with a bounded number of inputs (bound is ~4 for most logic
families).

6.111 Fall 2016 Lecture 2 13

 ANDs and ORs with > 2 inputs

A BC

Chain: Propagation delay increases

linearly with number of inputs

A BC D
Which one should I use?

A BC D
Tree: Propagation delay increases
logarithmically with number of inputs
6.111 Fall 2016 Lecture 2 14
 SOP w/ 2-input gates
Previous example restricted to 2-input gates:

Y A BC A BC A BC A BC

Using the timing specs given to the

left, what are tPD and tCD for this
INV AND2 OR2 combinational circuit?
tPD 8ps 15ps 18ps
Hint: to find overall tPD we need to
tC 1ps 3ps 3ps
D
find max tPD considering all paths
from inputs to outputs.
6.111 Fall 2016 Lecture 2 15
 More Building Blocks

A B Z A B Z
NAND (not AND) NOR (not OR)
0 0 1 0 0 1
0 1 1 0 1 0
A B A B
1 0 1 1 0 0
1 1 0 1 1 0

CMOS gates are naturally inverting so we want to use NANDs and NORs
in CMOS designs

A B Z XOR is very useful when implementing

XOR (exclusive OR)
parity and arithmetic logic. Also used
0 0 0 as a programmable inverter: if A=0,
AB 0 1 1 Z=B; if A=1, Z=~B
1 0 1
Wide fan-in XORs can be created with
1 1 0 chains or trees of 2-input XORs.
6.111 Fall 2016 Lecture 2 16
 NAND NOR Internals

Y
Y

6.111 Fall 2016 Lecture 2 17

 Universal Building Blocks

NANDs and NORs are universal:

= =
= =
= =
Any logic function can be implemented using only NANDs
(or, equivalently, NORs). Note that chaining/treeing
technique doesnt work directly for creating wide fan-in
NAND or NOR gates. But wide fan-in gates can be
created with trees involving both NANDs, NORs and
inverters.

6.111 Fall 2016 Lecture 2 18

 SOP with NAND/NOR
When designing with NANDs and NORs one often makes use of
De Morgans laws: De Morgan-ized NAND symbol

NAND form: A B A B =

NOR form: A B A B =
De Morgan-ized NOR symbol

So the following SOP circuits are all equivalent (note the use
of De Morgan-ized symbols to make the inversions less
confusing): De Morgan-ized
Inverter

AND/OR form NAND/NAND form NOR/NOR form

This will be handy in Lab 1 since All these extra inverters may seem less
youll be able to use just 7400s than ideal but often the buffering they
to implement your circuit! provide will reduce the capacitive load on
the inputs and increase the output drive.

6.111 Fall 2016 Lecture 2 19

 Logic Simplification
Can we implement the same function with fewer gates? Before
trying well add a few more tricks in our bag.
BOOLEAN ALGEBRA:
OR rules: a 11 a 0 a a a a
AND rules: a 1 a a 0 0 a a a
Commutative: a b b a a b b a
Associative: (a b) c a (b c) (a b) c a (b c)
Distributive: a (b c) a b a c a b c (a b) (a c)
Complements: a a 1 a a 0
Absorption: a a b a a a b a b a (a b) a a (a b) a b
De Morgans Law: a b a b a b a b
Reduction: a b a b b (a b) (a b) b

Key to simplification: equations that match the pattern of the LHS

(where b might be any expression) tell us that when b is true, the
value of a doesnt matter. So a can be eliminated from the equation,
getting rid of two 2-input ANDs and one 2-input OR.
6.111 Fall 2016 Lecture 2 20
 Boolean Minimization:
An Algebraic Approach

Lets simplify the equation from slide #3:

Y A BC A BC A BC A BC
Using the identity
A A
For any expression and variable A:

Y A BC A BC A BC A BC

Y BC AC A B
The tricky part: some terms participate in more than one
reduction so cant do the algebraic steps one at a time!
6.111 Fall 2016 Lecture 2 21
 Karnaugh Maps: A Geometric Approach

K-Map: a truth table arranged so that terms which differ by exactly one
variable are adjacent to one another so we can see potential reductions
easily.
A B C Y
Heres the layout of a 3-variable K-map filled in
0 0 0 0 with the values from our truth table:
0 0 1 0
Why did he
0 1 0 0 AB
shade that
row Gray?

0 1 1 1 Y 00 01 11 10
1 0 0 0 0 0 0 1 0
1 0 1 1 C
1 0 1 1 1
1 1 0 1
1 1 1 1 010 011

000 001
Its cyclic. The left edge is adjacent to the right 110 111
edge. Its really just a flattened out cube.
100 101

6.111 Fall 2016 Lecture 2 22

 On to Hyperspace
Heres a 4-variable K-map:

AB
Z 00 01 11 10
00 1 0 0 1
01 0 0 0 0
CD
11 1 1 0 1
10 1 1 0 1

Again its cyclic. The left edge is adjacent to the right edge,
and the top is adjacent to the bottom.

We run out of steam at 4 variables K-maps are hard to draw and

use in three dimensions (5 or 6 variables) and were not equipped
to use higher dimensions (> 6 variables)!
6.111 Fall 2016 Lecture 2 23
 Finding Subcubes
We can identify clusters of irrelevent variables by circling
adjacent subcubes of 1s. A subcube is just a lower dimensional
cube.
AB
Z 00 01 11 10
AB 00 1 0 0 1
Y 00 01 11 10 01 0 0 0 0
CD
0 0 0 1 0 11 1 1 0 1
C
1 0 1 1 1 10 1 1 0 1

Three 2x1 subcubes Three 2x2 subcubes

The best strategy is generally a greedy one.

- Circle the largest N-dimensional subcube (2N adjacent 1s)
4x4, 4x2, 4x1, 2x2, 2x1, 1x1
- Continue circling the largest remaining subcubes
(even if they overlap previous ones)
- Circle smaller and smaller subcubes until no 1s are left.
6.111 Fall 2016 Lecture 2 24
 Write Down Equations
Write down a product term for the portion of each
cluster/subcube that is invariant. You only need to include
enough terms so that all the 1s are covered. Result: a minimal
sum of products expression for the truth table.
AB
00 01 11 10

C
0 0 0 1 0 Y AC BC A B
1 0 1 1 1
Were done!
AB
Z 00 01 11 10
00 1 0 0 1
01 0 0 0 0
CD Z B D BC AC
11 1 1 0 1
10 1 1 0 1
6.111 Fall 2016 Lecture 2 25
 Two-Level Boolean Minimization
Two-level Boolean minimization is used to find a sum-of-products
representation for a multiple-output Boolean function that is
optimum according to a given cost function. The typical cost
functions used are the number of product terms in a two-level
realization, the number of literals, or a combination of both. The
two steps in two-level Boolean minimization are:

Generation of the set of prime product-terms for a given function.

Selection of a minimum set of prime terms to implement the

function.

We will briefly describe the Quine-McCluskey method which was

the first algorithmic method proposed for two-level minimization
and which follows the two steps outlined above. State-of-the-art
logic minimization algorithms are all based on the Quine-McCluskey
method and also follow the two steps above.

6.111 Fall 2016 Lecture 2 26

 Prime Term Generation
F = f(W,X,Y,Z)
Start by expressing your Boolean function using 0- W X Y Z label
terms (product terms with no dont care care entries).
0 0 0 0 0
0 1 0 1 5
For compactness the table for example 4-input, 1- 0 1 1 1 7
output function F(w,x,y,z) shown to the right includes 1 0 0 0 8
only entries where the output of the function is 1 and 1
1
0
0
0
1
1
0
9
10
weve labeled each entry with its decimal equivalent. 1 0 1 1 11
1 1 1 0 14
1 1 1 1 15

Look for pairs of 0-terms that differ in only one bit position and merge
them in a 1-term (i.e., a term that has exactly one entry). Next 1-terms
are examined in pairs to see if the can be merged into 2-terms, etc. Mark
k-terms that get merged into (k+1) terms so we can discard them later.

1-terms: 0, 8 -000 [A] 2-terms: 8, 9,10,11 10-- [D]

5, 7 01-1 [B] 10,11,14,15 1-1- [E]
7,15 -111 [C]
8, 9 100-
8,10 10-0 3-terms: none!
9,11 10-1
Example due to
Srini Devadas
10,11 101- Label unmerged terms:
10,14 1-10 these terms are prime!
11,15 1-11
14,15 111-
6.111 Fall 2016 Lecture 2 27
 Prime Term Table
An X in the prime term table in row R and column K signifies that the 0-
term corresponding to row R is contained by the prime corresponding to
column K.

A B C D E
Goal: select the minimum 0000 X . . . . A is essential -000
set of primes (columns) 0101 . X . . . B is essential 01-1
such that there is at least 0111 . X X . .
1000 X . . X .
one X in every row. This 1001 . . . X . D is essential 10--
is the classical minimum 1010 . . . X X
covering problem. 1011 . . . X X
1110 . . . . X E is essential 1-1-
1111 . . X . X

Each row with a single X signifies an essential prime term since any prime
implementation will have to include that prime term because the
corresponding 0-term is not contained in any other prime.

In this example the essential primes cover all the 0-terms.

F = f(W,X,Y,Z) = XYZ + WXZ + WX + WY

6.111 Fall 2016 Lecture 2 28
 Logic that defies SOP simplification

Full Adder S
Ci A B S Co C/AB 00 01 11 10

0 0 0 0 0 A B 0 0 1 0 1

0 0 1 1 0 1 1 0 1 0

0 1 0 1 0 CO
0 1 1 0 1 Co FA Ci C/AB 00 01 11 10
1 0 0 1 0 0 0 0 1 0

1 0 1 0 1 1 0 1 1 1

1 1 0 0 1 S
1 1 1 1 1

S A B C A B C A B C A B C A B Ci
CO A C B C A B

The sum S doesnt have a simple sum-of-products implementation

even though it can be implemented using only two 2-input XOR
gates.

6.111 Fall 2016 Lecture 2 29

 Logic Synthesis Using MUXes
Truth Table
C B A Y
A
If C is 1 then
Y 0 0 0 0
B copy B to Y,
0 0 1 1
otherwise copy 0 1 0 0
C A to Y 0 1 1 1
A 4-input Mux
1 0 0 0
implemented as
1 0 1 0
a tree
2-input Multiplexer 1 1 0 1
I0 0
1 1 1 1 0
I1 11
S
0
0 Y
I2 11S
A 0
0
B I3 1
0 1S
C Y B 1
A S0 S1
C

schematic Gate
symbol

6.111 Fall 2016 Lecture 2 30

 Systematic Implementation of
Combinational Logic

Consider implementation of some

arbitrary Boolean function, F(A,B)
Full-Adder
... using a MULTIPLEXER Carry Out Logic
as the only circuit element:
0 0
A B C Y
0 1
0 0 0 0
0 2
0 0 1 0
1 3 Cout
0 1 0 0
0 4
0 1 1 1
1 5
1 0 0 0
1 6
1 0 1 1
1 7
1 1 0 1
1 1 1 1 A,B,Cin
6.111 Fall 2016 Lecture 2 31
 Systematic Implementation of
Combinational Logic

Same function as on previous slide, but this

time lets use a 4-input mux

Full-Adder
A B C Y Carry Out Logic
0 0 0 0
0 0 1 0 0 0
0 1 0 0 Cin 1 Cout
0 1 1 1 Cin 2
1 0 0 0 1 3
1 0 1 1
1 1 0 1 A,B
1 1 1 1

6.111 Fall 2016 Lecture 2 32

 Xilinx Virtex II FPGA

XC2V6000:
957 pins, 684 IOBs
CLB array: 88 cols x 96/col = 8448 CLBs
18Kbit BRAMs = 6 cols x 24/col = 144 BRAMs = 2.5Mbits
18x18 multipliers = 6 cols x 24/col = 144 multipliers
6.111 Fall 2016 Lecture 2 Figures from Xilinx Virtex II datasheet 33
 Virtex II CLB

16 bits of RAM which can be configured as a 16x1

single- or dual-port RAM, a 16-bit shift register,
or a 16-location lookup table Figures from Xilinx Virtex II datasheet

6.111 Fall 2016 Lecture 2 34

 Virtex II Slice Schematic

Figures from Xilinx Virtex II datasheet

6.111 Fall 2016 Lecture 2 35

 Virtex II Sum-of-products

Figures from Xilinx Virtex II datasheet

6.111 Fall 2016 Lecture 2 36

 Spartan 6 FPGA

6.111 Fall 2016 Lecture 2 37

 Spartan 6 SliceM Schematic

Figures from Xilinx

Spartan 6 CLB datasheet

6.111 Fall 2016 Lecture 2 38

 Oscilloscope
Cursor
controls

Menu driven
soft key/buttons

6.111 Fall 2016 39

 Oscilloscope Controls

Auto Set, soft menu Signal measurement

keys time,
frequency,
voltage
Trigger cursors
channel, single sweep
slope,
Level
Image capture
Input
AC, DC coupling,
10x probe,
1khz calibration
source,
probe calibration,
bandwidth filter

6.111 Fall 2016 40