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EInfochips Double Patterning Technology

Double patterning technology allows fabs to continue using 193nm lithography to print 20nm and below features. It works by breaking dense patterns into two sparse pattern masks printed sequentially. This doubles the effective pattern density while still using the same lithography wavelength. It allows continued use of existing 193nm tools and facilities for smaller nodes, extending the capabilities of optical lithography.

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Pramod Kumar Reddy
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206 views

EInfochips Double Patterning Technology

Double patterning technology allows fabs to continue using 193nm lithography to print 20nm and below features. It works by breaking dense patterns into two sparse pattern masks printed sequentially. This doubles the effective pattern density while still using the same lithography wavelength. It allows continued use of existing 193nm tools and facilities for smaller nodes, extending the capabilities of optical lithography.

Uploaded by

Pramod Kumar Reddy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SEMICONDUCTOR DESIGN

Double patterning Technology


Challenging finer technology nodes
The technique will allow the fabs to continue using 193nm wavelength
for printing 20nm and below features using the current tools and
manufacturing facilities.
UJJWAL PRAKAS, ASIC ENGINEER, EINFOCHIPS Email:[email protected]

I
n 1965 Gordon Moore, co-founder of Intel, researching various photolithographic techniques
made an observation that the number of such as extreme UV, Nano-imprint lithography and
transistors per square inch on integrated the latest directed self-assembly for nanometer
circuits doubles approximately every two years process nodes. The Extreme ultraviolet uses around
since the integrated circuit was invented. 13nm wavelength for next generation
His prediction has turned to be uncannily accurate photolithography but, unfortunately it hasn't been
as it had become a driving force in the able to intersect the industry roadmap and is
semiconductor industry for setting long-term goals expected to miss the 10nm node too. The lack of a
and targets for research and development. power source, lack of defect free masks, resist
As the semiconductor industry is racing towards technology and metrology infrastructure, have
new technology nodes, the fabs are getting a real postponed the production use of this technology.
hard time to imprint the new masks. The reason The answer to current needs is the double
being simple; Fabs are now reaching the limits of patterning technique. The DP technique will allow
the single exposure 193nm lithography for printing the fabs to continue using 193nm wavelength for
the 20 nm and below, which corresponds to a printing 20nm and below features using the current
layout minimum pitch of around 80 nm. tools and manufacturing facilities. The concept
In order to keep up with the Moores law, the fabs behind Double-patterning technology is to
must adopt lower wavelengths of light or the design breakdown the traditional layout mask of dense
must be split into two sets of alternating structures, patterns into two separate masks of sparse patterns.
each more dense than the other but utilizing the Thus, the actual manufacturing pitch in each mask
resource completely. Not to so say the resource is increased to enable higher resolution and better
being silicon over here. printability. The only additional cost is the need for a
Be it soothing and promising to hear that reducing second mask exposure for each double-patterning
the wavelength could cut our problems but in real layer.
world its quite the opposite. Scientists are There are various processes with which double
SEMICONDUCTOR DESIGN

patterning can be carried


out. The important ones are Original Layout DPT Coloring Mask 1
as:
1. Litho Etch Litho Etch (LELE)
2. Litho Freeze Litho Etch
(LFLE)
Mask 2
3. Self-Aligned Double
Patterning (SADP)
LELE: In this technique the
first pattern is exposed onto
a hard mask. Then the first
pattern is etched into the Figure 1. Double-Patterning Decomposition (Preferred Direction Only)
hard mask. Again a second
pattern is exposed onto the Original Layout DPT Coloring Mask 1
silicon, doubling the pattern
density. And finally double
density pattern is engraved
into the silicon. The
remaining mask is washed Mask 2

away.
LFLE: In this technique the
first pattern is exposed onto
the silicon. The already
developed layer is then Figure 2. Double-Patterning Hotspot Due to a Wire in the Nonpreferred Direction
chemically frozen and
coated with a layer of resist. A second pattern is
Mask 1
exposed, doubling pattern density. The unprotected
silicon is engraved with the final, double-density
pattern in a single etching operation.
SADP: In this technique a dummy pattern is created
on the silicon. Around the dummy lines a film is Mask 2

grown. The newly created film is then removed


except the sidewalls. In the next step the dummy
pattern is removed leaving the sidewalls. The (a) DPT Coloring by splitting
remaining double-density sidewall pattern is then
etched into the silicon. Figure 3. Alternative Double-Patterning Decomposition by
Splitting-and-Stitching
Out of all the discussed techniques SADP is the
most promising and cost effective technique .SADP cell boundary to ensure double patterning with
process uses only one critical exposure and overlay various other cells. Although the second approach
poses no issue. Also SADP process has shown to will lead you to a greater design utilization and die
improve the critical dimension uniformities and line area which you won't be wanting.
edge roughness. In Fig.1 you can see that each of the metal layers is
Now the question comes how is it impacting oriented in the same direction and hence DP
at the backend side of the chip designing? decomposition can be performed without any
So in order to implement the double-patterning you issue.
will be requiring a precoloured library. A To summarize, moving to a new process depend
precoloured library will let the routing tool know mostly on the manufacturing centers and the design
whether a cell has dual coloured, single coloured styles which we use. The main objective for any
or uncoloured next to the cell boundary. You can design center is to increase the yield at the same
also go for a conventional, non-double patterning time keeping the cost low so that the customers can
based placement but there the standard cells be benefited and at this point of time double
should be designed with greater guard band to the patterning is the answer to it.

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