CharFlo-Memory!

TM
A Total Solution for
Characterizing and Verifying Memory IP
from Memory Compilers

Agenda

Introduction
Legends Products and Roadmaps
CharFlo-Memory! Characterization Flow
Memory Characterization with Reliability Check
SpiceCut Technology
Performance Optimization
Power-Gating Solutions
The Conclusion
Appendix: ActiveNet Flow

Legends Products

IP Library Characterization Products

z
z

Charflo-Cell!TM : Automatic Cell/IO Library Characterization

Charflo-Memory!TM: Automatic Memory Characterization

IP Library Model Quality Assurance Products

z

Model Diagnoser-Cell!TM:
Cell Library .Lib Quality Assurance and Defect Repair

Circuit Simulation Products

z
z

MSIM: Accurate-Spice Simulator

Turbo-MSIM: Fast-Spice Simulator

Tools for Semiconductor IP

Characterization and Verification
IP Macros

Compiled Memory

Custom Memory
Characterization
Re-Characterization

Characterization
Re-Characterization

CharFlo-Custom!

CharFlo-Memory!

Build Critical-Path
Circuit by
Global-SpiceCut
User-defined Stimulus &
Measure
*Data Sheet or Spec

Standard/IO
Cell Library
Characterization
Re-Characterization
CharFlo-Cell!

Build Critical-Path
Circuit by
Verification & QA
SpiceCut
Defect Repairing
Turbo-SpiceCut
Model Diagnoser
Build Compiler Model by
Compiler Model Generator

CharFlo-Memory!TM
Push-button Characterization Flow

MSLTM :
MemChar SpiceCut Library, the tool for automating
memory characterization with .Lib-in and .Lib-out

SpiceCutTM :
Critical-path circuit building tool based on layoutextraction with RCs

MemCharTM :
Memory characterization tool with optimization.

MSIMTM :
High-accuracy circuit simulator

CharFlo-Memory!TM
Push-button Characterization Flow
Memory Compiler
Memory Instance
Layout Extraction

Circuit Netlist

.Lib Model

CharFlo-Memory!TM
MSLTM

Spice Model

SpiceCutTM

Circuit Simulator

MemCharTM

Updated
.Lib Model

Verification
Reports

MSIM

In-House and Commercial

Memory Compilers

Legends products have been successfully used for in-house

memory compiler development including 40/45/65/90 nm.
Legend provides push-button characterization tools for

Vendors
Memory Compilers 180nm
YES
Artisan*
YES
Virage
N/A
TSMC*
YES
Faraday*
YES
Virtual Silicon*
YES
Synopsys (Avanti)
N/A
Dolphin Technology*
YES
VeriSilicon*
* Legends customer and/or partner

130nm

90nm

65nm

45/40nm

YES

YES

YES

YES

YES
YES

YES

YES
YES

YES
YES

YES
YES

N/A

YES
YES
YES

YES
N/A

YES

N/A
YES

YES

N/A
N/A
YES

YES

N/A

N/A

N/A

N/A

N/A

N/A means indicated compilers not available

Major Applications
For Commercial Memory Compilers

Incoming QA for high yields

z
z

Analyze the mismatching for re-characterization or not.

Perform reliability checks (e.g. glitch, signal vs noise)

Instance re-characterization at new PVTs

Generate accurate instance models (.lib file), instead of the
interpolating or extrapolating by compiler models

Optimizing voltage supply for low-power designs

Silicon Failure Analysis
Eliminate the timing issues for specific instances as possible
cause of failure, and focus on other potential problems

What-if Analysis
By Using CharFlo-Memory!TM

The matrix of possible variations

z
z
z
z

PVTs (Process, Voltage and Temperature)

Spice models
Bit-cells
MOS device sizes (e.g. W/L) and parasitic R and C

Scenarios
z

Locate minimum voltage supply of low-power designs

to pass the read-margin check
Locate minimum voltage supply of memory banks to
pass the voltage-retention check

CharFlo-Memory!TM
A Complete Solution for Characterization

For both In-house memory compiler and vendors

memory compiler
For both memory characterization and validation
For both pre-sim and post-sim characterization
For

both critical-path circuit and full circuit

characterization

Enable automatic layout RC extraction on active-net

only, which enhance throughputs tremendously

Instance Characterization
Compare with Compiler Models
Compiler timing >> Actual timing
Timing

Timing
Compiler timing < Actual timing

Actual Silicon

Compiler Model
(margin added)

(Instance Model)

Actual Silicon
Design Failure !
Low Yield !

Compiler
Model
(no margin)

(Instance Model)

Slow Design !
Speed Sacrifice !

Memory Size

CharFlo-Memory!TM can produce actual instance model!

Memory Size

Bi-Section Optimization
Bi-Section model in MemCharTM is based upon multicriterion binary search algorithm. The convergence is
controlled by the BiSect Error
Success

Goal

t1

t3

t5

t2

t4

Fail

Time
t1
Setup/Hold
t2
Time
t3
t4
t5

t1
Start
t2
Start
t3 = (t1 + t2) / 2
t4 = (t2 + t3) / 2
t5 = (t3 + t4) / 2
Goal
Fail
Success
Fail
Success
Success

BiSect Error
Norm(t2-t1)
Norm(t3-t2)
Norm(t4-t3)
Norm(t5-t4)

Reliability Checking
Glitch and MetaStability Prevention
Clock

CLK
IN

CLKB
QB

CLK
CLKB

Reliability
Problem !
CharFlo-Memory!
locates glitch-free
metastability-free
setup/hold time

IN
Q
QB

Hold Time = 100 ps

IN
Q
QB

Hold Time = 283 ps

Insufficient Hold Time

Glitches
Safe

DataOut
Clock
IN
Q
QB
IN
Q
QB
DataOut

Setup Time = -6 ps

Insufficient Setup Time

MetaStability
Setup Time = 100 ps

Safe

Reliability Checking
Performance Degrading Prevention
Even functionally working, too short setup/hold time will
prolong the access time which degrades chip performance.
Access
Timing Performance
Time Hard Error Degrading

Functional Region

CharFlo-Memory!TM
locates True setup/hold time

Functional
Failure

Slow Speed
Low Yield !

Stable Access Time

True setup/hold time Setup/Hold Time

Read Margin Check

Sense-Amp Signal vs Internal Noise
Voltage

Bit

BitB
0.1 V

Sense
Sense
Controls Amplifier

Fast Access Time

Low Reliability

Early Sense Time

BitB

Time

CharFlo-Memory!TM can locate

z
z

Bit
0.2 V

Bit and BitB signal

Sense control signal

Any change on voltage supply,

.temp, process corners will impact
Bit, BitB and Sense Controls.

CharFlo-Memory!TM can automate the simulation

output and measurement for reliability check

Determine Read-Margin Setting

Checking for Yields and Speed

Determine Read-Margin setting based upon access time,

Voltage(Bit-BitB) against noise-margin
Read Margin Access Time V(Bit-BitB)
1000
0100
1101
0111
1111

4.3212 ns
1.8824 ns
2.8109 ns
1.8824 ns
1.6969 ns

365.8 mv
95.9 mv
200.6 mv
95.9 mv
68.3 mv

SRAM 8Kx24

Slow

Danger

* Noise margin is 100 mv minimum normally , and 200 mv for the safer.

Wrong Read Margin (RM) setting causes Poor Yield!

Yield

CCS/ECSM Model Support

Timing, Power and Noise

SpiceCut can partition memory circuit to receiver,

driver, and channel-connected blocks (CCB).
Based on those partitions, CharFlo-Memory! can
characterize CCS Timing, Power and Noise models.
CCS Timing Model

Memory Circuit
CCB DO0
AD0

AD0

Memory
Circuit

Load1

Memory
Circuit

Driver

DO0
DI0

AD0 CCB

DI0
Load2

DO0

DI0 CCB
CCS Noise Model

SpiceCut Functions
Circuit

characterization

Extract critical-path circuits for

z
z

Timing / Power simulations

Access / Setup / Hold Time / Minimum Clock

Circuit
z
z
z

verification for

Worst / best wordlines of decoders

Exhaustive address pattern simulation
Coupling analysis

Built-in

RC reduction

Recognize Memory Structure

Memory Cell

Pattern matching with core cell

Locate all memory banks, words
and bits
data_in0

.subckt dual_cell 3 4 5 6 14 16
.alias word = 14
.alias bit = 5
.alias bitb = 4
.alias word2 = 16
.alias bit2 = 6
.alias bit2b = 3
M29 9
8
VDD
7 P L=.40U W=.60U
M30 VDD
9
8
7 P L=.40U W=.60U
M33 0
8
9
11 N L=.40U W=1.37U
M34 0
9
8
11 N L=.40U W=1.37U
M37 4
14 9
11
N L=.40U W=.85U
M38 5
14 8
11
N L=.40U W=.85U
M39 3
16 9
11
N L=.40U W=.85U
M40 6
16 8
11
N L=.40U W=.85U
.ENDS

data_in31

Bit Line
Word Line
read1
write1

TM
SpiceCut
SpiceCutTM
read5
write5

D
E
C
O
D
E
R

Memory Bank

SpiceCut
Commands

Sense Amplifier
data_out0

data_out31

Extract Critical-Path Circuit

Using SpiceCut for Access Time
data-in
Data-in Buffer

Address

Decoder

Active

Word Line

Rd<1>
Rd<2>
Bit Line

Rd<5>

Complete multiple-paths
critical circuit for all PVTs

Active

Sense Amplifier
Data-out Buffer

data-out

Extract Critical-Path Circuit

Using SpiceCut for Setup/Hold Time

SpiceCut provides multiple automatic methods for

extracting critical-path circuits of setup/hold time
toward the reference nodes, such as
z
z
z
z

Latch node
Bit-line control node
Word-line / word-line control node
Memory-cell internal node

The critical-path circuit for setup/hold time is a very

complete one including multiple-paths. That is
good for simulating all PVTs.

Latch Node Example

For Address Setup / Hold Time
Latch output N101 can be automatically located, and then
critical-path circuits extracted for Address setup/hold time.
data-in
Data-in Buffer

Address
Rd<1>
Rd<2>

Word Line

Critical-Path Circuit
Decoder

Rd<5>
Clock

Critical-Path
Circuit

rd<5>

Bit Line
circuit1
circuit2
Clock

Word

in
clk

Latch

Sense Amplifier
Data-out Buffer

data-out

out

N101

Inside Memory-Cell Example

For Data-In Setup / Hold Time
Internal node N1 / N2 of memory cell can be automatically
located, and then critical-path circuits extracted for Data-In
setup/hold time.
data-in

Data-in Buffer

Address
Word Line

Rd<1>
Rd<2>

Decoder

Memory Cell
N1

Bit Line

Rd<5>
Clock
Sense Amplifier
Data-out Buffer

data-out

N2

Critical-Path Circuit for Power

Data -in
Data-in Buffer

Address
Rd <1>
Rd <2>

... Word Line

Decoder
Active

M=1022

Bit Line

Rd <10>

Active

Sense Amplifier

...
Data-out Buffer

Data -out

Performance Optimization
Segmenting MOSFET Loadings

When building critical-path circuits, segment those inactive

MOSFETs, resistors and capacitors on the nets with heavy
loadings, such as
z
z
z

Word-lines,
Bit-lines and
Nodes along critical-path circuits

Example: word-line segment

Active
Cell

Active
Cell
Inactive
Cell

Inactive
Cell

Inactive
Cell

Inactive
Cell

M=n1

M=n2

M=n3

M=n4

Performance Optimization
Segmenting MOSFET Loadings
45nm 256K SRAM using Subcircuit Spice model, with about
1.7 Million MOSFETs
Accuracy
Comparison
Access
Time

Speed and
Memory Usage
Comparison
Access
Time

Accuracy
Differences

Before Segment

After Segment

50,488 MOSFETs

10,292 MOSFETs

Rise

Fall

Rise

Fall

Rise

Fall

325.94p

351.53p

324.95p

351.98p

0.30%

0.13%

Before Segment

After Segment

50,488 MOSFETs

10,292 MOSFETs

CPU
Time

Memory
Usage

CPU
Time

Memory
Usage

CPU
Time

Memory
Usage

8,279 sec

3.8 GB

674 sec

1.6GB

12.28X

2.38X

Improvement

Power Gating Solutions

SpiceCut for Building Critical-Path Circuits

SpiceCut automatically recognizes Virtual_Vdd and

Virtual_VSS in memory circuits with Power Gating
On Virtual_Vdd / Virtual_VSS, SpiceCut executes
z RC reduction and port merging
z MOSFET segmenting on loadings
Based on Power Gating structures,
SpiceCut enables
z Memory structure recognition
z Path tracing/pattern identification
z Critical-path circuits generation

Legend and Foundry

Legends tools have been adopted and siliconproven by major foundries

* TSMC
* UMC
* Dongbu
* Vanguard

* HHNEC
* Jazz
* Tower

Direct access the updated SPICE models

* TSMC
* UMC
* IBM
* Vanguard
* X-FAB

* Chartered
* SMIC
* Tower
* Jazz

Legend and Library Vendors

Support

push-button re-characterization for

Artisan
Virage
TSMC
Virtual-Silicon
The

Dolphin Technology
Faraday (UMC Alliance)
VeriSilicon
Synopsys

instance models using Legends tools have

been silicon-proven by customers and major
foundries.

The Conclusion
Legends Memory Characterization

Production and silicon proven including 45nm/65nm

Automatically build critical-path circuits and
structures from layout-extracted circuit with RC
Access memory internals and reliability checking
Optimized critical-path circuits for Power-Gating
RC reduction and active-net extraction for speed
Support CCS timing, power and noise models
Foundry and IP vendors support
Excellent price-performance and automation

Appendix
ActiveNet Method for
Efficient Layout Extraction

Active Nets Flow I

Generate Active Nets for Layout Extraction
Memory Instance
Schematic Spice
Netlist

Programmable MSL
Specification

MSLTM

Layout GDS2
File

Interpret to
SpiceCut
Controls

SpiceCutTM
Critical-path circuits

List of Active Nets in

Critical-path Circuits

Layout Extraction Tools

StarRC-XTTM
Calibre xRCTM

Active Nets Flow II

Characterization based on Active Nets
StarRC-XTTM
Calibre xRCTM

Layout Extraction Tools

Layout-extracted Spice Netlist

with RC on Active Nets only

Programmable MSL
Specification

MSLTM
SpiceCutTM
MemCharTM

Customized by
compiler designs

Interpret to
SpiceCut Controls

Build critical-path
circuits

Perform memory characterization