Leena, Mr. Subham Gandhi and Mr.

Jitender Khurana

21

Implementing (7, 4) Hamming Code using CPLD

on VHDL
Leena, Mr. Subham Gandhi and Mr. Jitender Khurana
Abstract: During communication when data is transmitted from
sender to receiver then an error occurs. So there are various
technique used to detect and correct error. One of them is
Hamming Code which we use in this paper. Using Hamming
Code is this paper has advantage that we are implementing the
technique in VHDL software.. In order to do that the proposed
method uses a complex programmable logic device (CPLD).It is
known that CPLD provides quick implementation and fast
hardware verification. It gives facilities of reconfiguring the
design construct unlimited number of times. Hence, an attempt
is made to implement the Hamming Code for detecting and
correcting errors.
Index Terms:-Complex Programmable Logic Device (CPLD),
Very High Speed Integrated Circuit Hardware Description language
(VHDL), Xilinx, redundancy.

I. INTRODUCTION
Coding theory is concerned with reliability of
communication over noisy channels. Error correcting codes
are used in a wide range of communication systems from
deep space communication, to quality of sound in compact
disksand wireless phones. In computers, data of any kind is
stored and processed as binary digits (or bits for short). A bit
is a 0 or a 1. Every letter has an ASCII code. For example,
the ASCII code of the letter A is 01000001. Typically,
data consists of billions of bits. Digital data is transmitted
over a channel (which could be a wire, network, space, air
etc.), And there is often noise in the channel. The noise may
distort the messages to be sent. Therefore, what the receiver
receives may not be the same as what the sender sends. The
goal of coding theory is to improve the reliability of digital
communication by devising methods that enable the receiver
to decide whether there have been errors during the
transmission (error detection), and if there are, to possibly
recover the original message (error correction).[1]
A. ERROR
Error simply means that while transmitting data bits there
may be change of bits either from 0 to 1 or from 1 to
0.This change may occur due to external interference or
from noise. There are two types of errors.
Single error in which one bit is change.
Burst error in which more than one bits are changed.
There are various error detection and correction techniques
such as CRC, Parity check,LRC, VRC Hamming Code.
Hamming Code is the better way to detect and correct single
error which was given by R.W Hamming in 1950[2].
Leena is Mtech Student, Mr. Subham Gandhi and Mr. Jitender Khurana are
working as Associate Professor, Deptt. Of ECE, SBMN Engg.
College,AsthalBohar,Rohtak, Emails: [email protected],
[email protected], [email protected]

B. HAMMING CODE
Hammings development [Ham] is a very direct construction
of a code that permits correcting single-bit errors. He
assumes that the data to be transmitted consists of a certain
number of information bits, and he adds to these a number of
check bits p such that if a block is received that has at
most one bit in error, then p identifies the bit that is in error
(which may be one of the check bits). Specifically, in
Hamming code p is interpreted as an integer which is 0 if
no error occurred, and otherwise is the 1-origined index of
the bit that is in error. Let k be the number of information
bits, and m the number of check bits used. Because them
check bits must check themselves as well as the information
bits, the value of p ,interpreted as an integer, must range
from 0 to which is distinct values. Because m bits can
distinguish cases, we must have
2m m+k+1
This is known as the Hamming rule [3].
This project attempts to correct and detect the errors using
VHDL. As when we transmit any signal its bits can be
changed due to external interference so the signal get
corrupted . Hamming codes are used to correct the eroor and
when it is implemented in VHDL. Being an electronic
system it is reliable, compact and maintenance free. VHDL
makes the system versatile as the on off times can be easily
varied by changing the delay loops through software. [3]
II. CPLD
Complex Programmable Logic Device (CPLD) A
Complex Programmable Logic Device (CPLD) is a
programmable logic device with complexity between that of
PALs and FPGAs, and architectural features of both. The
maximum clock frequency is 20 MHz and hence it is faster
than microcontroller. The use of CPLDs (Field
Programmable Gate Arrays) and configurable processors is
an interesting new phenomenon in embedded development is
a combination of a fully programmable AND/OR array and a
bank of macro cells. The AND/OR array is reprogrammable
and can perform a multitude of logic functions.. Complex
Programmable Logic Devices (CPLDs) are exactly what they
claim to be. These are designed to appear just like a large
number of PALs in a single chip, connected to each other
through a cross point switch. They use the same development
tools and programmers, and are based on the same
technologies, but they can handle much more complex
logic and more of it.

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013

Leena, Mr. Subham Gandhi and Mr. Jitender Khurana

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Xilinx is a vendor of CPLD products and manufactures a

family known as the XC9500. In this project Xilinx ISE8.1
version is used. CPLDs enable ease of design, lower
development costs, and more product revenue for your
money, and the opportunity to speed your products to market.
Ease of Design: CPLDs offer the simplest way to implement
a design. Once a design has been described, by schematic
and/or HDL entry, you simply use CPLD development tools
to optimize, fit, and simulate the design. The development
tools create a file that is used to customize (that is, program)
a standard off-the-shelf CPLD with the desired functionality.
This provides an instant hardware prototype and allows the
debugging process to begin. If modifications are needed, you
can enter design changes into the CPLD development tool,
and re-implement and test the design immediately.

Fig 2. Design Flow for CPLD

Fig1. CPLD kit

III. IMPLEMENTING DESIGN ON CPLD
The process of implementing a design on an CPLD can be
broken down into several stages, loosely definable as design
entry or capture, synthesis, and place and route.

A. RTL Simulation:
After design entry, the design is simulated at the registertransfer level (RTL). This is the first of several simulation
stages, because the design must be simulated at successive
levels of abstraction as it moves down the chain toward
physical implementation on the CPLD itself. RTL simulation
offers the highest performance in terms of speed.
B. Synthesis Process
The next level in the design process is synthesis.. RTL is sent
through a synthesis tool that produces a netlist of hardware
components needed to actually build the system. After the
synthesis tool the net list is used to desing the logic
network.Verification at this level consist of simulations to
ensure that logic is correct.
C. Gate Level Simulation Process:
Simulation can be used to help optimize the design and refine
the logic, though designers need to be careful not to use it in
the undisciplined software-style code-and-fix mode.
After design synthesis, but before physical implementation,
functional simulation is used to help verify the design. The
goal of functional simulation is to ensure that the logic of the
design does what you want it to do, per the specification, and
that it produces the correct results.

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013

Leena, Mr. Subham Gandhi and Mr. Jitender Khurana

23

D2= 0

D3= 0

D4= 0

D5= 0

D6= 0

P1=d0, d2, d4, d6

P2=d1 ,d2 ,d4,d6;
P3=d3, d4,d5,d6;

Fig 3. Final Gate Level Simulation Stages

IV. VHDL
VHDL (Very high speed integrated circuit Hardware
Description Language) became IEEE standard 1076 in 1987.
It was updated in 1993 and is known today as "IEEE
standard 1076 1993.Another language of HDL is VERILOG.
It is used in electronic design automation to describe digital
and mixed signal systems such as field-programmable gate
array.
IV. IMPLEMENTATION OF HAMMING CODE ON
CPLD USING VHDL
A.
ENCODING OF HAMMING CODE
Now, the design of Hamming Code (7, 4) is to be done on
CPLD kit using VHDL. (7,4) means that there are 4-data bits
and and we need 3-parity bits to send along with these data
bits to make it 7-bit codeword. Even parity is used in.Data
bits are d2,d4,d5,d6; and parity bits are p1,p2,p3.
Where d0 is Ist bit which is given as: d0=20=1
D1 is 2nd bit and is given as : d1=21=2
D3 is 4th bit and is given as : d3=22=4
D0= 0

D1= 0

0
1

D6

D5

D4 D3

P3

P2

P1

D2

D1 D0

Where 0001 is data and p1,p2, p3 are parity bits which take
the position 2m where m =0,1,2,3---------------so on . which
are check bits.
For calculating p1:Count the number of 1s in d1,d3,d5,d7 ,if there are even
number of 1 then p1=0 otherwise it is 1.
Therefore, p1=1
For calculating p2:Count the number of 1s in d2,d3,d6,d7 ,if there are even
number of 1 then p1=0 otherwise it is 1.
Therefore, p2=1
For calculating p3:Count the number of 1s in d4,d5,d6,d7 ,if there are even
number of 1 then p1=0 otherwise it is 1.
Therefore, p3=1
Therefore the 7-bit codeword is
0

D6

D5

D4 D3

D2

D1 D0

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013

Leena, Mr. Subham Gandhi and Mr. Jitender Khurana

Fig 4. Transmitted Data

24

D6

D5

D4 D3

D2

D1 D0

7 bit codeword at Receiver

0

D6 D5

D4 D3

D2

D1 D0

Thus an error occurs at 4-th bit

So the error is detected using VHDL

Fig5. 7-bit data

B. DECODING OF HAMMING CODE
When this 7-bit codeword is sent then during transmission
error occurs which change the bits from 1 to 0 or 0 to 1.
7 bit codeword at Transmitter
Fig 6. Data with error

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013

Leena, Mr. Subham Gandhi and Mr. Jitender Khurana

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Fig 7.ERROR DETECTED

Thus the error is detected and it is corrected for successful
transmission of data.

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013

Leena, Mr. Subham Gandhi and Mr. Jitender Khurana

26

Fig 8. Data after correction.

Fig 8.Removal of error and corrected data

V. CONCLUSION
Thus from this we came to conclusion that Hamming Code is
better than any other method for error detection and
correction .Implementing this technique using VHDL
software proves much better as it can be be implemented as
many times by programming
and also much less
complicated and require less complicated circuitry than
hardware implementation .
REFERENCES
[1] Nuh Aydin:An Introduction to Coding Theory via Hamming
Codes. Department of Mathematics Kenyon College .
[2] Hamming, R. W. 1950. Error-detecting and error-correcting
codes. Chapter15-2.
[3] Rashmi, Anurag Sharma, VHDL based Multiple Traffic Lights
Controller, InternatIonal Journal of electronics &
communication technology259 IJECT Vol.2, Issue 3sept2011
[4] Behrouz A. Forouzan: Data Communications and Networking.
[5] R. E. Blahut, Theory and Practice of Error Control Codes,
Addison-Wesley, New York, 1983

International Journal of New Trends in Electronics and Communication (IJNTEC)..Vol.1, Issue. 1, Aug. 2013