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DLD Assignment 4 PartB M2014 VKM

This document outlines an assignment for a digital logic design course. It contains 6 questions covering topics like number systems, addition/subtraction circuits, binary coded decimal, and Karnaugh maps. Question 1 involves simplifying expressions for the sum and carry of 3-bit addition, as well as drawing the circuit. Question 2 covers decimal to BCD encoding and decoding. Question 3 implements half and full adders/subtractors for problems. Question 4 requires using Karnaugh maps to simplify Boolean expressions. Question 5 performs subtraction problems using different number representations. Question 6 involves drawing circuits from the Karnaugh map problems and writing some expressions in product of sums form.

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Sreedharreddy Ac
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13 views

DLD Assignment 4 PartB M2014 VKM

This document outlines an assignment for a digital logic design course. It contains 6 questions covering topics like number systems, addition/subtraction circuits, binary coded decimal, and Karnaugh maps. Question 1 involves simplifying expressions for the sum and carry of 3-bit addition, as well as drawing the circuit. Question 2 covers decimal to BCD encoding and decoding. Question 3 implements half and full adders/subtractors for problems. Question 4 requires using Karnaugh maps to simplify Boolean expressions. Question 5 performs subtraction problems using different number representations. Question 6 involves drawing circuits from the Karnaugh map problems and writing some expressions in product of sums form.

Uploaded by

Sreedharreddy Ac
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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[DLD-M14-Asgnt4B-VKM]

Digital Logic Design


Assignment 4 Part B
Topic: Number System and Karnaugh Maps
Note:- 1. Use A4 sheets only (write Name, Roll #, T # at top-right).
2. Submission date/ time due: 26 Sep 14 (Saturday), 10 am
3. * marked questions are optional, but carry bonus marks.
Q1:

(a)

(b)

Three bits X, Y, Z are to be added.


(i) Simplify the expression for sum S and carry C,
(ii) Express S and C in canonical form,
(iii) Simplify standard form SoP for S and C, and
(iv) draw circuit diagram to implement it, using AND, OR, NOT gates only.
Consider subtraction: x y, where x = 5 and y = 7.
nd
For the subtraction of bits in 2 column from LSB side (i.e., for x2 y2):
(i) write truth-table,
(ii) write Boolean expression for difference D and borrow B as Sum of Product
form,
(iii) write Boolean expression for D and B in canonical form, i.e., sum of minterms
(iv) Simplify standard form SoP expressions
(v) Implement the circuit using AND, OR,INV gates only.

Q2:

(a) Draw circuit diagram for Decimal to BCD (i) encoder and (ii) decoder
(b)* Draw circuit diagram for BCD to 7-segment LED decoder.

Q3:

(a)
(b)
(c)
(d)

Q4:

Simplify below Boolean expressions in Sum of Products form, using Karnaugh Maps:
(a)
Z = f(x,y,z) = m(0,1,2,5,7) [Dont use Dont care]
(b)
Z = f(x,y,z) = m(0,4,2,6) [Dont use Dont care]
(c)
Z = f(x,y,z) = m(1,2,4,7) [Dont use Dont care]
(d)
Z = f(x,y,z) = m(1,2,4,6,7) [You can use Dont care]
(e)
Z = f(A,B,C)= A + BC + BC
(f)
Z = f(A,B,C)= ABC + BC + BC + ABC
(g)
Z = f(A,B,C,D)= ABC + BCD + ABCD + ABC ) [Dont use Dont care]
(h)
Z = f(A,B,C,D)= ABC + BCD + ABCD + ABC ) [You can use Dont care]

Implement Q1(a) using 2 Half-adders


Implement Q1(b) using 2 Half-subtractors
Draw block diagram to add 9 and 14, using cascaded Full adders.
Draw block diagram to subtract 12 7, using cascaded Full subtractors.

Q5:
Perform below subtraction using (a) Signed magnitude, (b)1s complement, (c) 2s
complement representation. Assume 8 bit register.
(i)
54 67
(ii)
127 128
(iii)
96 63
(iv)
127 - 255
Q6:

(a)
(c)*

Draw circuit diagrams for Q4.


Solve Q4(a),(d), (f) and (g) as Product of Sums form

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