DLD Exp 8 Student Manual
DLD Exp 8 Student Manual
this, even if the clock has not reached a positive edge. That is, it sets Q to zero as fast as it
can. The asynchronous clear is often used to reset flip flops to some initial value. But for
synchronous clear, Q will be 0 if the clear is active when the clock is in a positive edge.
There are different ways to design a D flip-flop. In this lab sheet, only one way is shown.
Students will be familiar about other ways in their theory class.
Figure1: Logic circuit a positive edge triggered D flip-flop without preset and clear
capability.
Figure 2:Graphical Symbol of a positive edge triggered D flip-flop without preset and clear
capability.
Figure3:Logic circuit a positive edge triggered D flip-flop with preset (active low) and
asynchronous clear (active low) capability.
Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB)
Figure4: Graphical symbol of a positive edge triggered D flip-flop with preset (active low)
and asynchronous clear (active low) capability.
K
0
1
0
1
Q(t+1)
Q(t)
0
1
~ Q(t)
Figure 9: IC-7474
Figure10: IC-7476
Pre Lab Homework:
1) Learn the differences between a combinational logic and sequential logic.
2) Learn about different terminologies of clock such as positive edge, negative edge.
3) Learn the difference between level triggered and edge triggered devices.
Apparatus:
IC :
2[pcs]
Implement the circuits shown in fugure1, figure3, figure5 and figure7 on the trainer board
and observe the input-output characteristics. Use pulse switch as clock. Generate timing
diagrams from the implemented circuits.
Simulation and Measurement:
Timing Diagram of a positive edge trigged D flip-flop without Preset and Clear capability:
Figure11: Timing Diagram of a positive edge triggered D Flip-Flop without preset and clear
capability. Output only samples the input when the clock has a positive edge and remains
unchanged for the next positive edge.
Reference:
1. Fundamentals of Digital Logic with verilog design by Brown &Vranesic
2. www.wikipedia.org
3. http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Seq/flip.html