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Static Timing Analysis (STA) Using EDA Tool - Part1 - VLSI Concepts

This document discusses how to perform static timing analysis (STA) using EDA tools. It explains that while tools are intelligent, users still need to understand basics and set various options and settings within the tools. The document outlines different types of timing analysis that can be done, such as setup/hold/recovery/removal constraints. It also lists various necessary input data formats that tools require, such as timing libraries, netlists, and parasitic data formats. Finally, it states that the next blog post will provide more details on these topics.

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Narendra Achari
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99 views

Static Timing Analysis (STA) Using EDA Tool - Part1 - VLSI Concepts

This document discusses how to perform static timing analysis (STA) using EDA tools. It explains that while tools are intelligent, users still need to understand basics and set various options and settings within the tools. The document outlines different types of timing analysis that can be done, such as setup/hold/recovery/removal constraints. It also lists various necessary input data formats that tools require, such as timing libraries, netlists, and parasitic data formats. Finally, it states that the next blog post will provide more details on these topics.

Uploaded by

Narendra Achari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Thursday,July26,2012

StaticTimingAnalysis(STA)UsingEDAToolPart1

5.1

5.2

STAUsingEDAtool(Part1)

STAUsingEDAtool(Part2)

TillNow,IhavediscussedsomanybasicabouttheSTAandothertopicsbutnowthequestioniswhere
and how we can use these basics in the real world. Whats the practical use of these basics? Someone
asked me long time back that now a days, EDA tools are enough intelligent that they can solve the
problemveryeasilyandverywell,thenwhyshouldIknowallthebasics?Hewasright(not100%),thing
istoolsareintelligentbutuptoacertainlimit.Stilltherearelotofthings/settingswhichyouhavetoset
insidethetools(likeoptions/switches/settings),beforerunningthosetoolsonyourdesign.
Basicsarepillarsforanypracticaluses,buthewascorrectbecauseuntilwedontknowhowandwhereto
usethesebasics,wewillalwayshavesuchquestions.
IwasthinkingtocapturetheflowofSTA(Statictiminganalysis)ingeneral(independentofanyspecific
EDA tool) but I faced a lot of problem in generalizing the different concepts. So I have used
PrimeTime/Encounter Timing system (PT/ETS), which are industry standard EDA Tool for the Timing
Analysis,formyBlogasareference.IhavecapturedonlythoseinforelatedtoPT/ETSwhichisonthe
basisofmyexperienceandeasilyavailableontheinternet.

FeaturedPost

TypesOfClockSkew

ClassificationOfClockSkewIntheprevio
havediscussedabouttheSkew
Inthisarticlewewill...

Note: For explanation purpose, there are chances that I have picked any example which is/are not
supported by Primetime/ETS, so dont consider this Blog as a user guide for Primetime/ETS. Please
refer/contact Synopsys Document/support team for the any help related to PrimeTime and Cadence
CommunityforanyhelprelatedtoEncounterTimingSystem.
NowbeforewestartperformingtheStaticTimingAnalysis,weshouldknowfollowingtypeofinfo
Whattypeofanalysiswewanttoperform?

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Whethertooliscapabletodothat?
Ifyes,whatshouldbetheinputdataandinwhichformat?
WhatarethesettingswehavetodointhatspecificEDAtool?
Letsstartwiththetypeofanalysis/checkingwecanperform.Therearedifferenttypesofanalysiswecan
do as per the complexity of the design / technology node /specification of design (or we can say the
applicationofthedesign).Fewofthemarelistedbelow(Iamnotgoingtodescribethedetailsofthosein
thisblogbecausefewarealreadydiscussedandfewIwillpostlateron).

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TypesofCheckingPerformed
Setup,hold,recovery,andremovalconstraints
Clockgatingsetupandholdconstraints
Minimumperiodandminimumpulsewidthforclocks
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12/1/2016

StaticTimingAnalysis(STA)UsingEDAToolPart1|VLSIConcepts

Designrules(minimum/maximumtransitiontime,capacitance,andfanout)
AnalysisFeatures
MultipleclocksandclockfrequenciesAnalysis
Transparentlatchanalysis
Simultaneousminimum/maximumdelayanalysisforsetupandhold

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Bestcase(bc),worstcase(wc),bc_wc,OCV/AOCVanalysis
Caseanalysis(analysiswithconstantsorspecifictransitionsappliedtospecifiedinputs)

Bridging Gap Between


Acdamia and Industry

Mode analysis (analysis with modulespecific operating modes, such as test mode,
functionalmode,scanmode)

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Bottleneckanalysis(reportingofcellsthatcausethemosttimingviolations)
ECO analysis without modifying the original netlist, using inserted buffers, resized
cells,andmodifiednets

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3,852,418

SignalIntegrityAnalysis(crosstalkeffectsbetweenphysicallyadjacentnets)
Noiseanalysis
StatisticalTiminganalysis
Pathbased/GraphBasedanalysis

Nowonceyouwillchoosethetypeofanalysis,nextiswhetheryourTiminganalysistoolsupportthese
type of analysis and till what accuracy. As such most of the analysis type is common and all the tools
supportthese.ButstillitsworthtocheckthisbeforestartingSTA.
Nowwhatshouldbetheinputdataandinwhatformat.Fewofthenecessarydataarelistedbelowwith
differenttypeofformats.
.db
VHDL

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Model":StaticTiming
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Delay"Interconnect
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"SetupandHoldTime"
:StaticTimingAnalysis
(STA)basic(Part3a)

StandardDelayFormat(SDF)
Parasiticdata
StandardParasiticExchangeFormat(SPEF)
SynopsysBinaryParasiticFormat(SBPF)
ReducedStandardParasiticFormat(RSPF).
Timingconstraints
SynopsysDesignConstraints(SDC).
NowintheNextBlogwewilldiscussalltheseinmoredetail.

"SetupandHoldTime
Violation":Static
TimingAnalysis(STA)
basic(Part3b)
"ExamplesOfSetup
andHoldtime":Static
TimingAnalysis(STA)
basic(Part3c)
"TimeBorrowing":
StaticTimingAnalysis
(STA)basic(Part2)
10WaystofixSETUP
andHOLDviolation:
StaticTimingAnalysis
(STA)Basic(Part8)

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EffectofWireLength
OntheSlew:Static
TimingAnalysis(STA)
Basic(Part7a)

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