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Experiment-1: 1. For Threshold Voltage

The document describes experiments to characterize NMOS and PMOS transistors at different technology nodes. It involves plotting the input and output characteristics to determine threshold voltage (Vth) and output resistance (Ro) for varying gate-source (Vgs) and drain-source (Vds) voltages. For NMOS, Vth is found to be 0.457V at Vds=0.1V and 0.455V at Vds=1.8V. For PMOS, Vth is -0.49V at Vds=-0.1V and -0.65V at Vds=-1.8V. Ro is also calculated and is found to be 16.1kΩ for N

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Girish Verma
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38 views

Experiment-1: 1. For Threshold Voltage

The document describes experiments to characterize NMOS and PMOS transistors at different technology nodes. It involves plotting the input and output characteristics to determine threshold voltage (Vth) and output resistance (Ro) for varying gate-source (Vgs) and drain-source (Vds) voltages. For NMOS, Vth is found to be 0.457V at Vds=0.1V and 0.455V at Vds=1.8V. For PMOS, Vth is -0.49V at Vds=-0.1V and -0.65V at Vds=-1.8V. Ro is also calculated and is found to be 16.1kΩ for N

Uploaded by

Girish Verma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT-1

Aim: PLOT INPUT AND OUTPUT CHARACTERISTIC OF NMOS AND


PMOS FOR DIFFERENT TECHNOLOGY NODE.
1. FOR THRESHOLD VOLTAGE:

(i)For NMOS

(a) AT Vds = 0.1

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girishkumar\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 1.8 0.01
.inc "C:\Users\Girishkumar\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth= 0.457V

(b) At Vds= 1.8 V

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\Rishabh\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc
M1 N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 1.8 0.01
.inc "C:\Users\Rishabh\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth = 0.455V

(ii)FOR PMOS
(a) VDS = -0.1
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 Vds
N002 0 -0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\Girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Vth= -0.49V

(b)VDS= -1.8

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 Vds
N002 0 -1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
VTH = -0.65V

2. FOR OUTPUT RESISTANCE:


(i) FOR NMOS
(a) VGS = 0.1V
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0 0.1
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds 0.0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
RO cannot find out as device is in cutoff region.

(b) VGS = 1.8V

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\NMOS\Vgs1\Draft1.asc M1
N002 N001 0 0 NMOS l=180n w=1u
Vgs N001 0 1.8
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds 0.0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro =16.1K

(ii)FOR PMOS
(a)Vgs = -0.1

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 0 PMOS l=180n w=1u
Vgs N001 0 -1.0
Vds N002 0 -0.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro cannot be find out as device is in cut off region.

(b)Vgs = -1.8

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Ro\PMOS\VGS=-0.1\Draft2.asc M1
N002 N001 0 N003 PMOS l=180n w=1u
Vgs N001 0 -1.8
Vds N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vds -1.8 0.0 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

RESULT:
Ro =20K

3. Calculation of sub threshold:


(i) FOR NMOS
For Vds=1.8V
SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Vth\NMOS\Vds=1.8\Draft1.asc M1
N002 N001 0 N003 NMOS l=180n w=1u
Vgs N001 0
Vds N002 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0 1.8 0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end
.end

GRAPH:

ResultSub threshold=53.5mv/decade

(ii)For PMOS
(a)Vds=
-1.8v

SCHEMATIC DIAGRAM:

NETLIST:
* C:\Users\girish\Desktop\DIC Lab\EXP 1\Vth\PMOS\1.8\Draft1.asc Vgs
N001 0
Vds N002 0 -1.8
M1 N002 N001 0 N003 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.dc Vgs 0.0 -1.8 -0.01
.inc "C:\Users\girish\Desktop\180nm_bulk.txt"
.backanno
.end

GRAPH:

Result : Subthresold = 54.44 mv/decade

4. Drain Induced Barrier Lowering

DIBLnmos=Vth/Vds=0.001
DIBLpmos=Vth/Vds=0.094

GIRISH KUMAR

BT14ECE032

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