2014.09.23.

DIGITAL TECHNICS
Dr. Blint Pdr
buda University,
Microelectronics and Technology Institute
3. LECTURE: IMPLEMENTATION OF
COMBINATIONAL LOGIC

1st (Autumn) term 2014/2015

3. LECTURE

1. Implementation of combinational logic

2. Multiple output logic networks with examples
3. AND-OR-XOR networks with examples

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SYNTHESIS USING LOGIC GATES

The traditional process of logic synthesis is based on the
application of logic gates.
Its more modern variant makes use of programmable logic
devices too.
However in many case it is more advantageous to use a
logic synthesis procedure based on the application of logic
functional blocks.

IMPLEMENTING COMBINATIONAL LOGIC

The different steps involved in the design of a combinational
logic circuit are as follows:

1. Statement of the problem.

2. Identification of input and output variables.
3. Expressing the relationship between the input and output
variables.
4. Construction of a truth table to meet inputoutput
requirements.
5. Writing Boolean expressions for various output variables
in terms of input variables.
6. Minimization of Boolean expressions.
7. Implementation of minimized Boolean expressions.

2014.09.23.

IMPLEMENTING COMBINATIONAL LOGIC

These different steps are self-explanatory. One or two points,
however, are worth mentioning here.

There are various simplification techniques available for

minimizing Boolean expressions, which have been discussed
in the previously. These include the use of theorems and
identities, Karnaugh mapping, the QuineMcCluskey
tabulation method and so on. Also, there are various possible
minimized forms of Boolean expressions.
The following guidelines should be followed while choosing
the preferred form for hardware implementation:

IMPLEMENTING COMBINATIONAL
LOGIC
1. The implementation should have the minimum number
of gates, with the gates used having the minimum
number of inputs.
2. There should be a minimum number of interconnections,
and the propagation time should be the shortest.
3. Limitation on the driving capability of the gates should
not be ignored.
It is difficult to generalize as to what constitutes an
acceptable simplified Boolean expression. The importance of
each of the above-mentioned aspects is governed by the
nature of application.

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Problem statement

Truth Table

Sum of minterms
form

Product of maxterms
form

Minterm table

Maxterm table
Minimized
SoP form

Minimized
PoS form

Elimination of hazards

Impementation:
NAND gates

Elimination of hazards

Implementation:
NOT-AND-OR

Implementation:
NOR gates

Flow diagram of logic synthesis procedure using gates

IMPLEMENTATION OPTIONS
Ready-made catalog-order (modular) devices (gates,
functional blocks, etc.)
Custom-design devices
Gate-array devices
Programmable logic devices (PLD), e.g. programmable logic
array (PLA), programmable array logic (PAL), etc.
Table look-up (ROM)
Microcomputer

2014.09.23.

USING READY MADE (MODULAR)

ELEMENTS
Ready-made catalog-order devices usually are available as simple
gates, or functional bocks. The manufacturers have attempted to
provide a repertoire of logic networks that will find common usage and
generality. Some examples are arrays of individual gates (typically four
to six), decoders, multiplexers, etc., further on arrays of flip-flops,
simple counters, arithmetic adders (e.g. 4-bit), and multipliers of
forming the product of two 4-bit numbers in a single step (i.e. a
combinational multiplier).
The number of gates or logic elements realized on individual devices
ranges from a few to several hundred. Clearly a design that can use the
devices (modules) with larger gate count is likely to be more compact
and more economical.

CUSTOM-DESIGNED DEVICES
A second common realization of logic gates is customdesigned devices. Two factors which make this practical
are computer-aided-design (CAD) tools and libraries of
sub-networks that can be used as building blocks.
Custom design of a logic network implies the generation
of highly complicated artwork patterns, called masks, for
use in photolithography to produce the integrated circuit
(IC) networks. The availability of a library of sub-networks
for which the artwork has already been generated
reduces the additional artwork required to interconnection
patterns among these library elements to set up the
desires logic network.

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GATE-ARRAY DEVICES
A third-option is to use gate-array devices. The vendor manufactures and
offers devices comprising a two-dimensional array of logic cells. Each cell
is equivalent to one or more logic gates. The final layers of metallization
that determine the actual function of each cell and interconnect the cells to
form a specific network are deferred until the customer orders such a
device. This procedure uses the advantage of mass production for the
majority of processing steps necessary to manufacture a device, including
most of the artwork. Since the interconnecting metallization layers are a
relatively small and simple part of the total device fabrication, the
customization cost and time can be reduced significantly by this method
relatively to a totally custom fabrication.
The sacrifice in this approach is that the packing density of the twodimensional array will tend to be less than a custom-designed layout,
since routing channels must allow for reasonably general interconnection
patterns.

PROGRAMABLE LOGIC DEVICES

A fourth option in realizing logic functions is programmable
logic devices (PLDs), more specifically programmable logic
arrays (PLAs) and programmable array logic (PAL). The
manufactured device has the potential or realizing any of a
large number of different sets of logic functions. E.g. in a
certain tape of device, each of the 16 device-input signals is an
input to each of 48 AND gates; the 48 AND outputs are input
signals 8 OR gates that generate the device outputs.
Appropriate activation of input connections to AND gates and
the connections between AND and OR gates enables
implementation of a wide variation of functions.
Certain types of PLDs contain flip-flops too, allowing the
realization of sequential logic too.

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PROGRAMMABLE ARRAY LOGIC

16-input, 8-otput PAL (P16H8)

PROGRAMMABLE SEQUENTIAL ARRAY

PSA = PLA + registers (flip-flops)

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TABLE LOOK-UP (ROM)

A fifth embodiment of logic network functions involves the use of table
look-up. A logic network has several logic input signals and one or more
logic/binary outputs. The connection between the inputs and outputs need
not to be realized by AND-OR type logic elements at all; instead, the
collection of input signals can be grouped arbitrarily as address digits to a
memory device. In response to any particular combination of inputs the
memory device location which is addressed becomes the output.
For example a logic network involving 10 inputs and 8 output signals could
be realized with a single memory device that holds 1024 memory cells,
with 8 bits stored in each cells (1kx8).
In its simplest form the memory device used is usually read-only, ROM or
PROM. Typically, this approach may lead to slower operation than the use
of logic circuits, but in some cases can lead to very significant economies.

ROM APPLICATIONS: CODE

CONVERSIONS
One important application of ROMs in combinational logic is
the code conversion.
n-bit code m-bit code necessary memory capacity:
m x 2n.
8-bit binary code 8-bit Gray code: 256x8 ROM.
13-bit binary code 4 tetrad BCD code:
Two 8-kbyte capacity EPROM, 1s, and 10s, and 100s and
1000s respectively, (13 bit: 0-8191).
16

2014.09.23.

CODE CONVERSION USING ROM

Binary inputs

B0 B12

A0

A12

D0
...

D7

A0

A12

D0
...

D7

BCD outputs

1s and 10s

100s and 1000s

13-bit binary code to 4 tetrad BCD code converter

ROM BASED LOGIC: MULTIPLIER

X Y
0*0
0*1
0*2
0*3
1*1
1*2
1*3
2*0
2*1
2*2
2*3
3*0
3*1
3*2
3*3

00
00
00
00
01
01
01
10
10
10
10
11
11
11
11

00
01
10
11
01
10
11
00
01
10
11
00
01
10
11

Z
0000
0000
0000
0000
0001
0010
0011
0000
0010
0100
0110
0000
0011
0110
1001

X
Y

ROM
16x 4bit

Fast, simple, cheap,

Can generate any function
(look-up-table, LUT)
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8x8 BIT COMBINATIONAL MULTIPLIER

4x4 bit partial products are generated by four 256x8 bit ROMs

LUT BASED SYSTEM LOGIC BLOCK

In general, a logic block (CLB or LAB) consists of a few

logical cells (called ALM, LE, Slice etc). A typical cell
consists of a 4-input Lookup table (LUT), a Full adder (FA)
and a D-type flip-flop. The LUT are in this figure split into
two 3-input LUTs. In normal mode those are combined into
a 4-input LUT through the left mux.

10

2014.09.23.

MICROCOMPURTER,
MICROCONTROLLER
Finally the last form of logic network embodiment considered here is
the generic microcomputer. In short a microcomputer is a single (onechip) device that includes a ROM to hold a program, a processor
capable of reading and executing that program, and a small R/W
memory for scratch working space. Just as a memory device discussed
before provides an efficient realization of a combinational network, an
equivalent of a highly complex sequential network can be had with a
microcomputer, as evidence e.g. by electronic games.
Two important advantage of this approach that little or no custom
fabrication is required, and the programmability permits utilization of
complicated and modifiable equivalent networks.
As with table look-up, the principal disadvantage of this approach is
that the speed of operation may be slower than if an actual network of
high-seed logic circuits were used.

MINIMIZATION AND IMPLEMENTATION

OF MULTIPLE OUTPUT NETWORKS
C
Fa = 4(5,12,13)

b
a,b

Fb = 4(3,5,7)

b
B

Elementary implementation:
four 3-input AND gates and
two 2-input OR gates

A
Cost function (pin count):
4x3 + 2x2 = 16
D

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2014.09.23.

MINIMIZATION AN IMPLEMENTATION OF
MULTIPLE OUTPUT NETWORKS
C
Fa = 4(5,12,13)
b
a,b

Fb = 4(3,5,7)

b
B

23

MINIMIZATION AN IMPLEMENTATION OF
MULTIPLE OUTPUT NETWORKS
A

_
C

B
&

_
_
A B C D

_
A C

&

&

Fa

Fb

Pin count: 14

24

12

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EXAMPLE: MINIMIZATION OF THREE

OUTPUT LOGIC FUNCTION
Determine the simplest conceptual two-level AND-OR
logic diagram of the three output logic network:
Fa = 4(0,1,5,6,7,13)
Fb = 4(0,1,5,10-15)
Fc = 4(0,1,8-11,14,15)
The common prime implicants of Fa and Fb are the prime
implicants of the product function Fab = FaFb, etc.
25

COMMON (PRIME) IMPLICANTS

Product functions (pairs):
Fa = 4(0,1,5,6,7,13)
Fb = 4(0,1,5,10-15)
Fc = 4(0,1,8-11,14,15)
Fab = FaFb = 4(0,1,5,13) = m(0,1) + m(5,13)

Fbc = FbFc = 4(0,1,10,11,14,15) = (0,1) + m(10,11,14,15)

Fca = FcFa = 4(0,1) = m(0,1)
26

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2014.09.23.

RESULT OF MINIMIZATION

Principle: the common prime implicants occurring in more

outputs are implemented only once.
Fa,Fb,Fc:
/A /B /C
m(0,1)
Fa,Fb:
B /C D
m(5,13)
Fa,Fb:
AC
m(10,11,14,15)

27

ANOTHER EXAMPLE: BCD TO

7-SEGMENT DISPLAY CONTROLLER
Understanding the problem
Input is a 4 bit BCD digit (A, B, C, D)
Output is the control signals for the display (7 outputs
C0 C6)
c0
c1
c5
Block diagram
c4

c6

c2

c3
c0 c1 c2 c3 c4 c5 c6

BCD to 7segment
control signal
decoder
A B C D

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2014.09.23.

FORMALIZE THE PROBLEM

A
0
0
0
0
0
0
0
0
1
1
1
1

Truth table
Show don't cares
Choose implementation
target
If ROM, we are done
Don't cares imply PAL/PLA
may be attractive
Follow implementation
procedure
Minimization using K-maps

B
0
0
0
0
1
1
1
1
0
0
0
1

C
0
0
1
1
0
0
1
1
0
0
1

D
0
1
0
1
0
1
0
1
0
1

C0
1
0
1
1
0
1
1
1
1
1

C1
1
1
1
1
1
0
0
1
1
1

C2
1
1
0
1
1
1
1
1
1
1

C3
1
0
1
1
0
1
1
0
1
0

C4
1
0
1
0
0
0
1
0
1
0

C5
1
0
0
0
1
1
1
0
1
1

C6
0
0
1
1
1
1
1
0
1
1

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IMPLEMENTATION AS MINIMIZED
SUM-OF-PRODUCTS (SOP)
15 unique product terms when minimized individually
A

C 1
1

C 0
1

C 1
1

C 1
0

C 1
1

1
B

C 0
0

C 1
1

C0
C1
C2
C3
C4
C5
C6

= A + B D + C + B' D'
= C' D' + C D + B'
= B + C' + D
= B' D' + C D' + B C' D + B' C
= B' D' + C D'
= A + C' D' + B D' + B C'
= A + C D' + B C' + B' C
30

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IMPLEMENTATION AS MINIMIZED SOP

(CONTD)
Can do better
9 unique product terms (instead of 15)
Share terms among outputs
Each output not necessarily in minimized form
A

C2

C 1
0

C2
D

C0
C1
C2
C3
C4
C5
C6

=
=
=
=
=
=
=

C 1
0

A + B D + C + B' D'
C' D' + C D + B'
B + C' + D
B' D' + C D' + B C' D + B' C
B' D' + C D'
A + C' D' + B D' + B C'
A + C D' + B C' + B' C

C0
C1
C2
C3
C4
C5
C6

=
=
=
=
=
=
=

B C' D + C D + B' D' + B C D' + A

B' D + C' D' + C D + B' D'
B' D + B C' D + C' D' + C D + B C D'
B C' D + B' D + B' D' + B C D'
B' D' + B C D'
B C' D + C' D' + A + B C D'
B' C + B C' + B C D' + A
31

PLA IMPLEMENTATION
A B C D
BC'
B'C
B'D
BC'D
C'D'
CD
B'D'
A
BCD'

C0 C1 C2 C3 C4 C5 C6 C7
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2014.09.23.

BCD-TO-7-SEGMENT DISPLAY DECODER

a real MSI circuit

54/74LS47
44 gates

OUTPUT: C0
C

1
1

1
B

1
A
1

1
D

34

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2014.09.23.

EXAMPLE FOR EXCLUSIVE-OR LOGIC:

BCD-TO-GLIXON CODE CONVERTER
The Glixon code is a one-step BCD code (the Hamming
distance is 1). The code words from 0 to 9 are
0000(0)
0111(5)

0001(1)
0101(6)

0011(2)
0100(7)

Normal BCD code:

Glixon code:

0010(3)
1100(8)

0110(4)
1000(9)

ABCD (A is the MSB)

E3, E2, E1, E0 (E3 is the MSB).

E3 = 4(8,9)X(10-15)
E2 = 4(4-8)X(10-15)
E1 = 4(2-5)X(10-15)
E0 = 4(1,2,5,6)X(10-15)
35

BCD-TO-GLIXON CODE CONVERSION

C

Design a (normal)
BCD/Glixon kd converter.
The illegal code word
cannot be present at the
inputs.
B

8
A
9
D

36

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2014.09.23.

MINIMIZED TWO LEVEL AND-OR CIRCUIT

E3 = A
&

_
E2 = B + A D
_ _
E1 = B C + B C

&
1
&

_ __
E0 = C D + A C D

&
1

Pin count 18
Gate count 8

&
37

AND-OR-EXCLUSIVE-OR LOGIC
IMPLEMENTATION
Using XOR gates in implementing (partially) symmetric
logic functions make possible to obtain more economical
solutions than using standard optimized two-level ANDOR or OR-AND circuits.
Here this approach can be applied to E1 and E0.
Full or partial symmetry is evident on the Karnaugh map
by noting the chessboard patterns.

38

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AND-OR-XOR LOGIC: E1
C
1

_
_
E1 = B C + B C

(three gates)
1

1
B

E1 = B C
One gate instead of
three!

39

AND-OR-XOR LOGIC: E0
C

_ __
E0 = C D + A C D

1
B

(three gates)
_
E0 = A (C D)
Two gates instead of
three!

40

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2014.09.23.

AND-OR-XOR LOGIC IMPLEMENTATION

E3 = A
&

_
E2 = B + A D
E1 = B C

=1

_
E0 = A (C D)

=1

&

Pin count 11
Gate count 5

Additional benefit: 2 inverters instead of 4 at the input!

41

EXAMPLE: BINARY-TO-GRAY CODE

CONVERTER USING PLA
Consider a 4-bit example:
Binary code:
Gray code:

b3 b2 b1 b0
g3 g2 g1 g0

The code conversion algorithm:

g3 = b3
__
__
g2 = b3 b2 = b3 b2 + b3 b2
__
__
g1 = b2 b1 = b2 b1 + b2 b1
__
__
g0 = b1 b0 = b1 b0 + b1 b0

42

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FIRST STEP: IMPLEMENTATION OF G0

B3 B2 B1 B0

__
__
g0 = b1 b0 + b1 b0

G3 G2 G1 G0

43

BINARY-TO-GRAY CODE CONVERSION

B3 B2 B1 B0

g3 = b3
__
__
g2 = b3 b2 + b3 b2

(1)
(0)

__
__
g1= b2 b1 + b2 b1
__
__
g0 = b1 b0 + b1 b0

G3 G2 G1 G0

Extension to more bits is trivial!

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