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Experiment-1 Aim: Introduction To Xilinx ISE 9.2i: Starting With A New Project

The document provides instructions for creating a new project called "fadd" in Xilinx ISE 9.2i using VHDL. It describes adding a source file called "fadd.vhd" to the project and synthesizing it. It then explains how to create a test bench file called "fadd_tb.vhd" to simulate and check the outputs of the design.

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Saurabh Anand
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103 views4 pages

Experiment-1 Aim: Introduction To Xilinx ISE 9.2i: Starting With A New Project

The document provides instructions for creating a new project called "fadd" in Xilinx ISE 9.2i using VHDL. It describes adding a source file called "fadd.vhd" to the project and synthesizing it. It then explains how to create a test bench file called "fadd_tb.vhd" to simulate and check the outputs of the design.

Uploaded by

Saurabh Anand
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment-1

Aim: Introduction to Xilinx ISE 9.2i


Starting with a New Project
First start the project manager with the following;
Start => Programs => XiLinx ISE 9.2i => Project Manager
If the Tip-of-the-Day window pops open, click its OK button to close it. We will be referring to the
Xilinx-ISE window as the Project Navigator window. In this window, use the mouse to select:
File => New Project...
The trailing dots indicates that in selecting the item, a dialog box will appear. In the correponding fields
enter the the following information. If you are working at home, replace the Z: with C:

Project Name: fadd

Project Location: Z:\ee534\proj\fadd

Design Flow: HDL

In the next window select the following, then click Next.

Product Category: General Purpose

Family: Spartan2

Device: XC2S200

Package: PQ208

Speed Grade: -6

Synthesis Tool: XST (VHDL/Verilog)

Preferred Language: VHDL

Enable Enhanced Design Summary: checked

Enable Message Filtering: not checked

Display Incremental Messages: not checked

If you know the names of your new source files, you can enter them now. In a few moments you will use
a different method to make a new VHDL source file. Click Next.
The final window provides a summary of all your choices for the new project. Review the list and then
click Finish.

With the new project, either click the New Source Button below the title bar or select Project => New
Source.
In the pop-up window do the following:

Click to highlight VHDL Module in the type field

Enter the name fadd in the File name field

Make sure the Add to Project box is checked

Click the Next button. In the next pop-up window, change the Architecture Name field to 'DataFlow',
enter the port names, and set the signal directions. The window should look like the following:

Adder Ports
Click Next. . Enter your Require Input and output ports. Click the Finish button. Review the VHDL
listing given above. Complete the architecture declaration. Your code should look similar to
the fadd.vhd file above. Select File=>Save.
Synthesizing the Example
Look in the upper left pane of the Project Navigator Window. The file name fadd.vhd should appear as
being a source in the current project. If you don't see the file name, you can add it by clicking left to
select Project => Add Source. To remove a source file from your project, right click on the file name
and select Remove. The file is not deleted, but is simply removed from the current project. Go ahead
and remove, then add the file back to the project. The file is a VHDL Design File.
You will notice that the upper left pane has a choice as to what to consider the files for. The choice
'Synthesis/Implementation' should be displayed. When a file name in the upper left pane is selected, it

becomes highlighed. The use choice and type of file selected determines what choices you have in the
lower left Processes pane. In the upper left pane, click left to highlight and select the name fadd.vhd.
In the lower left pane, right click on the keyword Synthesize. In the pop-up window select the
entry Run to run the synthesis tool. The synthesis tool verifies the syntax of the VHDL code and
generates an intermediate form that we use to perform simulation. The intermediate form is used later to
implement the design.
Test Benches, Bencher, and Simulation
A test bench is analagous to a laboratory test bench, which has signal generators, and test gear. A test
bench is special VHDL file that describes what the input will be will be, as can also be used to check that
the corresponding outputs are correct.
In the Project Navigator Window, make the following selection by either clicking the New Source icon or
pointing the mouse and left clicking:
Project => New Source
In the New dialog box, click to highlight the Test Bench Waveform entry, enter fadd_tb into the File
Name field, verify that the Add to Project box is checked, and then click Next. Be carful to not use the
name fadd here, as that is the name of your VHDL source file. The Select dialog box associates the new
file with a VHDL entity to be tested. The entry fadd should already be highlighted. Click
the Nextbutton.
The next dialog box summarizes the data entered. Click Finish to start the HDL Bencher tool and open
the Initialize Timing dialog box.

Bencher input assigned


Select File=>Save and then close the Bencher window. In order to have Bencher produce a test bench
that checks output, it is necessary to somehow tell Bencher what the expected output values are.
Simulating the Example
In the upper-left pane of the project manager, change the Sources for: choice to 'Behavioral Simulation'.
Click left to select the fadd_tb file icon. In the lower left pane, click the '+' icon in front of the Xilinx ISE
Simulator toolbox icon. Right click on 'Simulate Behavioral Model' and select Run. You may have to

stretch to resize the simulation output window..

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