Design Rules
Design Rules
N- Well
r101
r102
r110
Minimum width
Between wells
Minimum well Area
r 101
N - Well
r 102
12
12
144 2
r201
r 201
P+ Diff
r 201
N+ Diff
N - Well
r202
r 202
P+ Diff
N - Well
r 202
N+ Diff
r203
r 203
P+ Diff
r 203
N - Well
N+ Diff
r204
P+ Diff
N - Well
r 204
N+ Diff
r210
r 210
P+ Diff
r 210
N+ Diff
N - Well
162
r301
Polysilicon Width
Polysilicon
r 301
P+ Diff
N - Well
Polysilicon
r 301
N+ Diff
r302
r 302
P+ Diff
N - Well
Polysilicon
r 302
N+ Diff
r307
r 307
P+ Diff
r 307
N - Well
Polysilicon
r 307
N+ Diff
r 307
r304
r 304
P+ Diff
N - Well
Polysilicon
r 304
N+ Diff
r307
r 307
r 307
P+ Diff
N - Well
Polysilicon
r 307
r 307
N+ Diff
r401
Contact width 2
Contact
r 401
Polysilicon Contact
Metal/Polysilicon Contact
r404
r 404
Polysilicon Contact
Metal/Polysilicon Contact
r 404
r405
Polysilicon Contact
Metal/Polysilicon Contact
r 405
r 405
r403
r 403
Polysilicon
P+ Diff
N - Well
r 403
Polysilicon
N+ Diff
r501
Metal 1
Metal 4
r 501
Metal 2
Metal 5
r 501
Metal 3
Metal 6
r510
Metal 1
Metal 2
r 510
r 510
r 510
r 510
Metal 3
Metal 4
Metal 5
Metal 6
r 510
r 510
Step 3: n+ Diffussion
Step 4: Polysilicon
Step 6: p+ Diffusion
Step 7: Polysilicon
Step 8: Contacts
Final Connections
pMOS Completed
Now Interconnection of pMOS and nMOS to
complete inverter
Connect Source of pMOS to VDD and Source of
nMOS to VSS.
Check DRC
Assign Source
Assign Signal (Clock) to Gate Terminal
Add Visible node at Output
Run Simulation
VTC Characteristics