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Course Basic Uvm Session1 Introduction To Uvm Tfitzpatrick

The document introduces the Universal Verification Methodology (UVM) which is a standard for verification test benches. It discusses that UVM uses constrained random stimulus generation and coverage-driven verification. It also describes key aspects of UVM like its layered approach using sequences, transactions, drivers and monitors.

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0% found this document useful (0 votes)

67 views12 pages

Course Basic Uvm Session1 Introduction To Uvm Tfitzpatrick

Uploaded by

kalyani

We take content rights seriously. If you suspect this is your content, claim it here.

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Download as PDF, TXT or read online on Scribd

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UVM Basics

Introduction to UVM
Tom Fitzpatrick
Verification Evangelist
[email protected] | www.verificationacademy.com

Sessions in this Course

Introduction to UVM

UVM "Hello World"

Connecting Env to DUT
Connecting Components
Introducing Transactions
Sequences and Tests
Monitors and Subscribers
Reporting

2013 Mentor Graphics Corporation, all rights reserved.

What is UVM?

The Universal Verification Methodology

Test benches for (System)Verilog / VHDL / SystemC designs
Accellera standard
SystemVerilog UVM Base Class Library (BCL)
Open source (Apache licence)
Near-backward compatible with OVM

2013 Mentor Graphics Corporation, all rights reserved.

UVM Highlights
Constrained random, coverage-driven verification
Configurable, flexible, test benches
Verification IP reuse

Separation of tests from test bench

Transaction-level communication (TLM)
Layered sequential stimulus
Standardized messaging
Register layer

2013 Mentor Graphics Corporation, all rights reserved.

Constrained Random Verification

Constrained random
stimulus
11001001
01001010
00001001
01110110
01100110
01001001
01001110

Find unexpected
bugs
Design
Under
Test

Automate stimulus
generation
2013 Mentor Graphics Corporation, all rights reserved.

Constrained Random Verification

Constrained random
stimulus

Checker

Does it work?
000010
11001001
010011
01001010
000010
00001001
Design
110010010100101000001001
110010010100101000001001100100
01110110
Under
001000
01100110
Test
110010
01001001
000011
01001110
Functional
Coverage
Constraints
Header

Payload

Checksum

Increase coverage

Are we done?

2013 Mentor Graphics Corporation, all rights reserved.

Test versus Testbench

Test1

Test2

Reusable
verification
environment

Test3

Tests define
differences

DUT

2013 Mentor Graphics Corporation, all rights reserved.

Layered Sequential Stimulus

Nested, layered or
virtual sequences

seq1

seq2

seq3

tx1

tx2

tx3

Constrained random
sequence of transactions

Drive transactions into DUT

tx1

Driver

DUT

The Big Picture

Test
Test

Configuration database
name = value
name = value
name = value

Configure environment
Virtual
sequence

Configure component

Reusable verification
environment
Scoreboard

Sequencer

Verification
component

Monitor

Driver

HTML Documentation

What You Need to Learn

Verification Planning and Management
Constrained Random Verification

UVM Base Class Library (BCL) & OOP & TLM

classes
SystemVerilog

UVM Basics

Introduction to UVM
Tom Fitzpatrick
Verification Evangelist
[email protected] | www.verificationacademy.com

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