2016

TM

UNITED STATES

conference
program
- and -

exhibition
guide

The Premier Conference for Design & Verification

February 29 - March 3, 2016 San Jose, California

Industrys Fastest*
Emulation System
*and fast e st
growing

table of
contents
General Chairs Welcome...............................4

Wednesday Agenda......................................25

General Information............................................6

Panel....................................................................26

Voting Instructions...............................................7

Sessions: 8 - 10...................................................26

Steering Committee.............................................8

Sponsored Luncheon........................................28

Technical Program Committee..........................9

Panel....................................................................29

Conference Sponsor..........................................10

Sessions: 11 - 13.................................................29

Accellera Technical Excellence Award.............10

Best Paper & Poster Award..............................30

Monday Agenda............................................12

Thursday Agenda..........................................32

Tutorial Overview...............................................13

Tutorials: 5 - 8.....................................................33

Tutorials: 1 - 2.....................................................14

Sponsored Luncheon........................................36

Sponsored Luncheon........................................16

Tutorials: 9 - 12...................................................37

Tutorials: 3 - 4.....................................................16
DVCon Expo....................................................40

ZeBu Server-3

Tuesday Agenda............................................18

Exhibitor Listing.................................................42

Sessions: 1 - 3.....................................................19

Exhibitor Floorplan............................................43

Session 4: Poster Session..................................20

Exhibiting Companies........................................44

Sponsored Luncheon........................................22

First Time Exhibitors..........................................48

Keynote Address................................................23

synopsys.com/zebu

Sessions: 5 - 7.....................................................23

welcome
to dvcon
Yatin Trivedi

General Chair - Synopsys, Inc.

DVCon U.S. 2016: A Community Event

Of course, the name changes were indicative of

the changing needs of the user community. In
the late 1980s and early 1990s, the two HDLs
(among several others) were vying to establish
their identity by forming a community around
the language. Hence the name of the respective
HDLs in the conference was important. By the
late 1990s, the two underlying HDLs (Verilog and
VHDL) were widely in use in the industry and
methodology was becoming a larger focus for
the user community. The user community drove
the two separate conferences to merge into a
single event. In due time, other languages such as
SystemVerilog and SystemC became more widely
used and the focus changed from HDLs to design
flows and verification methodologies. In 2014,
DVCon took yet another step forward by spawning
DVCon Europe and DVCon India. With two years of
successful conferences in India and Europe under
the DVCon umbrella, the three DVCons are serving
a much larger global community.

DVCon U.S. is truly a community event an event

organized by and for the design and verification
community!
First and foremost, thanks to the Accellera Systems
Initiative for its continued sponsorship of DVCon
in the U.S. and abroad. Through DVCon, Accellera
continues to build and serve a very strong design
and verification community worldwide.
DVCon U.S. is also only possible because of the
countless hours spent by volunteers over the past
eight months to organize this years conference.
These volunteers include Steering Committee
members, Program Committee Reviewers,
technical paper and poster authors, exhibitors,
sponsors, and perhaps the most important, the
MP Associates team. Altogether, the efforts and
commitment of more than 100 people bring us to
the doorstep of this years event.
As you plan your attendance at DVCon U.S.,
I want you to think about how the conference has
evolved over the years to serve the community
better. Way back in 1988 a small gathering was
held under the banner of VHDL International
Users Forum (VIUF). A few years later, there was
a more formal International Verilog Conference
(IVC). By 1997, the two were co-locating, and
formally merged in 1999 to be called International
HDL Conference (HDLCon). After the formation
of Accellera in 2001, the evolution continued and
the conference was renamed once again in 2003
to the Design and Verification Conference and
Exhibition, or simply DVCon.

No matter how long you have known DVCon, one

thing has remained constant. The conference
has continued to act as the venue for the user
community to network, raise awareness of
problems and challenges faced in their daily grind,
and sought innovative tools and solutions from
peers and vendors. Now in its 28th year, DVCon
U.S. 2016 is no different. It still offers you the same
great opportunity to attend a highly informative
and educational event.

Panel discussions: This years panel discussion

topics include Emulation and ESL. As always, both
panels will provide lively and interactive debate
on current issues.

Here are some of the highlights:

Keynote: Dr. Wally Rhines, CEO and Chairman
of the Board at Mentor Graphics will deliver this
years keynote, Design Verification Challenges:
Past, Present and Future. As we have come to
expect from him in the past, he will explain what
the future holds for the industry based on all of
the trend data he gathers throughout the year
from his customers, market analysts and the
research from EDAC.

Exhibits: When the orderly, formal technical

sessions stop, the vibrant exhibit floor brings
out all the fun, food and friends showcasing
the latest EDA tools, design and verification IP
and services. With 40 exhibitors, you are sure to
strike conversations that help solve some of your
current challenges or plant an intriguing new
idea. It surely is a networking event for all.

Tutorials: One of the biggest attractions at

DVCon has been the tutorials offered by the
experts who develop Accellera standards.
On Monday, Accellera Day, we will have four
tutorials covering UVM, SystemVerilog Assertions,
SystemVerilog-AMS and SystemC Synthesis.
On Thursday, there will be eight tutorials covering
a wide variety of verification methodologies
and techniques.

This years busy technical program promises to

offer several topics of interest to all attendees.
However, there are many breaks and socializing
events throughout the four days for you to
network with your peers and learn from
each other.
With everyones active participation all these years,
DVCon has clearly achieved the status of a true
community event for the industry. Personally, I
have learned a lot from many of you. It has been a
real privilege to serve as the General Chair for this
year and last.

Technical papers and posters: For the

beginners as well as experienced engineers, the
opportunity to hear the latest developments
in design and verification techniques by the
industry practitioners is invaluable. The formal
paper presentations and informal conversations
during poster sessions will cover a range of topic
including UVM, UPF (Low Power), SystemVerilog,
SystemC, AMS, Emulation, and Formal
Verification techniques. Remember to vote for
the Best paper and Best Poster awards.
These are Peoples Choice awards and the
authors very much appreciate the recognition
from their peers.

So, welcome to DVCon U.S. 2016! Lets enjoy the

latest edition of DVCon and learn together.
Thank you,

General Chair, DVCon U.S. 2016

conference
details
Registration Hours

Best Paper & Poster Voting

Location: Bayshore Foyer

Monday, February 29........................... 7:30am to 7:00pm

Sponsored by:

Tuesday, March 1.................................. 7:30am to 6:00pm

Wednesday, March 2............................ 7:30am to 6:00pm
Thursday, March 3................................ 7:30am to 2:00pm

Wednesday, March 2 | Location: Bayshore Ballroom | 5:00pm

Location: Bayshore Ballroom

6
01

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All Access, Conference Only and One-Day only registrants are entitled to vote for
the DVCon Best Paper and Poster awards. The attendees are the judges!
Enjoy the convenience of voting from your PC and mobile device:
1. Go to http://vote.dvcon.org
2. Vote on the papers and posters you have attended

Awards Presentation

Expo Hours
CON
2
DV

Sponsored by:

Join us on the Exhibit Floor for the announcement of the 2016 award recipients!

Monday, February 29.......... 5:00pm to 7:00pm

Tuesday, March 1.................................. 2:30pm to 6:00pm

Expo Floorplan

Wednesday, March 2............................ 2:30pm to 6:00pm

Parking Instructions
Day/overnight self parking is $10.00 per day/per car with no in/out privileges.
Local attendees are to scan their parking ticket at the designated DVCon validation area (Bayshore Foyer).
The scanner will beep 3 times to notify the attendee has validated their tickets at the group discounted rate.
There are two pay stations inside the hotel. One is located near the convention entrance (Bayshore Foyer) side and
this machine accepts both cash and credit card. The second pay station is located near the guest elevators near the
South Parking Lot. This machine accepts only cash.

DVCon Tutorials & Proceedings Distribution

DVCon Conference Papers and Tutorial presenter slides will be delivered electronically online via a username
and password.
To access: http://proceedings.dvcon.org
Username = Email address
Password = Registration ID (on your badge)
Please refer to your registration receipt to access the files you are eligible to view.

Wireless Information

Enjoy free Wi-Fi at DVCon! Connect to the Conference Wi-Fi via:

Wi-Fi SSID: DVCon2016
No Password Required

Social Media At DVCon

Follow @DVCon on Twitter and get hourly conference announcements.

Also, tweet #DVCon about your experience and highlights at the conference!
Dont miss DVCon on Facebook at facebook.com/DVCon.

steering
committee

technical program
committee

General Chair

Vice Chair

Program Chair

Poster Chair

 90 East Middlefield Rd.

6
Mountain View, CA 94043
650-584-5000
[email protected]

 005 SW Boeckman Rd.

8
Wilsonville, OR 97070
503-685-0893
[email protected]

1230 Midas Way, Ste. 200

Sunnyvale, CA 94085
508-292-1681
[email protected]

690 East Middlefield Rd.

Mountain View, CA 94043
650-584-5000
[email protected]

Tutorial Co-Chair

Tutorial Co-Chair

270 Billerica Rd.

Chelmsford, MA 01824
978-262-6389
[email protected]

18 Whistle Post Ln.

Groton, MA 01450
978-448-8797
[email protected]

Past Chair

Program Chair

2655 Seely Ave.

San Jose, CA 95134
408-944-7260
[email protected]

1230 Midas Way, Ste. 200

Sunnyvale, CA 94085
508-292-1681
[email protected]

Dennis Brophy
Mentor Graphics Corp.

Yatin Trivedi
Synopsys, Inc.

Tom Fitzpatrick
Mentor Graphics Corp.

Adam Sherer
Cadence Design Systems, Inc.

Ambar Sarkar, Ph.D.

eInfochips

Stanley J. Krolikoski, Ph.D.

Cadence Design Systems, Inc.

Poster Chair

Panel Chair

690 East Middlefield Rd.

Mountain View, CA 94043
650-584-5000
[email protected]

609 Castle Ridge Rd., Ste. 210

Austin, TX 78746
512-537-3136, ext. 7101
[email protected]

Accellera Representative
& Finance Chair

Publicity/Marketing Chair

Vanessa Cooper
Verilab, Inc.

Shankar Hemmady
Synopsys, Inc.

Ambar Sarkar, Ph.D.

eInfochips

Shankar Hemmady
Synopsys, Inc.

Mark Azadpour
Western Digital Corp.

Manish Gajjar
light

Karen Pieper
Microsemi Corp.

Amit Baranwal
Microsoft Corp.

Ning Guo
Advanced Micro Devices, Inc.

Mitchell Poplingher
Microsemi Corp.

Kamel Belhous
Teradyne, Inc.

Kaiming Ho
Independent

Logie Ramachandran
VeriKwest Systems Inc.

Dan Benua
Synopsys, Inc.

Phu Huynh
Cadence Design Systems

Dave Rich
Mentor Graphics Corp.

Shalom Bresticker
Intel Corp.

Tor Jeremiassen
Texas Instruments, Inc.

Imtiyaz Ron
Broadcom Corp.

Clifford Cummings
Sunburst Design, Inc.

Neyaz Khan
Maxim Integrated, Inc.

Sean Safarpour
Synopsys, Inc.

Stephen DOnofrio
Paradigm Works

Kelly Larson
Paradigm Works, Inc.

Erik Seligman
Intel Corp.

Charles Dawson
Cadence Design Systems

Kaowen Liu
MediaTek, Inc.

Stuart Sutherland
Sutherland HDL, Inc.

Joanne DeGroat
Ohio State University

Paul Marriott
Verilab

Robert Troy
ON Semiconductor

John Dickol
Samsung Electronics Co., Ltd.

Don Mills
Microchip Technology, Inc.

Greg Tumbush
Tumbush Enterprises LLC

Harry Foster
Mentor Graphics Corp.

Nagi Naganathan
Avago Technologies

Srinivasan Venkataramanan
CVC Pvt., Ltd.

Barbara Benjamin
HighPointe Communications

Lynn Bannister-Garibaldi
Accellera Systems Initiative

14359 SE Donatello Loop

Happy Valley, OR 97086
503-209-2323
[email protected]

8698 Elk Grove Blvd. Ste 1, #114

Elk Grove, CA 95624
916-670-1056
[email protected]

Conference Manager
Kathy Embler, CMP
MP Associates, Inc.

1721 Boxelder St., Ste. 107

Louisville, CO 80027
303-530-4562
[email protected]

conference
sponsorS
About Accellera Systems Initiative
Accellera Systems Initiative is an
independent, not-for profit organization
dedicated to create, support, promote, and
advance system-level design, modeling,
and verification standards for use by the
worldwide electronics industry. We are composed of a broad range
of members that fully support the work of our technical committee
to develop technology standards that are balanced, open, and
benefit the worldwide electronics industry. Leading companies
and semiconductor manufacturers around the world are using
our electronic design automation (EDA) and intellectual property
(IP) standards in a wide range of projects in numerous application
areas to develop consumer, mobile, wireless, automotive, and
other smart electronic devices. Through an ongoing partnership
with the IEEE, standards and technical implementations developed
by Accellera Systems Initiative are contributed to the IEEE for formal
standardization and ongoing governance.

Collaborate with our community of companies, individuals,

and organizations to deliver standards that lower the cost of
designing commercial IC and EDA products and embedded
system solutions, as well as increase the productivity of designers
worldwide.

TM

event
sponsors
Thank you to our Thursday Tutorial Sponsors

Encourage availability and adoption of next-generation EDA and

IP standards that encompass system-level, RT-level, and gate-level
design flows.
Collaborate with the electronic design community to deliver
standards that increase designer productivity and lower the cost
of product development.
Provide mechanisms that enable the continued growth of the
Accellera Systems Initiative user community including SystemC,
Universal Verification Methodology (UVM), and IP-XACT.
Standardize technical implementations developed by Accellera
Systems Initiative through the IEEE.

Our Mission
At Accellera our mission is to provide a platform in which the
electronics industry can collaborate to innovate and deliver global
standards that improve design and verification productivity for
electronics products.

Membership
Accellera members directly influence development of the most
important and widely used standards in electronic design.
Member companies protect and leverage their investment in
design languages through their funding of a proven, effective
and responsible organization. In addition, our members have a
higher level of visibility in the EDA industry as active participants in
Accellera-sponsored activities and as contributors to its decisions,
which impact the EDA industry. For a full list of technical activities
that are supported by Accellera, and for information on how to join
us, please visit our website at www.accellera.org.

The purposes of the organization include:

P
 rovide design and verification standards required by systems,
semiconductor, IP, and design tool companies to enhance a frontend design automation process.

Thank you to our Luncheon Sponsors

Accellera Systems Initiative Technical Excellence Award

Any member of an Accellera Working Group is eligible for the award.
Candidates can be nominated by Working Group chairs and are
endorsed and selected by participants of the Accellera Technical
Excellence Award Committee, which is a subcommittee of the
Technical Committee.

Accellera wishes to recognize the outstanding achievements of its

Working Group members by selecting outstanding contributors to
our standards development process as recipients of the Accellera
Systems Initiative Technical Excellence Award.
This annual award recognizes major contributions to the
development of Accellera standards. Examples of such
contributions may include leadership in standardization of new
technologies, assuring achievement of standards development
goals, and identifying opportunities to better serve the needs of the
community through standards.

TM

Past Recipients:

2015: Justin Refice

2014: Andrew Goodrich
2013: Janick Bergeron
2012: John Aynsley
For more information about Accellera awards
programs and to find out how to submit a nomination,
visit accellera.org/about/awards.

Sponsored by:

Accellera Global Sponsors:

TM

10

11

mondays
agenda
8:00am 11:00am

tutorial
overview
Monday, February 29

Coffee Break

Tutorial 1: Preparing for IEEE UVM Plus UVM Tips and Tricks..........................................14

Room: Gateway Foyer

Tutorial 2: SVA Advanced Topics: SVAUnit and Assertions for Formal............................15

MON DAY, F E B R UARY 29

12:00pm 1:30pm

2:00pm 5:00pm

Preparing for IEEE UVM Plus UVM

Tips and Tricks
Room: Oak

Tutorial 3: Cut Your Design Time in Half with Higher Abstraction...................................16

Tutorial 2

SVA Advanced Topics: SVAUnit and

Assertions for Formal
Room: Fir

Tutorial 4: SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling..............16

Thursday, March 3
Tutorial 5: Advanced Validation and Functional Verification
Techniques for Complex Low Power System-on-Chips...................................33

Sponsored Luncheon

Sponsored by:

Monday Accellera Luncheon

Room: Pine/Cedar

TM

Tutorial 3

Cut Your Design Time in Half with

Higher Abstraction
Room: Oak

Tutorial 4

SystemVerilog-AMS: The Future of

Analog/Mixed-Signal Modeling
Room: Fir

Tutorial 6: Developing Innovative Verification and Debug

Methodologies Using Synopsys VC Apps..........................................................34
Tutorial 7: Methodology for Addressing Mixed-Signal SoC
Verification Challenges.......................................................................................35
Tutorial 8: Using Portable Stimulus for SoC Verification
as Applied on Mobile, Networking and Server Designs..................................36
Tutorial 9: Back to Basics: Doing Formal the Right Way....................................................37

3:00pm 4:00pm

Coffee Break

Room: Gateway Foyer

Tutorial 10: Validate Your Next Generation SoC Memories

Utilizing Advanced Verification Techniques...................................................37
Tutorial 11: It All Starts with Quality Design.......................................................................38

CON
2
DV
6
01

DVCon Expo & Booth Crawl

Room: Bayshore Ballroom

DVCon is doing it again! You wont want to miss the annual DVCon Booth
Crawl on the exhibit floor.
Cocktails and conversations in a casual environment with the DVCon
exhibitors.
By attending the Booth Crawl youll be automatically entered into a drawing
for a $500 VISA gift card. The winner must be present to win and will be
announced Monday night.
Mingle from booth to booth while enjoying food and drinks.
&

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5:00pm 7:00pm

Look for the flag to find a participating company!

12

Tutorial 12: Solving the Next Big SoC Challenges with

FPGA Prototyping and Stratix 10.....................................................................38

Special Thanks to Our Tutorial Sponsors

TM

MONDAY + Th ur sday t ut ori a l s

9:00am 12:00pm

Tutorial 1

Tutorial 1 - Preparing for IEEE UVM Plus UVM Tips

and Tricks

Tutorial 2 - SVA Advanced Topics: SVAUnit and Assertions

for Formal

Time: 9:00am - 12:00pm | Room: Oak

Time: 9:00am - 12:00pm | Room: Fir

Organizer:
Adam Sherer - Accellera Systems Initiative

Organizer:
Adam Sherer - Accellera Systems Initiative
While we are preparing for the future, we do need
to get chips out now. Debugging UVM testbenches
can be extremely difficult because errors often
appear in lines of SystemVerilog code that make
up the UVM package, as opposed to the user
written code. There are also a number of common
errors, that are hard to recognize because the
compiler gets off on the wrong track early, and
never recovers. Most of these errors can easily be
eliminated by following a structured approach to
debugging that targets these common errors first.

Knowing what these changes are can help

you prepare for the new standard. This part
of the tutorial will provide code examples and
recommendations from experts working in the IEEE.

This part of the tutorial will walk through an

introduction of UVM testbench features, a working
examples including common errors and fixes, and
conclude with the built in debugging features in
UVM and how to use them.
Speakers:
Doug Perry - Doulos
Srinivasan Venkataramanan - CVC Pvt., Ltd.
Srivatsa Vasudevan - Synopsys, Inc.

SystemVerilog Assertions (SVA) is one of the

central pieces in functional verification for protocol
checking or validation of specific functions.
This tutorial will introduce advanced topics for
assertion based verification including SVAunit and
SVA for formal.

This half of the tutorial closes with the presentation

of SVA test patterns for the most common temporal
sequences and scenarios.
In the second half of the tutorial we learn how to
define objects in SystemVerilog by specifying their
properties formally. Then, this formal specification
is used for assertion or coverage purposes with real
USB interface examples and show the advantages
over scripting and SystemVerilog always blocks.
For example, the Perl scripting was at least 3X less
efficient, while using SystemVerilog with always
structures was 6X worse. In addition, a well-defined
SVA library is part of the verification methodology
where generic sequences are reused.

This first half of the tutorial discusses SVA planning,

coding guidelines, SVAUnit (SVAUnit framework,
self-checking tests, debug), and test patterns.
Planning includes parametrization, temporal
sequence composition, sequence reuse and also
consider how the SVA package will be integrated
with other verification methods. Coding guidelines
ensure efficiency as well as avoid common
implementation pitfalls.

Finally, the inclusion of SVA reduces the debug

effort since SVA points to a specific area where the
error was detected.

SVAUnit is a new concept that specifically addresses

these requirements and more:
Decouple assertion validation code from assertion
definition code

This second half of the tutorial contains 3 sections,

the first part explains the formal specification where
its basics are clearly described using SystemVerilog
language as a vehicle. The second and third part
cover the formal specification applications on
assertions and coverage respectively.

Simplify the generation of a wide range of stimuli,

from 1 bit signal toggling to transactions
Provide the ability to reuse scenarios
Provide self-checking mechanisms

Speakers:
Ionut Ciocirlan - AMIQ srl
Andra Radu - AMIQ srl
Rodrigo Calderon-Rico - Intel Corp.
Israel Tapia - Intel Corp.

Report test status automatically

Integrate with major simulators

14

15

MON DAY, F E B R UARY 29

MON DAY, F E B R UARY 29

UVM is poised to make the great leap to the

IEEE with the work in the 1800.2 committee. In
preparation for this new step and as part of
the work done in the IEEE, there are changes
you should know about the IEEE version of the
standard. Some of the most significant changes are
involve retiring hidden APIs.

Time: 12:00pm - 1:30pm | Room: Pine/Cedar

Organizer:
Adam Sherer - Accellera Systems Initiative
Speaker:
Tom Fitzpatrick - Mentor Graphics Corp.
Shishpal Rawat - Intel Corp.

MON DAY, F E B R UARY 29

The Accellera Tutorial Day 2016 at DVCon will be filled

with exciting technical insights youll be able to apply
immediately to your projects. In the middle of the day
well take a break and gather for lunch and look forward.

Sponsored by:
TM

Well start with a presentation by Accellera that will

include the 2016 Technical Excellence award, a look
forward to the worldwide DVCon events, and working
group activities. After that, the Portable Stimulus
Working will give us an update on this exciting standard
under development in 2016.

Tutorial 3 - Cut Your Design Time in Half with

Higher Abstraction
Time: 2:00pm - 5:00pm | Room: Oak
Organizer:
Adam Sherer - Accellera Systems Initiative
In the quarter century that RTL has been our main digital
design abstraction, the silicon devices that we build have
grown 4 orders of magnitude in gate count. Our projects
are managing millions of lines of code eating into our
design and verification efficiency. Such dizzying growth
makes the design engineer wonder is it time to move
up abstraction again?

algorithms written at RTL and those written using the

synthesizable subset, explaining the reasons behind the
coding choices and the downstream implications for RTL
and gates. We will also discuss how a synthesis standard
is the foundation for a full design and verification
ecosystem at a higher level of abstraction and the value
that can bring to the designer.

We in the Accellera SystemC Synthesis Working Group

(SSWG) think the answer is YES. The most recent draft of
a synthesizable subset standard for SystemC has been
available for public review and wed like to introduce it to
you. This tutorial is focused on the engineer today who is
coding in Verilog/SystemVerilog or VHDL. We will explain
how to use the language subset to write synthesizable
models at a higher level of abstraction than RTL.
We will provide real code examples comparing

Well conclude with some potential directions for

the synthesis subset that will further enable the HLS
ecosystem and a Q/A panel session with our presenters.

Speakers:
Bob Condon - Intel Corp.
Frederic Doucet - Qualcomm, Inc.
Peter Frey - Mentor Graphics Corp.
Mike Meredith - Cadence Design Systems, Inc.
Dirk Seynhaeve - Intel Corp.

DVCon India

Sponsored Luncheon - Accellera Lunch Featuring the 2016

Technical Excellence Award and a Portable Stimulus Update

2016

TM

Join us in Bangalore for DVCon India!

Tutorial 4 - SystemVerilog-AMS: The Future of Analog/

Mixed-Signal Modeling
Time: 2:00pm - 5:00pm | Room: Fir
Organizer:
Scott Little - Intel Corp.
In the 2012 revision of SystemVerilog, nettypes and
interconnect were added to provide language features
for modeling analog/mixed-signal (AMS) circuits. While
these constructs are useful, they do not provide a
complete solution for those interested in complex
AMS modeling scenarios. Verilog-AMS is a much more
complete AMS modeling solution, but it is based on the
Verilog IEEE Std 1364-2005 standard which has been
superseded by SystemVerilog.

Over the past two years, a small group of Verilog-AMS

and SystemVerilog experts have been meeting with the
goal to unify SystemVerilog and Verilog-AMS. This tutorial
will provide an introduction to the concepts underlying
the upcoming SystemVerilog-AMS language standard.

Speakers:
Martin Vlach - Mentor Graphics Corp.
Scott Little - Intel Corp.

September 15-16, 2016 | DVCon-India.org

Leela Palace, Bangalore India

17

tuesdays
agenda

Opening Session
Time: 8:15am - 8:45am | Room: Oak/Fir
Join us as we set the stage for the 2016 DVCon Conference and Exhibition. DVCons Steering Committee will
highlight the conferences events.

Coffee Break

Room: Gateway Foyer

Session 1 - UVM Applications - I

8:15am 8:45am

Opening Session

9:00am 10:30am

Session 1

10:30am 12:00pm

Poster Session

12:00pm 1:15pm

Sponsored Luncheon

1:30pm 2:30pm

Room: Oak/Fir Ballroom

UVM Applications - I
Room: Oak

3:00pm 4:30pm
5:00pm 6:00pm

Session 2

Design and Modeling

Approaches
Room: Fir

Session 3

Low-Power Verification
Room: Monterey/Carmel

Enterprise Verification Visualize This!

Room: Pine/Cedar

Walden C. Rhines - Mentor Graphics Corp.

Room: Oak/Fir

Session 2 - Design and Modeling Approaches

Time: 9:00am - 10:30am | Room: Fir

Room: Gateway Foyer

2.1 Full Flow Clock Domain Crossing From Source to Si

Mark Litterick - Verilab Ltd.

DVCon Expo

2.2 Modeling Analog Systems Using Full Digital

Simulations, a State Space Approach
Rajat K. Mitra - Cadence Design Systems, Inc.

Room: Bayshore Ballroom

Session 5

SystemVerilog
Programming and
Techniques
Room: Oak

1.3 Using Portable Stimulus to Verify Cache

Coherency in a Many-Core SoC
Adnan Hamid - Breker Verification Systems, Inc.
Thomas L. Anderson - Breker Verification
Systems, Inc.
David Koogler - Cavium, Inc.

Session Chair:
Stuart Sutherland - Sutherland HDL, Inc.

Coffee Break

expo

1.1 UVM Register Modelling at the IntegrationLevel Testbench

Wayne Yun - Advanced Micro Devices, Inc.

Sponsored by:

Keynote Address: Design Verification Challenges:

Past, Present and Future

dvcon

Session Chair:
Dave Rich - Mentor Graphics Corp.

1.2 Adapting the UVM Register Abstraction

Layer for Burst Access
Mark Villalpando - General Dynamics Mission
Systems

Room: Gateway Foyer

2:30pm 4:00pm
2:30pm 6:00pm

Time: 9:00am - 10:30am | Room: Oak

Session 6

Advanced Fault
Analysis Techniques
Room: Fir

2.3 Applying High-Level Synthesis for

Synthesizing Hardware Runtime STL
Monitors of Mission-Critical Properties
Konstantin Selyunin
- Vienna Univ. of Technology
Thang Nguyen - Infineon Technologies AG
Andrei-Daniel Basa - Infineon Technologies AG
Ezio Bartocci - Vienna Univ. of Technology
Dejan Nickovic - IST Austria
Radu Grosu - Vienna Univ. of Technology

Session 7

Effective Emulation
Room: Monterey/Carmel

DVCon Reception

Room: Bayshore Ballroom

18

19

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t ue sday, m ar ch 1

7:45am 12:00pm

Session 3 - Low-Power Verification

Session 4 - Poster Session

Time: 9:00am - 10:30am | Room: Monterey/Carmel

Time: 10:30am - 12:00pm | Room: Gateway Foyer

Session Chair:
Charles Dawson - Cadence Design Systems, Inc.
3.2 UPF Generic References: Unleashing the
Full Potential
Durgesh Prasad - Mentor Graphics Pvt. Ltd.,
India
Jitesh Bansal - Mentor Graphics Pvt. Ltd.,
India
3.3 Incomplete Low-Power Verification Flow
& the Oncoming Internet of Things (IoT)
Tsunami!
Neyaz Khan - Maxim Integrated
Kamran Haqqani - Maxim Integrated

Session 4 - Poster Session

Time: 10:30am - 12:00pm | Room: Gateway Foyer
Session Chair:
Shankar Hemmady - Synopsys, Inc.
4P.1 Molding Functional Coverage for Highly
Configurable IP
Jeremy Ridgeway - Avago Technologies
Kavitha Chaturvedula - Avago Technologies
Karishma Dhruv - Consultant

4P.8 Cross Coverage of Power States

Veeresh V. Singh, Awashesh Kumar
- Mentor Graphics Pvt. Ltd., India
4P.11 Detoxify Your Schedule With A Low-Fat
UVM Environment
Nihar Shah - Oracle Labs

4P.3 Distributed Simulation of UVM Testbench

Theta Yang - Advanced Micro Devices, Inc.

4P.13 UVM Based Approach to Model Validation

for SV-RNM Behavioral Models
Donald C. Lewis - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.

4P.5 Coverage Driven Signoff with Formal

Verification on Power Management IPs
Baosheng Wang - Advanced Micro Devices, Inc.
Xiaolin Chen - Synopsys, Inc.

4P.14 How Do You Verify Your Verification

Components
Joshua W. Rensch - Superion Technology
Neil Johnson - XtremeEDA Corp.

4P.6 A Holistic Approach to Low Power

Mixed-Signal Design Verification Using
Power Intent
Vijay Kumar - Cadence Design Systems, Inc.
Lakshmanan Balasubramanian
- Texas Instruments India Pvt. Ltd. & IEEE
Bharath Kumar Poluri - Texas Instruments
India Pvt. Ltd.
Badrinarayan Zanwar - Cadence Design
Systems, Inc.
Qingyu Lin - Cadence Design Systems, Inc.
Venkatraman Ramakrishnan
- Texas Instruments India Pvt. Ltd.

4P.16 Aceing the Verification of SOCs with

Cache Coherent Heterogeneous
Multiprocessors Targeted for Optimized
Power Consumption
Mehul Kumar - Broadcom Corp.
Amir M. Nilipour - Synopsys, Inc.
Tushar Mattu - Synopsys, Inc.

20

4P.27 Practical Considerations for Real

Valued Modeling of High Performance
Analog Systems
Dushyant Juneja - Analog Devices, Inc.
Siddharth Prabhu - Analog Devices, Inc.
Syam Veluri- Analog Devices, Inc.

4P.18 Introspection Into SystemVerilog Without

Turning It Inside Out
Dave Rich - Mentor Graphics Corp.

4P.28 Automated Specification Driven

Verification by Generation of System
Verilog Assertions
Ferdinando Pace - Sensirion AG

4P.19 Power State to PST Conversion:

Simplifying Static Analysis and Debugging
of Power Aware Designs
Madhur Bhargava - Mentor Graphics Pvt.
Ltd., India
Pankaj Gairola - Mentor Graphics Corp.

4P.29 Programming Model Inheritance and

Sequence Reuse
Aji Varghese - Texas Instruments, Inc.

4P.20 Multi-Tier Power-Aware Verification of

SoC ICs
Sergey Golubkov - Advanced Micro Devices, Inc
Pearl Liu - Advanced Micro Devices, Inc
David Akselrod - Advanced Micro Devices, Inc.

4P.31 A Client-Server Method for Register

Design and Documentation
Scott D. Orangio - ADVA Optical Networking
Julien Gagnon - Hardent
4P.32 Marrying Simulation and Formal
Made Easier!
Lun Li - Samsung Austin R&D Center
Durga Rangarajan - Samsung Austin R&D Center
Christopher Starr - Samsung Austin R&D Center
James Greene - Samsung Austin R&D Center
Nitin Mhaske - Synopsys, Inc.

4P.21 Reset and Initialization, the Good, the Bad

and the Ugly
Ping Yeung - Mentor Graphics Corp.
Kaowen Liu - MediaTek, Inc.
4P.22 Improving the UVM Register Model:
Adding Product Feature Based API for
Easier Test Programming
Krishnan Balakrishnan - Analog Devices, Inc.
Courtney Fricano - Analog Devices, Inc.
Kaushal M. Modi - Analog Devices, Inc.

4P.33 Testing the Testbench

Stan Sokorac - ARM, Inc.
4P.34 Tough Verification Challenges: Data
Visualization to the Rescue
Shaji Kunjumohamed - Broadcom Corp.

4P.23 EASI2L: A Specification Format for

Automated Block Interface Generation
and Verification
Chintan Kaur - Rensselaer Polytechnic
Institute
Ravi Narayanaswami - Google, Inc.
C. Richard Ho - Google, Inc.

4P.35 Slaying the UVM Reuse Dragon. Issues and

Strategies for Achieving UVM Reuse
Michael Baird - Willamette HDL
Robert D. Oden - Mentor Graphics Corp.

4P.24 Evolution of TRIAGE - Realtime

Improvements in Debug Productivity
Gordon Allan - Mentor Graphics Corp.
4P.25 Automating Sequence Creation from a
Microarchitectural Specification
Subramoni Parameswaran - Xilinx, Inc.
Ravi Ram - Xilinx, Inc.

21

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3.1 Pre-Silicon Power Management

Verification of Complex SOCs: Experiences
with Intel(c) Moorefield
Nivedha Krishnakumar - Intel Corp.
Robert J. Karas - Intel Corp.
Bryan Morgan - Intel Corp.
Neil A. Rosenberg - Intel Corp.
Billy J. Dennie - Intel Corp.
Rajeev Muralidhar - Intel Corp.

4P.26 Verification with Multi-Core Parallel

Simulations: Have You Found Your Sweet
Spot Yet?
Rohit K. Jain - Mentor Graphics Corp.
Shobana Sudhakar - Mentor Graphics Corp.

4P.17 The Art of Portable and Reusable

UVM Shared System Memory Model
Verification Methodology Across Multiple
Verification Platforms: UVM IP StandAlone, ComboWhacker, Virtual FPGA and
SoC Full Chip
Roman Wang - Advanced Micro Devices, Inc.
Thomas Bodmer - Advanced Micro Devices, Inc
Beryl Chen - Advanced Micro Devices, Inc.

Session 4 - Poster Session

Keynote Address - Design Verification Challenges:

Past, Present and Future

Time: 10:30am - 12:00pm | Room: Gateway Foyer

4P.36 DVS Interface Elements A Novel
Approach in Multi-Power Domain, MixedSignal Design Verification
Vijay Kumar - Cadence Design Systems, Inc.
Ji Du - Cadence Design Systems, Inc.
Qingyu Lin - Cadence Design Systems, Inc.
Arumugan A - Cadence Design Systems, Inc.
Badrinarayan Zanwar - Cadence Design
Systems, Inc.
Shekar Chetput - Cadence Design Systems, Inc.

4P.41 De-Mystifying Synchronization Between

Various Verification Components by
Employing Novel UVM Classes
Pushpal Nautiyal - Synopsys India Pvt. Ltd.
Gaurav Chugh - Synopsys India Pvt. Ltd.
Srivatsa Vasudevan - Synopsys, Inc.
4P.43 System to Catch Implementation Gotchas
in the RTL Restructuring Process
Anmol Rattan - STMicroelectronics
Satinder Singh Malhi - STMicroelectronics
Balwinder Singh Soni - STMicroelectronics
Anuj Kumar - Synopsys, Inc.
Navneet Chaurasia - Synopsys, Inc.
Sami Akthar - Synopsys, Inc.
4P.44 A Complete SystemC Process
Instrumentation API and its Application
to Simulation Performance Analysis
Bishnupriya Bhattacharya - Cadence Design
Systems, Inc.
Chandra Sekhar Katuri - Cadence Design
Systems, Inc.
Vincent Motel - Cadence Design Systems, Inc.

4P.38 Jump-Start Portable Stimulus Test

Creation with SystemVerilog Reuse
Matthew Ballance - Mentor Graphics Corp.
4P.39 Collaboratively Utilize SVA in UVM
Based Simulation
Kathy Zhang - Avago Technologies
4P.40 A New Class Of Registers
Mark Peryer - Mentor Graphics Corp.
David Aerne - Mentor Graphics Corp.

4P.45 Low Power Verification with LDO

Shang-Wei Tu - MediaTek, Inc.
Amol Herlekar - Synopsys, Inc.
Yu-Juei Chen - MediaTek, Inc.

Sponsored Luncheon - Enterprise Verification

Visualize This!
Time: 12:00pm - 1:15pm | Room: Pine/Cedar
Organizer:
Rebecca Granquist - Mentor Graphics Corp.

Sponsored by:

Speaker:
Stephen Bailey - Mentor Graphics Corp.

Speaker:
Walden C. Rhines, Chairman and Chief Executive Officer - Mentor Graphics Corp.
Every time design verification methodologies
standardize enough to become manageable, a
new set of requirements emerges. Dr. Rhines
will review the history of each major phase of
verification evolution and then concentrate on
the challenges of newly emerging problems.
While functional verification still dominates the
effort, new requirements for security and safety
are becoming more important and will ultimately
involve challenges that could be more difficult than
those we have faced in the past.

He also supervised the development of the first TI

speech synthesis devices (used in Speak & Spell)
and is co-inventor of the GaN blue-violet light
emitting diode (now important for DVD players
and low energy lighting). He was President of TIs
Data Systems Group and held numerous other
semiconductor executive management positions.
Rhines has served five terms as Chairman of the
Electronic Design Automation Consortium and
is currently serving as a director. He is also a
board member of the Semiconductor Research
Corporation and First Growth Family & Children
Charities. He has previously served as chairman of
the Semiconductor Technical Advisory Committee
of the Department of Commerce and as a board
member of the Computer and Business Equipment
Manufacturers Association (CBEMA), SEMISematech/SISA, Electronic Design Automation
Consortium (EDAC), University of Michigan National
Advisory Council, Lewis and Clark College and
SEMATECH.

Walden C. Rhines is Chairman and Chief Executive

Officer of Mentor Graphics, a leader in worldwide
electronic design automation with revenue of
$1.24 billion in 2014. During his tenure at Mentor
Graphics, revenue has nearly quadrupled and
Mentor has grown the industrys number one
market share solutions in three of the ten largest
product segments of the EDA industry.
Prior to joining Mentor Graphics, Rhines was
Executive Vice President of Texas Instruments
Semiconductor Group, sharing responsibility
for TIs Components Sector, and having direct
responsibility for the entire semiconductor
business with more than $5 billion of revenue and
over 30,000 people.

Dr. Rhines holds a Bachelor of Science degree

in metallurgical engineering from the University
of Michigan, a Master of Science and Ph.D. in
materials science and engineering from Stanford
University, a master of business administration
from Southern Methodist University and an
Honorary Doctor of Technology degree from
Nottingham Trent University.

During his 21 years at TI, Rhines managed TIs

thrust into digital signal processing and supervised
that business from inception with the TMS 320
family of DSPs through growth to become the
cornerstone of TIs semiconductor technology.

Session 5 - SystemVerilog Programming and Techniques

Time: 3:00pm - 4:30pm | Room: Oak
Session Chair:
Clifford Cummings - Sunburst Design, Inc.
5.1 SystemVerilog Interface Classes - More
Useful Than You Thought
Stan Sokorac - ARM, Inc.
5.2

22

5.3 Efficient Bug-Hunting Techniques Using

Graph-Based Stimulus Models
Nguyen D. Le - Microsoft Corporation
Mike Andrews - Mentor Graphics Corp.

Generic Programming in SystemVerilog

Mark Glasser - NVIDIA Corporation

23

t ue sday, m ar ch 1

t ue sday, m ar ch 1

4P.37 JESD204B Deterministic Latency

Verification with UVM Constrained
Random Approaches
Girish Nadiger - Analog Devices, Inc.
Ashok Chandran - Analog Devices, Inc.

Time: 1:30pm - 2:30pm | Room: Oak/Fir

wednesdays
agenda

Session 6 - Advanced Fault Analysis Techniques

Time: 3:00pm - 4:30pm | Room: Fir
Session Chair:
Harry Foster - Mentor Graphics Corp.
6.1 Whose Fault Is It? Advanced Techniques for
Optimizing ISO 26262 Fault Analysis
Avidan Efody - Mentor Graphics Corp.

6.3 Fault Effects Analysis On Multiple

Abstraction Levels In Hardware Modeling
Bogdan-Andrei Tabacaru - Infineon
Technologies AG
Moomen Chaari - Infineon Technologies AG
Wolfgang Ecker - Infineon Technologies AG
Thomas Kruse - Infineon Technologies AG
Cristiano Novello - Infineon Technologies AG

6.2 A Universal DFT Verification Environment:

Filling the Gap Between Function
Simulation and ATE Test
Rui Huang - Advanced Micro Devices, Inc.

t ue sday, m ar ch 1

Time: 3:00pm - 4:30pm | Room: Monterey/Carmel

8:30am 9:30am
10:00am 12:00pm

Session Chair:
Logie Ramachandran - VeriKwest Systems Inc.
7.1 Activity Trend Guided Efficient Approach
for Peak Power Estimation Using Emulation
Gaurav Saharawat - Mentor Graphics Corp.
Saurabh Jain - Mentor Graphics Corp.

7.2 Invited Presentation: Hardware Emulation:

ICE vs Virtual
Lauro Rizzatti - Rizzatti LLC
Alex Starr - Advanced Micro Devices, Inc.

Colocated Meeting - The EDA Consortium Presents Crossing

the Chasm: From Technology to Valuable Enterprise Jim Hogan in Conversation with Ajoy Bose
Time: 6:00pm - 9:00pm | Room: Oak Ballroom
Organizer:
Steve Pollock - Semi-Pac Inc.
The EDA Consortium (EDAC) and its Emerging
Companies Committee will host Crossing the
Chasm: From Technology to Valuable Enterprise,
featuring Jim Hogan in conversation with Dr. Ajoy
Bose, formerly of Atrenta Inc. (now Synopsys).

Tuesday, March 1, from 6:00 - 9:00pm, starting with

networking and refreshments.
Panelists:
Jim Hogan - Vista Ventures
Ajoy Bose - Synopsys, Inc.

It is open free of charge to all EDAC member

companies and DVCon attendees. Non-EDAC
members are invited to attend for a fee of $40.
The EDA Consortium is the provider of services,
market awareness and a common voice for EDA
and IP suppliers to the global semiconductor
industry.

24

12:00pm 1:15pm

1:30pm 2:30pm

Coffee Break

Room: Gateway Foyer

Panel

Redefining ESL
Room: Oak/Fir

Session 8

UVM Applications - II
Room: Oak

3:00pm 4:30pm

Session 3

Advanced Mixed-Signal
Practices
Room: Fir

Verification Processes
and Resource
Management
Room: Monterey/Carmel

Sponsored Luncheon

Software Driven Verification with Portable Stimulus:

The Next Productivity Leap Enabling the Continuum
of Verification Engines
Room: Pine/Cedar

Sponsored by:

Panel

Emulation + Static Verification Will Replace Simulation

Room: Oak/Fir

2:15pm 3:30pm
2:30pm 6:00pm

Session 9

Coffee Break

Room: Gateway Foyer

dvcon

expo

DVCon Expo

Room: Bayshore Ballroom

Session 11

Session 12

UVM Applications - III

Room: Oak

Formal Techniques
Room: Fir

Session 12

SystemVerilog and
Other Languages
Room: Monterey/Carmel

5:00pm 5:15pm

Best Paper & Poster Awards Presentation

5:00pm 6:00pm

DVCon Reception

Room: Bayshore Ballroom

Room: Bayshore Ballroom

25

w e dn e sday, m ar ch 2

Session 7 - Effective Emulation

8:00am 10:00am

Session 9 - Advanced Mixed-Signal Practices

Time: 8:30am - 9:30am | Room: Oak/Fir

Time: 10:00am - 12:00pm | Room: Fir

Moderator:
Brian Bailey - Semiconductor Engineering

Session Chair:
Neyaz Khan - Maxim Integrated

Organizers:
Dave Kelf - OneSpin Solutions GmbH
Nanette Collins - Nanette V. Collins Marketing and Public Relations

9.1 Verification of an Image Processing

Mixed-Signal ASIC
Milos Becvar, Kevin Buescher
- EM Microelectronic - US, Inc.
Greg Tumbush - Tumbush Enterprises, LLC
David Jenkins - FirstPass Engineering

9.3 Functional Coverage Collection for Analog

Circuits Enabling Seamless Collaboration
Between Design and Verification
Zhipeng Ye - Texas Instruments, Inc.
Honghuang Lin - Texas Instruments, Inc.
Asad Khan - Texas Instruments, Inc.

9.2 Mixed-Signal Systems-on-Chip Design

Verification with Automatic Real-Number
Abstraction
Frank Yang - Analog Devices, Inc.
Himadri De - Analog Devices, Inc.
Nancy Qiu - Analog Devices, Inc.
Nishtha Rakholiya - Orora Design
Technologies, Inc.
Yuan Cai - Orora Design Technologies, Inc.
C.-J. Richard Shi - Univ. of Washington

9.4 Unique Verification Case Studies of Low

Power Mixed Signal Chips
Venkatesh Ranga - NXP Semiconductors
Madhusudhan Subramanya - NXP
Semiconductors
Anand Shirwal - NXP Semiconductors
Pramod Rajan K S - NXP Semiconductors
Jeff Goswick - NXP Semiconductors

w e dn e sday, m ar ch 2

Brian Bailey of Semiconductor Engineering recently

wrote an article titled, What ESL Is Really About. ESL is
not a design flow, he noted, it is a verification flow, and
it will not take off until the industry recognizes that.

DVCon attendees are invited to join Brian and a panel

of distinguished experts who will attempt to define ESL
verification, from tools to flows. They will attempt to
answer: How or when can all the disparate pieces be
brought together, or is that even necessary?

With as many views as there are fragmented pieces of

ESL, panelists will have plenty of angles to consider as
they discuss raising the abstraction from the register
transfer level (RTL) for both design and verification. For
example, HLS raises design abstraction, but only works
well for certain parts of the design. Portable stimulus
raises the abstraction of test specification. Formal
works at this level because assertions can be written
similarly to parts of the specification. It is a fragmented
mess different inputs to the main design effort the
starts at RTL that will be a lively debate.

Panelists:
Adnan Hamid - Breker Verification Systems, Inc.
Dave Pursley - Cadence Design Systems, Inc.
Bryan Bowyer - Mentor Graphics Corp.
Simon Davidmann - Imperas Software Ltd.
Raik Brinkmann - OneSpin Solutions GmbH
Patrick Sheridan - Synopsys, Inc.

Session 8 - UVM Applications - II

Time: 10:00am - 12:00pm | Room: Oak

Time: 10:00am - 12:00pm | Room: Monterey/Carmel

Session Chair:
Joanne DeGroat - Ohio State Univ.

Session Chair:
Greg Tumbush - Tumbush Enterprises, LLC
8.1 How Far Can You Take UVM Code
Generation and Why Would You Want To?
John Aynsley - Doulos

8.3 Using UVM Virtual Sequencers

& Virtual Sequences
Clifford E. Cummings - Sunburst Design, Inc.
Janick Bergeron - Synopsys, Inc.

8.2 Design Patterns by Example for

SystemVerilog Verification Environments
Enabled by SystemVerilog 1800-2012
Eldon G. Nelson - Intel Corp.

8.4 Parameters, UVM, Coverage & Emulation

Take Two and Call Me In the Morning
Michael Horn - Mentor Graphics Corp.
Bryan Ramirez - Mentor Graphics Corp.
Hans van der Schoot - Mentor Graphics Corp.

Session 10 - Verification Processes and Resource Management

26

10.1 Verification Patterns Taking Reuse to the

Next Level
Harry D. Foster - Mentor Graphics Corp.
Michael Horn - Mentor Graphics Corp.
Robert D. Oden - Mentor Graphics Corp.
Pradeep Salla - Mentor Graphics Pvt. Ltd., India
Hans van der Schoot - Mentor Graphics Corp.

10.3 Optimal Usage of the Computer Farm for

Regression Testing
Daniel Hansson, Patrik Granath - Verifyter AB
10.4 The Cost of SoC Bugs
Ken Albin - Oracle Labs

10.2 Regressions in the 21st Century - Tools for

Global Surveillance
Venkataramanan Srinivasan
- Cypress Semiconductor Corp.
David Crutchfield, James F. Roberts
- Cypress Semiconductor Corp.
Tushar Gupta - Cypress Semiconductor Corp.

27

w e dn e sday, m ar ch 2

Panel - Redefining ESL

Sponsored Luncheon - Software Driven Verification with

Portable Stimulus: The Next Productivity Leap Enabling
the Continuum of Verification Engines
Time: 12:00pm - 1:15pm | Room: Pine/Cedar

w e dn e sday, m ar ch 2

Panelists:
Sharon Rosenberg - Cadence Design
Systems, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.
Alex Starr - Advanced Micro Devices, Inc.
RK Patil - Vayavya Labs Pvt., Ltd.
Sponsored by:

Moderator:
Jim Hogan - Vista Ventures
Emulation and static verification have both been
on a tear lately. With processor frequency at a
plateau of few GHz and the processor + system
architecture + software combination still catching
up to the parallelism imperative, emulation has
stepped up to fill the void nicely. Almost all chips
go through some combination of emulation or
FPGA-prototyping prior to product release. With
a cloud-based pay-as-you-go model, emulation
doesnt even have to be expensive. Emulation is all
about speed the only way to push through stimuli
through a high-end SOC.
Likewise static verification is also on a steep
upward spiral with almost universal adoption of
targeted tools for sign-off verification problems
like CDC as well as increasing adoption for
problems like power management, reset analysis,
X-verification, timing exceptions, security, SOC
integration etc. System-level functional formal
verification has been on a slower but also positive
adoption trajectory. On verification problems
where they work well, static methods have come
to deliver enhanced productivity and sign-off level
confidence. Static tools ensure that design quality
is already extremely high before simulation or
emulation is started.

May be the verification paradigm of the future is

to invest in high-end targeted static verification
tools to get the design to a very high quality level,
followed by very high-speed emulation or FPGAprototyping for system-level functional verification.
Where does that leave RTL simulation? Between
a rock and a hard place! Gate-level simulation is
already marginalized to doing basic sanity checks.
May be RTL simulation will follow. Or will it?
Panelists:
Ashish Darbari - Imagination Technologies Ltd.
Richard Ho - Google, Inc.
Lauro Rizzatti - Consultant
Brian Hunter - Cavium, Inc.
Steven Holloway - Dialog Semiconductor
Pranav Ashar - Real Intent, Inc.

Session 11 - UVM Applications - III

Time: 3:00pm - 4:30pm | Room: Oak
Session Chair:
John Dickol - Samsung Austin R&D Center
11.1 A 360 Degree View of UVM Events A Case Study
Deepak Kumar E V - elitePLUS Semiconductors
Technologies Pvt Ltd
Sathish Dadi - elitePLUS Semiconductors
Technologies Pvt Ltd
Vikas Billa - elitePLUS Semiconductors
Technologies Pvt Ltd

28

11.2 No RTL Yet? No Problem - UVM Testing a

SystemVerilog Fabric Model
Rich Edelman - Mentor Graphics Corp.
11.3 A UVM-Based Approach for Rapidly
Verifying Digital Interrupt Structures
Christoph Rumpler- Infineon Technologies AG
Alexander W. Rath - Infineon Technologies AG
Sebastian Simon - Infineon Technologies AG
Heinz Endres - Univ. of Applied Sciences
Wrzburg-Schweinfurt

w e dn e sday, m ar ch 2

This panel will discuss state-of-the-art solutions to

address these SoC level challenges. How to create
portable stimulus across engines? What are the right
mechanisms to define use cases and system-level
scenarios? Who keeps track of various configurations
and RTL integrations? What are the right innovative
approaches to software driven verification,
building on proven model based software testing
approaches? How can system actions, pre-conditions,
post conditions and resource requirements
be properly captured? How does metric driven
verification and coverage driven verification play into
all this?

Verification re-use becomes crucial both vertically

from IP to sub-systems to SoCs and Systems
and horizontally across the continuum of dynamic
verification engines from transaction-level base
virtual prototyping to RTL simulation, acceleration,
emulation, FPGA based prototyping all the way to the
actual chip testing. In addition, innovative techniques
to enable use-case re-use between different
disciplines like low power, cache coherency, driver
software etc. are needed to address the issue that
chip complexity simply has outgrown the ability for a
single architect to grasp all aspects.

Time: 1:30pm - 2:30pm | Room: Oak/Fir

Organizer:
Graham Bell - Real Intent, Inc.

Organizer and Moderator:

Frank Schirrmeister - Cadence Design Systems, Inc.
Verification is undergoing a transformation to
novel software driven approaches, introducing
unique challenges in terms of writing tests for the
complex interactions at the subsystem and SoC
level. Ensuring that expected performance targets
are achieved is becoming more and more difficult
due to the number of processors and the expanding
configuration choices of system interconnect.

Panel - Emulation + Static Verification

Will Replace Simulation

Session 12 - Formal Techniques

Time: 3:00pm - 4:30pm | Room: Fir
Session Chair:
Sean Safarpour - Synopsys, Inc.
12.1 Automated Safety Verification for
Automotive Microcontrollers
Holger Busch - Infineon Technologies AG

12.3 Do You Know What Your Assertions Are

Up To? A New Approach to Safety Critical
Verification Using Questa VIP
Lee C. Smith - Rockwell Collins, Inc.

w e dn e sday, m ar ch 2

12.2 The Process and Proof for Formal

Sign-Off - A Live Case Study
Ipshita Tripathi - Oski Technology, Inc.
Ankit Saxena - Oski Technology, Inc.
Anant Verma - Oski Technology, Inc.
Prashant Aggarwal - Oski Technology, Inc.

join us in europe!

Session 13 - SystemVerilog and Other Languages

Time: 3:00pm - 4:30pm | Room: Monterey/Carmel
Session Chair:
Karen Pieper - Microsemi Corp.
13.1 UVM and SystemC Transactions An Update
David I. Long - Doulos
John Aynsley - Doulos

13.3 Analysis of TLM-2.0 and its Applicability to

Non Memory Mapped Interfaces
Guillaume Delbergue - GreenSocs Ltd
Mark Burton - GreenSocs Ltd
Bertrand Le Gal - Univ. of Bordeaux
Christophe Jego - Univ. of Bordeaux

13.2 Challenges in UVM+Python Random

Verification Environment for Digital Signal
Processing Datapath Design
Shabbar A. Vejlani - Analog Devices, Inc.
Ashok Chandran - Analog Devices, Inc.

Best Paper & Poster Awards Presentation

Time: 5:00pm | Room: Bayshore Ballroom
2016 Recipients of the Best Paper and Poster are announced by Technical Program Chair, Ambar Sarkar.
Sponsored by:

2016

October 19-20, 2016

Munich, Germany | DVCon-Europe.org
EUROPE

30

TM

THURSDAYs
agenda

Tutorial 5 - Advanced Validation and Functional Verification

Techniques for Complex Low Power System-on-Chips
Time: 8:30am - 12:00pm | Room: Donner
Organizer:
Rebecca Granquist - Mentor Graphics Corp.

8:00am 11:00am

Coffee Break

Room: Gateway Foyer

Tutorial 5

Tutorial 6

Advanced Validation and Functional

Verification Techniques for Complex
Low Power System-on-Chips
Room: Donner

Developing Innovative Verification

and Debug Methodologies Using
Synopsys VC Apps
Room: Siskiyou

8:30am 12:00pm

Sponsored by:

Tutorial 7

Tutorial 8

Methodology for Addressing MixedSignal SoC Verification Challenges

Room: Cascade

Using Portable Stimulus for SoC

Verification as Applied on Mobile,
Networking and Server Designs
Room: Sierra

Sponsored by:

12:15pm 1:45pm

Sponsored by:

Sponsored Luncheon

Industry Leaders Verify with Synopsys

Room: Donner/Siskiyou Ballroom

Tutorial 9

Back to Basics: Doing Formal the

Right Way
Room: Donner
Sponsored by:

2:00pm 5:30pm

Sponsored by:

Tutorial 6

Validate Your Next Generation

SoC Memories Utilizing Advanced
Verification Techniques
Room: Siskiyou
Sponsored by:

Tutorial 11

It All Starts with Quality Design

Room: Cascade
Sponsored by:

Tutorial 12

The following will also be discussed in this tutorial:

Application of Static Power aware checking
techniques

More designs now employ sophisticated power

management techniques.

Power-aware simulation for early verification

of the logical power management architecture
captured in the constraints and configuration UPFs
as well as the technology specific implementation
UPF necessary for implementation tools.
Specifically, we will explore coverage closure and
debug adapted for power aware simulations.

For example, design teams implement more power

domains per design with each power domain
placed in many different power states that balances
power consumption with system performance
requirements, leading to an exponential growth in
power domain interactions that must be thoroughly
verified.

Leveraging emulation technology for verification

of power management logic interactions with
system software and for estimation of system
power consumption under realistic software loads

Since overall system power management is usually

handled in software, software interactions with
hardware power management logic must be
verified. Furthermore, designers need to ensure
that the entire system stays within its power budget
as it traverses its legal power state space. Finally,
it is imperative that power management strategies
and their verification begin as early as possible
in order to facilitate and maximize power saving
opportunities at the architectural level.

Introduction to system-level power modeling at

the SystemC level of abstraction.
Speakers:
Gabriel Chidolue - Mentor Graphics Corp.
Vijay Chobisa - Mentor Graphics Corp.
Desinghu PS - ARM, Inc.

In this tutorial, you will learn the latest advances

in power architecture specification, leveraging
existing UPF standards and emerging low-power
design methodologiessuch as Successive
Refinement UPF methodology. You will also learn
how new constructs in IEEE p1801 2015 aka UPF
3.0 can facilitate power modeling at high levels of
abstraction and improve application of Successive
Refinement methodology.

Sponsored by:

Solving the Next Big SoC Challenges

with FPGA Prototyping and Stratix 10
Room: Sierra
Sponsored by:

2:30pm 4:00pm

Coffee Break

Room: Gateway Foyer

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Sponsored by:

Mentor Graphics, industry experts, and customers

will discuss new trends in the use of EDA tools
for the functional verification of power managed
designs.

Driven by process technology needs, government

legislation, and continued product integration and
miniaturization, reducing power consumption is a
mainstream primary design requirement for many
industry segments; including networking, mobile,
consumer, and IoT markets.

Tutorial 7 - Methodology for Addressing Mixed-Signal SoC

Verification Challenges

Time: 8:30am - 12:00pm | Room: Siskiyou

Time: 8:30am - 12:00pm | Room: Cascade

Organizer:
Rich Chang - Synopsys, Inc.

Organizer:
Mladen Nizic - Cadence Design Systems, Inc.

The complexity of SoC design and verification

environments is growing dramatically. Multiple
EDA tools with different use models are used by
design and verification engineers daily. Each of
the tool serves different purposes in the overall
design flow. Companies invest significant resources
to establish tool flows to manage the flow of
information between these tools, and customized
methodologies to achieve design goals.

Additionally, EDA vendors can ensure

interoperability with their tools and feed
information into Verdi to leverage its debug
capabilities.

Development of effective and efficient

methodologies is enabled by the provision of
convenient hooks in EDA tools for easy access to
information.

In this tutorial we will:

Ready to use apps in Verdis installation package

offer solutions to common tasks while the APIs
allow users to develop custom flows and checks
on designs and simulation results based on Verdis
KDB and FSDB databases.
Provide an introduction to VC Apps
Explain the resources available in VC Apps

Verdi, the industrys best-in-class SoC debug

solution offers a fully extensible platform for SoC
teams and third-party EDA vendors to develop
innovative debug capabilities to address this
growing challenge in the industry. Synopsys VC
Apps is a programming interface that provides
access to a wide array of design and simulation
information.

Introduce VC Apps data models

Walk step-by-step through the VC Apps
programming flow
VC Apps example demo
Present a case study
Speakers:
Rich Chang - Synopsys, Inc.
Jack Yen - Synopsys, Inc.

It allows SoC teams to access information from

Verdis databases and Verdis analysis engines
for design analysis and validation of design rules.
SoC teams can further maximize the effectiveness
of Verdi deployment with custom automation
programs that leverage the underlying design
knowledge infrastructure for data mining and
design manipulation applications.

Sponsored by:

What you will learn?

Todays designs in wireless, automotive, consumer,

power management and industrial applications
require high integration of analog and digital
functionality into a mixed-signal systems
implemented as single SoC or 2.5/3D integration.
Strong interdependence between analog and
digital, and complexity of the designs operating in
many configurations and modes amplifies already
challenging mixed-signal verification.

Practical approach to collect coverage on analog

and mixed-signal blocks, and top-level measure
on full functional coverage of the design
How to model electrical behavior using Real
Number for event driven simulation
How to verify low power intent in mixed-signal
design using Common Power Forman (CPF)
or IEEE-1801 (UPF) controlled mixed-signal
simulation

Verification engineers must verify connectivity,

functionality and power in all modes for individual
components as well as entire system as early
as possible. Traditionally, verification involving
any analog content was done using direct test
methodology with transistor level simulation
limiting how much can be verified in a given time.
Coverage metric has been used on digital, but
growing complexity of mixed-signal designs require
coverage and metric driven methodology to be
applied on analog as well.

How to model components using RNM following

UVM methodology and implement verification
plan to verify functionality on Fractional-N PLL
How to model a power converter using
SystemVerilog RNM and verify voltage overshoot,
over-current and temperature responses, fault
recovery, entry and exit out of low power state
and other functionality
Who should attend?

The tutorial session will cover:

SoC and System Architects

State-of-the art, metric-driven methodology

required to address functional verification
challenges in mixed-signal designs, including:

SoC Integration Engineers

Engineers designing analog, mixed-signal and
digital circuits

Functional coverage for analog

Verification and Modeling Engineers

Usage of assertions for automating checking of

analog functionality

Verification and Design managers

Verification planning and management

Speakers:
Ayesha Chowdhury - Texas Instruments, Inc.
Raj Mitra - Cadence Design Systems, Inc.

Best practices in modeling analog behavior

using wreal/Verilog-AMS and Real Number in
SystemVerilog IEEE 1800-2012
Techniques and tools for automating model
generation and regression

Sponsored by:

Reusable testbench development with constraint

random stimuli following Universal Verification
Methodology (UVM) applied on analog and
mixed-signal

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Tutorial 6 - Developing Innovative Verification and Debug

Methodologies Using Synopsys VC Apps

Tutorial 8 - Using Portable Stimulus for SoC Verification as

Applied on Mobile, Networking and Server Designs
Time: 8:30am - 12:00pm | Room: Sierra

Time: 2:00pm - 5:30pm | Room: Donner

Organizer:
Rebecca Granquist - Mentor Graphics Corp,

Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc.
Developers are facing processor architectures in
a large variety of devices, from sensors through
mobile and consumer devices all the way to
networking and servers enabling cloud based
applications. System on Chips (SoCs) include
more and more processor cores, more IP,
complex power control, coherent interconnect,
and complex software controlled operations.
Verification is undergoing a transformation to novel
software driven approaches, introducing unique
challenges in terms of writing tests for the complex
interactions at the subsystem and SoC level.

Furthermore we will introduce innovative

approaches to software driven verification,
building on proven model based software testing
approaches, allowing to capture system actions,
pre-conditions, post conditions and resource
requirements to validate SoC level features and
generate portable stimuli including coverage
analysis. We will also discuss how you can
achieve 10X faster SoC performance analysis and
verification of ARM CoreLink IP-based systems, as
well as how verification can be accelerated using
mixed TLM-RTL execution approaches both in
software simulation as well as in hardware assisted
execution of hardware/software verification.

Ensuring that expected performance targets are

achieved is becoming more and more difficult due
to the number of processors and the expanding
configuration choices of system interconnect.
Developing hardware and software in parallel is
often facing significant barriers: Suitable models for
all the IP blocks may not be available and when they
are available then they may be in RTL only, lacking
corresponding transaction-level models.

Speakers:
Frank Schirrmeister - Cadence Design
Systems, Inc.
Larry Melling - Cadence Design Systems, Inc.
Raj Mathur - Cadence Design Systems, Inc.
Sharon Rosenberg - Cadence Design
Systems, Inc.

This tutorial will take a close look at state-of-the-art

solutions to address these SoC level challenges and
demonstrate a comprehensive SoC verification flow,
illustrated through use of case studies where these
approaches have been utilized in practice.

Automated formal apps have introduced a new

generation of D&V engineers to the power of
formal verification without the pain. This success
has inspired renewed interest in creating formal
testbenches for DUT-specific verification challenges
that are well suited to formal.

Run formal the right way simple tips to setup

the analysis for rapidly reaching a solution
Looking at coverage the right way measuring
minimal sequential distance as a way to
measure formal coverage and judge whats the
correct number of assertions.

Join Mentor Graphics, industry experts, and

customers for this tutorial to learn how to:

Speakers:
Joe Hupcey - Mentor Graphics Corp.
Mark Eslinger - Mentor Graphics Corp.
Doug Smith - Mentor Graphics Corp.

Write assertions the right way easy to learn

SVA coding tricks that get the most out of the
formal analysis engines AND ensure reuse with
simulation and emulation

Sponsored by:

Tutorial 10 - Validate Your Next Generation SoC Memories

Utilizing Advanced Verification Techniques
Time: 2:00pm - 5:30pm | Room: Siskiyou
Organizer:
Shankar Hemmady - Synopsys, Inc.

Sponsored by:

We will introduce the different options of hardware

assisted development and focus on how best
throughput for verification tasks can be achieved in
emulation and FPGA based prototyping.

Sponsored Luncheon - Industry Leaders Verify with Synopsys

Time: 12:15pm - 1:45pm | Room: Donner/Siskiyou Ballroom
Moderator:
Michael Sanie - Synopsys, Inc.
Hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have
achieved success, how you can apply their insights on your next project, as well as discussions about the
latest developments in the verification landscape.

Todays complex and sophisticated System on

Chip designs are geared towards achieving faster
performance with lower power consumption.
Even though Processor speed is an important
factor in those designs however with memory
intensive workloads many times the memory
system has a far greater impact on performance
than the CPU speed.

This tutorial is geared for Verification Engineers

who validate Memory Protocols and Timings either
at the Block or Chip level. It will review the various
Memory Technologies available today and their
corresponding application area, such as LPDDR,
HBM, HMC, and eMMC. And it will give an overview
of the VIP technology infrastructure used which
includes the test environment, coverage, debug,
and configuration components.

Verifying the memory subsystem at the Block or

SoC level requires State of the Art Verification
Techniques and Methodologies. Old fashion
and archaic approach using pure Verilog or
third party languages makes it difficult to
validate. Furthermore, utilizing latest Verification
methodologies, such as UVM, natively built over
SystemVerilog makes it the ideal verification
platform for the next generation Memory
Verification IPs.

Also, walk the attendees through topics such as:

Ease of integration, Dynamic and virtual part
selection, Configuration creator, Coverage support,
Error injection, Protocol training, and Advanced
Protocol debugging with Verdi.
Speakers:
Nasib Naser - Synopsys, Inc.
Robert Freeman - Synopsys, Inc.

Sponsored by:

36

Sponsored by:

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Tutorial 9 - Back to Basics: Doing Formal the Right Way

join us

Tutorial 11 - It All Starts with Quality Design

Time: 2:00pm - 5:30pm | Room: Cascade
Organizer:
Adam Sherer - Cadence Design Systems, Inc.

Th ur sday, m ar ch 3

We preach that the earlier we fix a problem the

lower the cost of the fix. When applied to electronics
that notion created the verification engineer and
an array of automation tools and standards to
make those engineers efficient. Hidden behind
the brilliance of verification is one important fact:
design is the starting point. To practice what we
preach, we must put more focus on design and
provide designers with automation tools so every
project starts faster with higher quality.
The challenge is that design is under massive
pressure. Individual designers are now managing
tens of thousands of lines of RTL code. Moreover,
they are increasingly responsible for unit testing and
initial quality of their designs. Since they dont have
time to learn verifications software engineering
they need to find efficient ways to improve quality.
While it might seem easy to just rely on verification
engineers to identify bugs, the designer is the one
who knows their code best.

in China

The good news is that this tutorial will reveal novel

technologies that are here today to both make the
designers more efficient and to increase the quality
of their designs.

for 2017

We will conduct a code review of an abstract model

exploring how to use these compact designs to
create efficient RTL to meet your spec. From there
well focus on one of the most challenging design
and verification problems today clock domain
crossing verification and how to apply formal
analysis to solve it. Finally, well look at advances
in root cause analysis debug and the connection
between designers and verification engineers to
resolve challenging bugs. Engineering experts will
present each topic using code examples and case
studies that you can take back to your project and
immediately apply.
Speakers:
Chris Komar - Cadence Design Systems, Inc.
Corey Goss - Cadence Design Systems, Inc.
Mike Meredith - Cadence Design Systems, Inc.
Sponsored by:

Tutorial 12 - Solving the Next Big SoC Challenges with FPGA

Prototyping and Stratix 10
Time: 2:00pm - 5:30pm | Room: Sierra
Organizer:
Rob van Blommestein - S2C, Inc.
Were all too familiar with the fact that large SoC
designs present challenges in both design and
verification. FPGA prototyping offers obvious
advantages for both design and verification but many
dismiss the notion of employing FPGA prototyping
because of size constraints, hardware scalability,
partitioning challenges, performance, debug ability,
and in-circuit testing. While previous generations
of FPGAs and FPGA prototyping couldnt tackle
large designs, advances in both FPGA and FPGA
prototyping technologies and methodologies have
given way to breaking through these challenges.
Sponsored by:

This tutorial will explore the advances of Alteras

Stratix 10 FPGA and the FPGA prototyping techniques
and technology that will work with Stratix 10 to
accomplish the prototyping of even the largest SoC.
Case studies will be provided that will demonstrate
how to properly take advantage of Stratix 10
FPGA prototyping for compiling, partitioning, and
debugging across multiple devices.
Speakers:
Toshio Nakama - S2C, Inc.
Manish Deo - Altera Corp.

2017

china

TM

DVCon-China.org
Dates and Location Coming Soon!

3rd Annual

Welcome to the
DVCon 2016 Expo!

BOOTH CRAWL
6
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on
ta i l s
s
v ersation

WIN $500!
Attend the Booth Crawl

Get automatically entered into a drawing for a $500 Visa gift card
Winner announced Monday at 6:45pm on the exhibit floor!
(Must be present to win)

Collaborate with vendors at the pinnacle of innovation!

Learn about new, cutting-edge technology and network with vendors well-tuned to todays
verification needs, and see how collaboration can take your design to the next level.

THANK YOU TO OUR SPONSORS:

IP Cores
Blue PMS 7463
Red PMS 1795

Dvcon expo

Dvcon expo

Exhibit Hours
CON
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ve ails ns
rsatio

Exhibitor Floorplan
Tuesday, March 1:
2:30pm - 6:00pm

Monday, February 29:

5:00pm - 7:00pm
Join us for the 3rd annual
booth crawl!

 ednesday, March 2:
W
2:30pm - 6:00pm

DVCon 2016 Exhibitors

Agnisys, Inc. .................................................. 704

Oski Technology, Inc. ................................... 205

Aldec, Inc. ...................................................... 602

PRO DESIGN Electronic .............................. 1001

AMIQ EDA ...................................................... 405

Real Intent, Inc. ............................................ 802

Avery Design Systems, Inc. .............................905

Rocketick, Inc. ............................................... 805

Blue Pearl Software ..................................... 401

S2C Inc. .......................................................... 904

Breker Verification Systems ....................... 304

Semifore, Inc. ................................................ 502

Cadence Design Systems, Inc. .................... 505

SmartDV Technologies ................................ 404

CAST, Inc.* ................................................... 1105

Sutherland HDL, Inc. - Sunburst Design .......302

DINI Group .................................................... 604

Synopsys, Inc. ............................................... 101

Doulos ........................................................... 301

Test and Verification Solutions LLC ........... 901

Networking Receptions

EDACafe.com .............................................. 1101

TRUECHIP .................................................... 1002

One of the main reasons you came to DVCon: NETWORKING!

Introduce yourself and leave DVCon with a deeper professional network!

InnovativeLogic, Inc. .................................... 801

Verification Academy................................... 702

MathWorks ................................................... 504

Verific Design Automation .......................... 402

Mentor Graphics Corp ................................. 501

Verifyter ........................................................ 305

OneSpin Solutions ....................................... 804

Vtool .............................................................. 902

CON
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ve ails ns
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Tuesday, March 1:
5:00 - 6:00pm
Networking Reception

Monday, February 29:

5:00 - 7:00pm
Join us for the 3rd annual
booth crawl!

 ednesday, March 2:
W
5:00 - 6:00pm
Networking Reception

* Denotes First-time Exhibitor

42

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Dvcon expo

Dvcon expo

Exhibitor Listing

Exhibitor Listing

Agnisys, Inc.

Blue Pearl Software

DINI Group

MathWorks

Agnisys is an emerging EDA company with 1000+ users

worldwide. Its product, IDesignSpec, enables design and
verification engineers to generate an array of outputs from
Design to Verification to Software to Documentation in a
number of formats. All from a single description, for which
multiple formats are also supported. SoC Enterprise
enables large teams to collaborate and create
Digital/AMS SoCs.

Blue Pearl Software, Inc. provides electronic design

automation software that accelerates IP and FPGA design
verification. The Blue Pearl Software Suite checks RTL
designs for functional errors, performs Clock Domain
Crossing (CDC) checks, and automatically generates
comprehensive Synopsys Design Constraints (SDC) to
improve quality of results (QoR). ASIC and FPGA designers
use Blue Pearl Software to find design errors before
simulation and the lab.

Located in La Jolla, California, Dini Group is a professional

hardware and software engineering firm specializing in
FPGA-based high performance digital circuit design and
application development. We have products targeted
to ASIC prototyping, High Performance Computing,
Algorithmic Acceleration (including Data Center), and Low
Latency Networking.

MathWorks is the leading developer of mathematical

computing software. Engineers and scientists worldwide
rely on its products to accelerate the pace of discovery,
innovation, and development. MATLAB and Simulink
are used throughout the automotive, aerospace,
communications, electronics, and industrial automation
industries as fundamental tools for research and
development. For more information visit
www.mathworks.com

Booth: 704
www.agnisys.com

Booth: 401
www.bluepearlsoftware.com

Aldec, Inc.

Breker Verification Systems

Booth: 602
www.aldec.com

Booth: 304
www.brekersystems.com

Established in 1984, Aldec is an industry leader in Electronic

Design Verification and offers a patented technology suite
including: RTL Design, RTL Simulators, Hardware-Assisted
Verification, SoC and ASIC Prototyping, Emulation, Design
Rule Checking, Clock Domain Crossing, VIP Transactors,
Requirements Lifecycle Management, DO-254 Functional
Verification and Military/Aerospace solutions.
www.aldec.com/

Breker, The SoC Verification Company, verifies your

most complex chip designs with realistic system-level
user scenarios. The Trek family of products and apps
automatically generates multi-threaded test cases that
verify your SoC more quickly and more thoroughly. These
test cases are portable from IP to full chip, and from
simulation to acceleration, emulation, FPGA prototypes,
and silicon in your lab.

AMIQ EDA

Cadence Design Systems, Inc.

Booth: 405
www.amiq.com

Booth: 505
www.cadence.com

AMIQ EDA provides software tools that enable design and

verification engineers to increase the speed and quality of
new code development, simplify legacy code maintenance,
accelerate language and methodology learning, improve
testbench reliability, extract automatically accurate
documentation, and implement best coding practices.
Its solutions, DVT Eclipse IDE, DVT Debugger Add-On,
Verissimo Linter, and Specador Documentation Generator
have been adopted worldwide. www.dvteclipse.com

Cadence is a global leader in software, hardware, design

and verification IP, and services that are transforming the
semiconductor industry. Our apps-driven approach to
creating, integrating, and optimizing electronic designs
helps customers develop innovative silicon chips, systemon-chip devices, and complete systems at lower cost and
with higher quality.

CAST, Inc.

Avery Design Systems, Inc.

Booth: 1105
www.cast-inc.com

Booth: 905
www.avery-design.com

CAST delivers high-value digital IP and VIP that helps

system developers save time, expand capabilities, and
improve quality. We feature low-power processors and
microcontrollers; popular peripherals and interconnects;
and a wide array of image, video, and data compression
cores and subsystems. Weve operated successfully for 20+
years, and have helped hundreds of customers ship millions
of product units.

44

Booth: 604
www.dinigroup.com

Booth: 504
www.mathworks.com

Doulos

Booth: 301
www.doulos.com

Mentor Graphics Corp.

Booth: 501
www.mentor.com

Doulos has set the industry standard for high quality

training and KnowHow for 25 years in design and
verification languages and methodologies for system,
hardware, and embedded software designers. The essential
choice for 3000+ companies across 60+ countries, Doulos
provides scheduled classes across North America and
Europe, and delivers on-site, training and live on-line
training worldwide. Find out more: www.doulos.com

Mentor Graphics delivers the most comprehensive

Enterprise Verification Platform (EVP), which combines
Questa for high performance simulation, verification
management and coverage closure, low-power verification
with UPF, CDC, Formal Verification, accelerated functional
coverage, and processor-based hardware verification,
Veloce OS3 global emulation technology, and the
Visualizer debug environment, to deliver performance
and productivity improvements ranging from 400X to
10,000X 400X to 10,000X, and Catapult and PowerPro
providing complete solutions for High Level Synthesis/
Verification and Low Power Analysis and Optimization.

EDACafe.com

Booth: 1101
www.edacafe.com

EDACafe.Com is the #1 EDA web portal. Thousands of IC,

SoC, FPGA, PCB, System designers and top level decisionmakers visit EDACafe.Com daily to learn about the latest
industry trends, design tools and services. Sign up for the
industrys best daily newsletter at www10.edacafe.com/nl/
newsletter_subscribe.php . Contact [email protected] to
book a video interview at the conference. Visit our booth to
sign up for a chance to win a KindleFire.

OneSpin Solutions

Booth: 804
www.onespin-solutions.com

OneSpin demonstrates formal technology leadership,

through a range of advanced verification solutions. These
include agile design evaluation, advanced, coverage-driven
ABV, and automated DV apps. Leading-edge challenges
are addressed, including safety critical, high-reliability
verification, SystemC/C++ algorithm analysis, and FPGA
Equivalency Checking. OneSpin has grown dramatically in
the last three years and may be found at most of the large
electronics companies.

InnovativeLogic, Inc.
Booth: 801
www.inno-logic.com

Innovative Logic is the leading provider of ASIC, FPGA,

Firmware, Software & IT services and Soft IP. We have very
flexible model to offer on-site, offsite or turnkey solutions
to our customers. We also provide complete soft IP solution
that includes source code, verification environment,
firmware, documentation, prototyping and extensive
support to ensure that you have successful product. We are
in business of offering the best quality services and soft IP
to many Fortune 500 companies for last 10 years.

45

Dvcon expo

Dvcon expo

Exhibitor Listing

Exhibitor Listing

Oski Technology, Inc.

S2C Inc.

Sutherland HDL, Inc. - Sunburst Design

Verification Academy

Oski Technology is a dedicated formal verification service

provider and formal sign-off company. Oskis Formal Sign-off
Methodology uses end-to-end checkers, constraints, Oski
Abstraction Models and formal coverage metrics to catch
corner case bugs, replace simulation and improve overall
verification efficiency. Oski provides formal verification
services to tape out critical projects, establish formal sign-off
methodology and help customers develop formal expertise.

S2C provides FPGA prototyping solutions. Our Prodigy

Complete Prototyping Platform consists of:
Rapid FPGA-based prototyping hardware and automation
software Prototype Ready IP, interfaces and platforms
Design verification and acceleration tools.
S2C systems have been deployed by leaders in consumer
electronics, communications, computing, image processing,
data storage, research, defense, education, automotive,
medical, design services, and silicon IP.
Visit us at booth #904.

Sutherland HDL provides private and open-enrollment

workshops onsite and online. We also license
professionally developed and maintained courses for
in-house training programs. Visit sutherland-hdl.com for
a description of workshops, open-enrollment schedules,
training quotes, and to download SystemVerilog-related
papers by Stuart Sutherland. Sunburst Design presents
high-energy, world-class training. Download papers by
Cliff Cummings at sunburst-design.com.
E-mail [email protected] for a training quote.

The Verification Academy is the most comprehensive

online resource for verification training. Organized into a
collection of free online courses, resources and forums, the
Verification Academy focuses on key aspects of advanced
functional verification, including: UVM, Coverage, AssertionBased Verification, Verification Management, CDC,
Acceleration, Low Power, FPGA Verification and more.

Semifore, Inc.

Synopsys, Inc.

Semifore Inc. provides the CSRSpec language and the

CSRCompiler, a complete register design solution for
hardware, software, verification, and documentation.
Collaboratively manage your design from a single
source specification. CSRSpec, SystemRDL, IP-XACT, or
Spreadsheet inputs generate: Verilog and VHDL RTL;
Verilog, or C headers; Perl, IEEE IP-XACT, UVM, HTML web
pages, and Word or Framemaker documentation.

Synopsys delivers comprehensive verification solutions

spanning the complete design cycle, including simulation,
emulation, advanced debug, static/formal verification,
FPGA-based prototyping and virtual prototyping. The
combination of best-in-class technology, verification IP,
advanced methodologies, open environments, and a robust
ecosystem enables users to solve the challenge of rapidly
escalating SoC complexities, accelerate the development
schedule, and bring innovative products to market faster.

Booth: 205
www.oskitechnology.com

Booth: 904
www.s2cinc.com

PRO DESIGN Electronic

Booth: 1001
www.profpga.com

ProDesign Electronics products and services include the

proFPGA family of ASIC Prototyping and FPGA systems.
The proFPGA system is a complete, scalable and modular
multi FPGA solution, which fulfills highest needs in the area
of FPGA based Prototyping. It addresses customers who
need a scalable and most flexible high performance ASIC
Prototyping solution for early software development and
real time system verification.

Booth: 502
www.semifore.com

Real Intent, Inc.

Booth: 802
www.realintent.com

SmartDV Technologies

Real Intent is the leading provider of EDA software to

accelerate Early Functional Verification and Advanced
Sign-off of digital designs. It provides comprehensive
clock-domain crossing verification, advanced RTL analysis
and sign-off solutions to eliminate complex failure modes
of SoCs. The Meridian and Ascent product families lead
the market in performance, capacity, accuracy and
completeness.

Booth: 404
www.smart-dv.com

SmartDV creates standard and custom verification

intellectual property (VIP), memory models and simulation
acceleration VIPs designed to work with coverage-driven
verification flows. All SmartDV VIPs ship with compliance
test-suite and comprehensive functional coverage models.
All VIPs are native UVM or language of customer choice.
SmartDV VIPs are 2-4x faster than competitor VIPs.
For more information on SmartDVs products,
see www.smart-dv.com/products.html.

Rocketick, Inc.

Booth: 805
www.rocketick.com

RocketSim seamlessly plugs into VCS/IES/Questa and

accelerates them by 3-30X by parallelizing logic calculation
over multiple CPU cores. As a result, regressions and debug
sessions finish sooner, while IT infrastructure and source
code are left untouched. RocketSim features unlimited
capacity, 4-state support, SVA acceleration, 80% memory
savings and fast compilation time.

Booth: 302
www.sutherland-hdl.com

Booth: 101
www.synopsys.com

Test and Verification Solutions LLC

Booth: 901
www.testandverification.com

T&VS provides hardware verification and software testing

products and services to the worldwide semiconductor
and embedded systems industries to help improve their
product time-to-market and quality. T&VS applies well
proven methodologies, tools and processes to ensure the
thoroughness of the verification, generating metrics to track
progress and enable a go-to-market decision thus enabling
our customers to focus their R&D resources on feature
development rather than QA.

TRUECHIP

Booth: 1002
www.truechip.net

46

Truechip is a leading provider of Design and Verification

solutions. Our portfolio of proven, plug-and-play
Verification IPs includes families of USB, PCIe, Memory,
AMBA, MIPI, Display and more protocols. All VIPs are
natively developed in SystemVerilog & UVM and are
compatible with formal/dynamic simulation and emulation.
All VIPs are in production use with customers worldwide.
To experience Truechips industry leading 24X5 support,
please visit www.truechip.net

Booth: 702
www.verific.com

Verific Design Automation

Booth: 402
www.verificationacademy.com

Build your own RTL tools with Verifics industry standard

SystemVerilog,VHDL, and UPF parsers ! With more than
60 active licensees worldwide, Verifics parsers are found
everywhere in EDA, FPGA, and semiconductor companies.
The parsers are written in C++, and its APIs are available in
Python, Perl, and C++.

Verifyter

Booth: 305
www.verifyter.com

Verifyter was founded 2010 with the mission to transform

the development process by automating debug of
regression test failures, especially targeting the ASIC
market. PinDown, Verifyters automatic debugger, is
currently used by both ASIC and ASIC IP companies and has
proven to speed-up the bug fixing cycle by up to 400% and
bring in the project release date by as much as 10%.

Vtool

Booth: 902
www.thevtool.com

Vtool is a verification productivity environment that

accelerates and simplifies the creation, comprehension and
debug of UVM testbenches. Leveraging synchronized visualtextural authoring, automated code/function generation,
and intelligent debug, Vtool enhances UVM environment
clarity,promotes reuse & teamwork, and accelerates
development. Already proven to cut weeks off real project
schedules, Vtool will restore your engineering freedom
while eliminating notorious UVM issues.

Dvcon expo

Dvcon expo

Thank You to Our Event Sponsors

Best

Exhibiting Companies

Paper Award

Registration

THE DESIGN VERIFICATION COMPANY

Blue PMS 7463

Red PMS 1795

IP Cores
Notepad

Lanyard

Media Sponsors

& Pen

Blue PMS 7463

Red PMS 1795

48

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Save
the
Date!
DVCon 2017
February 27 - March 2, San Jose, CA