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By Christian Plante, Director of Marketing For Low-Power and Mixed-Signal Fpgas, Actel Corp

Top 10 tips are provided to minimize power consumption when designing with FPGAs. Key tips include profiling the design to understand high and low power states, calculating power consumption for all device states including active, static and sleep, and determining the worst case static power consumption considering temperature and voltage changes over time. Additional tips include using available low power modes, minimizing RAM and I/O usage to reduce power sinks, and accounting for all system components when calculating total power consumption.

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44 views2 pages

By Christian Plante, Director of Marketing For Low-Power and Mixed-Signal Fpgas, Actel Corp

Top 10 tips are provided to minimize power consumption when designing with FPGAs. Key tips include profiling the design to understand high and low power states, calculating power consumption for all device states including active, static and sleep, and determining the worst case static power consumption considering temperature and voltage changes over time. Additional tips include using available low power modes, minimizing RAM and I/O usage to reduce power sinks, and accounting for all system components when calculating total power consumption.

Uploaded by

kanglc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Top 10 TIPS TO MINIMIZE POWER CONSUMPTION

WHEN DESIGNING WITH FPGAs


By Christian Plante, director of marketing for low-power and mixed-signal FPGAs, Actel Corp.

With stricter system power limits, specifications and standards that put a cap on the total power
consumed, system designers are increasingly challenged. Here are key Dos and Donts to help
designers manage power budgets with FPGAs.
DOs
Do profile your design. How long will the FPGA be running at high speed versus low speed
or with stopped clocks?
Can burst mode processing at a higher clock frequency, but with more device "sleep" time,
achieve the required system throughput?
Is it better to run the entire design at a lower clock frequency for longer periods of time? Most
FPGA suppliers provide power analysis and prediction tools to help in this process; however,
some tools can be overly optimisticbe careful.
Do calculate power consumption for each product state.
It is very important to account for power consumed by the device in all states over the product
lifetime or expected battery-operation time. At the very least, consider power-up, standby, idle,
dynamic and power-down states. For example, an FPGA in a consumer handheld device with
WiFi communication may have the following power profile: 5 percent active, 20 percent static
and 75 percent sleep.
Do calculate the worst-case static power consumption.
Newer FPGA technologies may have significantly higher static power consumption than
designers are aware of, particularly over-extended temperature ranges. Make sure core, I/O and
any auxiliary power supplies are taken into consideration. When calculating static power
consumption, P = I * V for each component and power supply is crucial in determining the
power consumed by the FPGA.
Do analyze the temperature and voltage changes expected over the product power profile.
Effects such as heat and voltage changes over the product operation time can dramatically
change the product power profile and need to be accounted for in the component power profile.
For example, SRAM-based FPGA power consumption at 50C may be ten times or more than
the power consumption at room temperature.
Do determine battery operation time for each system alternative.
Further calculation can be done to determine the battery operation time for each system
alternative (for example, high performance for short periods of time versus lower performance
for longer periods). This analysis will show which alternative offers the longest battery
operation time.
DONTS
Dont forget to use low-power modes.

Components for low-power applications usually offer easy-to-use low-power modes. The
characteristics of each mode are device dependent, as are the method and timing required to enter
or exit the power mode. Some power-saving modes require board considerations for
implementation, so the design should be able to accommodate that. Some modes cannot be used
due to complex implementation or long amounts of time for the application to enter or exit the
mode. For example, low-power modes offered by SRAM or SRAM hybrid FPGAs require
device reconfiguration with an associated power surge up to 1 Watt.
Dont let user static RAM and high I/O voltages sink excessive power.
When creating clock regions using local or regional clock resources, use "Enabled" logic to
disable clock transitions in the system. User static RAM can sink excessive power; therefore,
look for techniques to minimize RAM usage. I/Os can also sink a great deal of board power. Use
LVTTL standards and lower I/O voltages. Serial LVDS chip-to-chip data transfers using double
data rate registers may save power over parallel off-chip buses.
Check whether components can be integrated or functionality minimized to save even more on
power. A bigger FPGA may be able to accommodate a soft MCU and save significant power
over a two-chip solution, while reducing the toggle rate and total system resources used.
Dont rely solely on measured power data.
Base calculations on datasheet and power estimator numbers, and ask how those numbers were
obtained. Do the numbers also take into account silicon variations? Remember, what is
measured on the bench today may vary significantly from what may ship as a low-power device
tomorrow. Be careful when basing power calculations solely on measured data.
Dont omit power consumption levels of additional components.
In some cases, implementing solutions with a certain FPGA technology may require additional
components for support functions. For example, memory or a microcontroller may be required
for boot up, whereas nonvolatile FPGAs offer single-chip implementation.

About the Author


Christian Plante joined Actel in 2008, bringing with him more than 14 years of experience
in the semiconductor and computer hardware industries. Prior to joining Actel, he was the
director of customer marketing at Cswitch Corporation and also held several senior
marketing positions at Altera Corporation. Plante holds a bachelor's of science degree in
electrical engineering from Laval, Quebec City, Canada and a masters degree in business
administration from Queen's University, Kingston, Canada.

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