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ECE102 - F12 ProSet 7 PDF

This document provides exercises for analyzing differential amplifiers. The exercises include: 1) Computing voltages and currents for a differential amplifier circuit with and without channel length modulation. 2) Calculating the differential gain and transistor sizes for a matched differential pair circuit. 3) Determining transistor sizes, input voltages, and differential gain to achieve a target gain and power consumption. 4) Finding transistor sizes and differential gain for a cascode differential amplifier circuit.

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0% found this document useful (0 votes)
509 views37 pages

ECE102 - F12 ProSet 7 PDF

This document provides exercises for analyzing differential amplifiers. The exercises include: 1) Computing voltages and currents for a differential amplifier circuit with and without channel length modulation. 2) Calculating the differential gain and transistor sizes for a matched differential pair circuit. 3) Determining transistor sizes, input voltages, and differential gain to achieve a target gain and power consumption. 4) Finding transistor sizes and differential gain for a cascode differential amplifier circuit.

Uploaded by

lokeshwarrvrjc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 37

Exercises for

Differential Amplifiers

ECE 102, Fall 2012, F. Najmabadi

Exercise 1: Compute VD , VS , VDS and VGS if ID3 = 2 mA, RD = 500 ,


VOV3 = 0.5 V, and identical Q1 &Q2 with nCox (W/L ) = 8 mA/V2,
Vt = 0.5 V, = 0.
A) For VG = 0 and B) For VG = 1 V. Repeat the exercise for = 0.1 V-1.

This exercise shows that precise biasing of Q1 and Q2 is not necessary as VS


adjusts itself automatically.
Inclusion of channel-length modulation does not impact the bias points of Q1
and Q2 (which is set by the current source).
F. Najmabadi, ECE102, Fall 2012 (2/37)

Ignoring channel-length modulation ( = 0)


I D1 = I D 2 = 0.5 I D 3 = 1 mA

KVL: VD1 = 2 RD I D1 = 2 0.5 = 1.5 V


Assume Saturation
2
3 2
1 10 3 = I D1 = 0.5 n Cox (W / L) VOV
1 = 4 10 VOV 1

VOV 1 = 0.5 V
VGS 1 = VOV 1 + Vt = 1 V

A) VG1 = 0

A) VG1 = 1

VS = VG1 VGS 1 = 0 1 = 1 V

VS = VG1 VGS 1 = 1 1 = 0

VDS 1 = VD1 VS = 1.5 (1) = 2.5 V

VDS 1 = VD1 VS = 1.5 0 = 1.5 V

VDS 3 = VS (2) = 1 + 2 = 1 V

VDS 3 = VS (2) = 0 + 2 = 2 V

VDS 1 > VOV 1 & VDS 3 > VOV 3 Saturation

VDS 1 > VOV 1 & VDS 3 > VOV 3 Saturation

Note that as the bias voltage of Q1, VG1, changes, VS is


adjusted automatically to get the necessary VOV1 and ID1
F. Najmabadi, ECE102, Fall 2012 (3/37)

Including channel-length modulation ( = 0.1)


I D1 = I D 2 = 0.5 I D 3 = 1 mA

KVL: VD1 = 2 RD I D1 = 2 0.5 = 1.5 V


Assume Saturation
2
1 10 3 = I D1 = 0.5 nCox (W / L) VOV
1 (1 + nVDS 1 )
2
VOV
1 (1 + 0.1VDS 1 ) = 0.25

Need to write VDS1 in terms of VOV1:


VDS 1 = VD1 VS
= VD1 + (VGS 1 VG1 )
= VD1 + (VOV 1 + Vt ) VG1
= VOV 1 + (VD1 + Vt VG1 )

For a given VG1, we then substitute for VDS1 in ID


equation which leads to a cubic equation for VOV1

F. Najmabadi, ECE102, Fall 2012 (4/37)

Including channel- length modulation ( = 0.1)


VD1 = 1.5 V
2
VOV
1 (1 + 0.1VDS 1 ) = 0.25

VDS 1 = VD1 + (VOV 1 + Vt ) VG1

C) VG1 = 0

D) VG1 = 1 V

VDS 1 = VOV 1 + (1.5 + 0.5 0) = VOV 1 + 2.0

VDS 1 = VOV 1 + (1.5 + 0.5 1) = VOV 1 + 1.0

2
VOV
1 [1 + 0.1( VOV 1 + 2.0)] = 0.25

2
VOV
1 [1 + 0.1( VOV 1 + 1.0)] = 0.25

3
2
0.1VOV
1 + 1.2VOV 1 0.25 = 0

3
2
0.1VOV
1 + 1.1VOV 1 0.25 = 0

VOV 1 = 0.448 V

VOV 1 = 0.467 V

VGS 1 = VOV 1 + Vt = 0.948 V

VGS 1 = VOV 1 + Vt = 0.967 V

VS = VG1 VGS1 = 0 0.948 = 0.948 V

VS = VG1 VGS1 = 1 0.967 = +0.033 V

VDS 1 = 2.0 + VOV 1 = 2.448 V

VDS 1 = 1.0 + VOV 1 = 1.467 V

VDS 3 = VS (2) = 0.948 + 2 = 1.052 V

VDS 3 = VS (2) = 0.033 + 2 = 2.033 V

F. Najmabadi, ECE102, Fall 2012 (5/37)

Bias voltage of Q1 and Q2 (VG) does not affect ID1 as VS


adjusts itself automatically. VG affects only VDS1 and
VDS3 and precise biasing is NOT necessary.
Ignore channel-length modulation

I D1 = I D 2

= 1.0 mA

VOV 1 = VOV 2 = 0.500 V


VG1 = VG 2

=0 V

VS

= 1.00 V

VDS1

= 2.50 V

VDS 3

= 1.00 V

Include channel-length modulation

1.0 mA

1.0 mA

1.0 mA

0.500 V
1.0 V
0
1.50 V
2.0 V

0.448 V
0
0.948 V
2.448 V
1.052 V

0.467 V
1.0 V
0.033 V
1.467 V
2.033 V

Inclusion of channel-length modulation does


not impact the bias points of Q1 and Q2
(which is set by the Q3 current source).
F. Najmabadi, ECE102, Fall 2012 (6/37)

Specified
parameters

Exercise 2: Find the differential gain and (W/L) of all transistors in the
circuit below, Q3 & Q4 are matched, Q1 & Q2 are matched, all transistors
have VOV = 0.2 V, nCox = 400 A/V2, pCox = 100 A/V2, and VAn =
|VAp |= 3.6 V. Ignore channel-length modulation in biasing calculations.

For symmetric circuits:

vo 2 = vo1 vo ,d = vo 2,d vo1,d = 2vo1,d


Ad =

vo ,d
vd

= 2

F. Najmabadi, ECE102, Fall 2012 (7/37)

vo ,1d
vd

vo ,1d
0.5vd

Since transistors are matched and have the same VOV :


I D1 = I D 2 = I D 3 = I D 4 = 100 A
2
100 10 6 = I D1 = 0.5 n Cox (W / L)1 VOV
1

(W / L)1 = 12.5 = (W / L) 2
2
100 10 6 = I D 3 = 0.5 p Cox (W / L) 3 VOV
3

(W / L) 3 = 50 = (W / L) 4

Ad =

vo ,d
vd

vo ,1d

Differential Mode
Half Circuit

0.5vd

= g m1 (ro1 || ro 3 )
g m1 =

2 I D1
= 10 3 A/V
VOV 1

ro1 =

VA1
= 36 k
I D1

ro 3 =

V A3
= 36 k
I D3

Ad = g m1 (ro1 || ro3 ) = 10-3 (36 k || 36 k) = 10-3 18 103 = 18


F. Najmabadi, ECE102, Fall 2012 (8/37)

Exercise 3: The differential amplifier below should achieve a differential


gain of 40 with a power consumption of 2 mW. All transistors operate with
the same VOV . Find (W/L) of all transistors, VG3, VG4, and VG5.
(nCox = 400 A/V2, pCox = 100 A/V2, n = 0.1 /V, p = 0.2 /V, and
Vtn = |Vtp |= 0.4 V. Ignore channel-length modulation in biasing.

Power Consumption:
P = 1.8 I D 5 = 2 10 3 I D 5 = 1.11 mA
I D1 = I D 2 = I D 3 = I D 4 = 0.5 I D 5 = 0.556 mA

F. Najmabadi, ECE102, Fall 2012 (9/37)

Ad =

vo ,d
vd

vo ,1d
0.5vd

= g m1 (ro1 || ro 3 )
1
ro1 =
n I D1
ro 3 =

1
1
1
=
= n
= n ro1 = 0.5ro1
p I D 3 p I D1 p n I D1 p

ro1 || ro 3 =

ro1 (0.5ro1 ) ro1


=
3
ro1 + 0.5ro1

1
g m1ro1
3
1 2I
1
2
= D1
=
= 40
3 VOV 1 n I D1 0.3 VOV 1

| Ad | = + g m1 (ro1 || ro 3 ) =

VOV 1 = 0.167 V

F. Najmabadi, ECE102, Fall 2012 (10/37)

Differential Mode
Half Circuit

I D1 = I D 2 = I D 3 = I D 4 = 0.5 I D 5 = 0.556 mA
VOV 1 = VOV 2 = VOV 3 = VOV 4 = VOV 5 = 0.167 V
2
I D1 = 0.5 n Cox (W / L)1 VOV
1

0.556 10 3 = 0.5 400 10 6 (W / L)1 (0.167) 2


(W / L) 2 = (W / L)1 = 100
2
I D 3 = 0.5 p Cox (W / L) 3 VOV
3

0.556 10 3 = 0.5 100 10 6 (W / L) 3 (0.167) 2


(W / L) 4 = (W / L) 3 = 400
2
I D 5 = 0.5 n Cox (W / L) 5 VOV
5

VSG 3 = VOV 3 + | Vtp |= 0.167 + 0.4 = 0.567 V


VG 3 = VS 3 VSG 3 = 1.8 0.567 = 1.233 V

1.1110 3 = 0.5 400 10 6 (W / L) 5 (0.167) 2


(W / L) 5 = 200

VGS 5 = VOV 5 + Vtn = 0.167 + 0.4 = 0.567 V


VG 5 = VGS 5 + VS 5 = 0.567 + 0 = 0.567 V

F. Najmabadi, ECE102, Fall 2012 (11/37)

Exercise 4: The circuit below is fabricated with VAn = |VAp| = 3.6 V,


nCox = 100 A/V2 & pCox = 25 A/V2. All transistors operate with
VOV = 0.5 V. Find (W/L) of all transistors and the differential gain of the
circuit.

F. Najmabadi, ECE102, Fall 2012 (12/37)

n = p =

1
1
=
= 0.278 /V
VA 3.6

I D1 = I D 2 = ... = I D8 = 0.5I D 9 = 100 A


VOV 1 = VOV 2 = ... = VOV 8 = VOV 9 = 0.5 V
g m1 = g m 2 = ... = g m8
ro1 = ro 2 = ... = ro8 =

2 I D1 2 100 10 6
=
=
= 0.4 mA/V
0.5
VOV 1

1
1
=
= 36 k
6
I D1 0.278 100 10

NMOS: Q1, Q2, Q3, & Q4:


2
I D1 = 0.5 n Cox (W / L)1 VOV
1

100 10 6 = 0.5 100 10 6 (W / L)1 (0.5) 2


(W / L) 4 = (W / L) 3 = (W / L) 2 = (W / L)1 = 8

PMOS: Q5, Q6, Q7, & Q8:


2
I D 5 = 0.5 p Cox (W / L) 5 VOV
5

100 10 6 = 0.5 25 10 6 (W / L)1 (0.5) 2


(W / L)8 = (W / L) 7 = (W / L) 6 = (W / L) 5 = 32
F. Najmabadi, ECE102, Fall 2012 (13/37)

Ad =

vo ,d
vd

= 2

vo ,1d
vd

vo ,1d

g m1 = g m 2 = ... = g m8 = 0.4 mA/V

0.5vd

Method 1: Use formula for Cascode Amplifier on


Lecture Set 6, slide 14 (which assumes gmro >> 1):
Ad =

vo ,1d
0.5vd

ro1 = ro 2 = ... = ro8 = 36 k

= 0.5 ( g m ro ) 2

Differential Mode
Half Circuit

Ad = 0.5(0.4 10 3 36 103 ) 2 = 104


Method 2: Use multistage amplifier calculations (similar to
Lecture Set 6, slide 14 but not assuming gmro >> 1):
RL = ro 5 (1 + g m 5 ro 7 ) + ro 7
= 36 103 (1 + 0.4 36) + 36 103 = 590 k
AvQ 3 = vo1,d / v1 g m 3 (ro 3 || RL )
= 0.4 10 3 (36 k || 590k) = 13.6
r + RL
= 40.6 k
Ri 3 = o 3
1 + g m 3 ro 3

gmro >> 1 is a good


approximations

AvQ1 = v1 /( 0.5vd ) = g m1 (ro1 || Ri 3 )


= 0.4 10 3 (36 k || 40.6k) = 7.63
F. Najmabadi, ECE102, Fall 2012 (14/37)

Ad = AvQ 3 AvQ1 = 103.8

Exercise 5: Assume Q3 and Q4 as well Q1 and Q2 are identical. Compute the


differential gain.

This is a practice problem in


constructing half-circuit.

F. Najmabadi, ECE102, Fall 2012 (15/37)

Half-circuit for differential Gain


Zero voltage at symmetry line

Replace Q3 by
Elementary R forms

Ad =

vo ,d
vd

vo ,1d
0.5vd

= g m1 (r o1|| ro 3 || RP )

F. Najmabadi, ECE102, Fall 2012 (16/37)

Exercise 6: Compute the differential gain.

This problem has it all, half circuit, constructing


resistances from elementary R form, and
Cascode amplifier.

F. Najmabadi, ECE102, Fall 2012 (17/37)

Differential-Mode half-circuit

v1

RL = ro 5 [1 + g m (ro 7 || R p / 2)] + ro 7 || R p / 2
Since Rp value is not given, we cannot simplify RL expression using gmro >> 1 .
ro 3 + RL

Ri 3 =
AvQ 3 = vo1,d / v1 g m 3 (ro 3 || RL )
AvQ1 = v1 /( 0.5vd ) = g m1 (ro1 || Ri 3 )
1 + g m 3 ro 3
Ad = AvQ 3 AvQ1 = g m1 g m 3 (ro1 || Ri 3 )(ro 3 || RL )
F. Najmabadi, ECE102, Fall 2012 (18/37)

Exercise 7: What is the input common-mode range in the circuit below. Q1


and Q2 are Identical and RD = 500.
Use nCox (W/L ) = 8 mA/V2 , Vt = 0.5 V and VG3 = 1 V.

The input common-mode level is the range of DC


values that can be applied to the gate of Q1 and
Q2 (bias + signal) for which transistors remain in
saturation.
o Basically we are looking for range of DC
voltages (i.e., bias) that can be applied to Q1
and Q2 while keeping them in saturation.
o Then, for any given bias voltage, we can
calculate the range of common-mode signals
that can be applied to the circuit.
There are two limits: 1) for Q1 and Q2 remain in
saturation, 2) for Q3 to remain in saturation.
It is straight forward to extend this to active loads.
F. Najmabadi, ECE102, Fall 2012 (19/37)

Assume Q1 and Q2 in Saturation


3 2
2
1 10 3 = I D1 = 0.5 n Cox (W / L) VOV
1 = 4 10 VOV 1

VOV 1 = 0.5 V
VGS 1 = VOV 1 + Vt = 1 V
VD1 = 2 RD I D1 = 2 0.5 = 1.5 V

VOV 3 = VGS 3 Vt = VG 3 VS 3 Vt = 1 (2) 0.5 = 0.5 V

For Q3 in saturation:
VDS 3 VOV 3
VD 3 VS 3 = VS (2) 0.5
VS 2 + 0.5 = 1.5 V

For Q1/Q2 in saturation:


VDS1 VOV 1
VD1 VS 1 = 1.5 VS 0.5
VS 1.5 0.5 = 1 V

F. Najmabadi, ECE102, Fall 2012 (20/37)

1.5 VS 1 V
VGS 1 = VCM VS
VS = VCM 1
1.5 VCM 1 1
0.5 VCM 2 V

Exercise 8: Circuit below is designed to operate at zero bias voltage at the


gate of Q1 and Q2 (Q1 & Q2 are matched and = 0). The practical circuit,
however includes a slight mis-match of RD1 = RD 0.5 RD and RD2 = RD +
0.5 RD (RD /RD is small).
A) If v1 = v2 = 0, find Vo = vo2 vo1 (Differential DC voltage at the output).
B) For what values of VOS = v2 v1, the DC output voltage will be zero.
Ignore channel-length modulation.

No amplifier chip can be manufactured with perfect


symmetry. Mis-matches not only affect CMRR but DC
voltages.
Differential DC voltage at the output and the input
offset voltage, VOS , are important specs. Chips
typically include pins for feedback to zero out these
voltages.
Note: v1 and v2 are DC values in this problem, they
can be viewed either as mis-matched bias (and no
signal) and/or signal (but with a matched zero bias).
F. Najmabadi, ECE102, Fall 2012 (21/37)

A)

If v1 = v2 = 0, find Vo = vo2 vo1 (Differential DC voltage at the output):

RD1 = RD 0.5RD & RD 2 = RD + 0.5RD

Since transistors are matched and VGS1 = VGS2


(because v1 = v2 ):
I D1 = I D 2 = 0.5 I o

vo1 = VD1 = VDD RD1 I D1 = VDD 0.5 I o ( RD 0.5RD )


vo 2 = VD 2 = VDD RD 2 I D 2 = VDD 0.5 I o ( RD + 0.5RD )

Vo = vo 2 vo1 = 0.5 I o RD

F. Najmabadi, ECE102, Fall 2012 (22/37)

Output Offset Voltage

B) For what values of VOS = v2 v1, the DC output voltage will be zero.
Ignore channel-length modulation.
Vo = vo 2 vo1 = 0.5 I o RD

Output Offset Voltage

I D1 = I D 2 = 0.5 I o
Method 1: Viewing VOS as the signal.

The bias voltages remain at zero and Vo has the


above value. A differential signal vd = VOS is applied
to the circuit leading to a differential output , vo,d .
We want to find VOS such that vo,d + Vo = 0
v1 = 0.5 VOS and v2 = +0.5 VOS
vo1,d = g m RD1 (0.5VOS ) = +0.5 g m RD1VOS
vo 2,d = g m RD 2 (+0.5VOS ) = 0.5 g m RD 2VOS
vo ,d = vo 2,d vo1,d = 0.5 g mVOS ( RD 2 + RD1 )
vo ,d = 0.5 g mVOS [ RD + RD + RD RD ]
vo ,d = g mVOS RD = Vo
g m RDVOS = 0.5 I o RD
F. Najmabadi, ECE102, Fall 2012 (23/37)

2I D
RDVOS = I D1RD
VOV

Input Offset Voltage


VOS = 0.5VOV 1

RD
RD

Method 2: Viewing VOS as the bias voltage:


2
For: VG1 = VG 2 = 0 I D1 = I D 2 = 0.5 I o = 0.5 nCox (W / L) VOV

Find: VG 2 = +0.5Vos and VG1 = 0.5Vos such that Vo = vo 2 vo1 = 0


I D1 = 0.5 nCox (W / L) (VOV 0.5VOS ) 2
2
0.5 nCox (W / L) (VOV
VOSVOV )
2
(1 VOS / VOV )
= 0.5 nCox (W / L)VOV

Dropping V2OS terms by


assuming VOS << VOV

= 0.5 I o (1 VOS / VOV )

I D 2 = 0.5 nCox (W / L) (VOV + 0.5VOS ) 2 0.5 I o (1 + VOS / VOV )


vo1 = vo 2 VDD RD1 I D1 = VDD RD 2 I D 2
I D1 RD1 = I D 2 RD 2
0.5 I o RD (1 VOS / VOV )(1 0.5RD / RD ) = 0.5 I o RD (1 + VOS / VOV )(1 + 0.5RD / RD )

2(VOS / VOV ) + RD / RD = 0
F. Najmabadi, ECE102, Fall 2012 (24/37)

VOS = 0.5VOV 1

RD
RD

Exercise 9: Consider the circuit below with nCox = 90 A/V2, pCox =


30 A/V2, Vtn = Vpn = 0.7 V and VAn = VAp = 20 V. The circuit is
to operate such that all transistors operate at VOV = 0.5 V, ID1 = ID2 =
ID3 = ID4 = Iref = 0.2 mA, and (W/L )5 = (W/L )6 .
a) Design the circuit (i.e., find (W/L) of all transistors).
b) Find the differential gain.
c) Find the common mode response at vo1 (i.e., vo1/vCM).
d) Find the input common-mode range
e) Find the allowable range of the output voltage.
Ignore channel-length modulation in biasing calculations.

F. Najmabadi, ECE102, Fall 2012 (25/37)

5) Q6: Providing
reference voltage
(or current) for Q5
2) Q5: Biasing current mirror

1) Q1 & Q2: PMOS


Differential
amplifier
3) Q3& Q4: currentsource/active loads
4) Qref: The
reference leg of
current mirror for
the circuit

F. Najmabadi, ECE102, Fall 2012 (26/37)

6) Q7: Providing
Iref for Q6

a) Find (W/L of all transistors)


ID1 = ID2 = ID3 = ID4 = Iref = 0.2 mA,
and (W/L )5 = (W/L )6 .
Step 1: Compute all currents.
I D 5 = I = I D1 + I D 2 = 0.4 mA

I D6 =

(W / L )6 I = 0.4
(W / L )5 D5

mA

I D 7 = I D 6 = 0.4 mA

Step 2: Compute (W/L)s (Vov= 0.5 V)


NMOS: Qref, Q3, Q4, and Q7
2
0.2 10 3 = I ref = 0.5 n Cox (W / L) ref VOV
= 0.5 90 10 -6 (W / L) ref (0.5) 2

(W / L) ref = 17.8
I D 3 = I D 4 = I ref = 0.2 mA (W / L) 3 = (W / L) 4 = (W / L) ref = 17.8
I D 7 = 2 I ref = 0.4 mA (W / L) 7 = 2(W / L) ref = 35.6
F. Najmabadi, ECE102, Fall 2012 (27/37)

PMOS: Q1, Q2, Q5, and Q6


2
0.2 10 3 = I D1 = 0.5 p Cox (W / L)1 VOV
= 0.5 30 10 -6 (W / L)1 (0.5) 2

(W / L)1 = 53.3

I D 2 = I D1 = 0.2 mA (W / L) 2 = (W / L)1 = 53.3

I D 5 = I D 6 = 2 I D1 = 0.4 mA (W / L) 5 = (W / L) 6 = 2(W / L)1 = 107

Small signal parameters:

gm2

2 I D1 2 0.2 10 3
= g m1 =
=
= 8 10 4 A/V
0.5
VOV 1

ro 2 = ro1 =

20
VA1
=
= 100 k
3
I D1 0.2 10

ro 4 = ro 3 =

V A3
20
=
= 100 k
3
I D 3 0.2 10

ro 5 =

V A5
20
=
= 50 k
3
I D 5 0.4 10

F. Najmabadi, ECE102, Fall 2012 (28/37)

b) Find the differential gain:

c) Find common mode response, vo1:

vo1,c

Ad =

vc

vo ,1d
0.5vd

= g m1 (r o1|| ro 3 )

Ad = 8 10 (100k || 100k) = 40

vo1,c
vc
vo 2,c
vc

F. Najmabadi, ECE102, Fall 2012 (29/37)

g m1r o 3
1 + 2 g m1r o 5 + r o 3 / ro1

8 10 4 100 103
=
1 + 2 8 10 4 50 103 + 1
=

vo1,c
vc

80
= 0.98
1 + 80 + 1

d) Find input common mode range:


VS 1 VCM = VOV + | Vtp | = 1.2 V VS 1 = VCM + 1.2

The above equation indicates VS1 changes


and tracks VCM as VCM changes. VS1 is
limited by two criteria below:
1) Q5 in saturation:
VSD 5 = 2.5 VD 5 VOV VS 1 = VD 5 2.5 0.5 = 2 V

2) Q1/Q3 in saturation:
VSD1 VOV 1
VDS 3 VOV 3

VSD1 + VDS 3 VOV + VOV = 1 V


VS 1 (2.5) 1 VS 1 1.5

1.5 VS 1 2.0 V
1.5 VCM + 1.2 2.0 V
2.7 VCM 0.8 V

Note that the requirement on Q1/Q3 in saturation is usually more restrictive than above as Q1/Q3 do
not usually reach saturation together (calculation above represents the best case). However, correct
solution requires that we include channel-length modulation and calculate the relationship between
VSD1 & VDS3 (same arguments apply to part e).
F. Najmabadi, ECE102, Fall 2012 (30/37)

e) Find allowable range of output voltage:

1) Q3 in saturation:
VDS 3 = vo1 (2.5) VOV
vo1 2.5 + 0.5 = 2 V

2) Q1/Q5 in saturation:
VSD1 VOV
VSD 5 VOV

VSD 5 + VSD1 2VOV = 1 V


VSD 5 + VSD1 = 2.5 vo1 1
vo1 1.5 V

F. Najmabadi, ECE102, Fall 2012 (31/37)

2.0 vo1 1.5 V

Exercise 10: Consider the circuit below with nCox = 400 A/V2,
pCox = 100 A/V2, and Vtn = Vpn = 0.4 V. All transistors operate at
VOV = 0.2 V and ID1 = ID2 = ID3 = ID4 = ID6 = Iref = 0.2 mA
a) Design the circuit (i.e., find (W/L) of all transistors)
b) Find the input common-mode range
c) Find the differential gain ( = 0.2 V-1)

F. Najmabadi, ECE102, Fall 2012 (32/37)

5) Q3/Q4: asymmetric
active load for
differential amplifier

2) Q6: PMOS CS
amplifier (2nd stage)

4) Qref: The
reference leg of
current mirror for
the circuit

6) Q7: currentsource/active load for


Q6 CS amplifier
3) Q5: Currentmirror bias for
differential

F. Najmabadi, ECE102, Fall 2012 (33/37)

1) Q1 & Q2: NMOS Differential


amplifier with single-ended
output (1st stage)

a) Find (W/L of all transistors).


Step 1: Compute all currents.
I D1 = I D 2 = I D 3 = I D 4 = I D 6 = I ref = 0.2 mA
I D 5 = I D1 + I D 2 = 0.4 mA
I D 7 = I D 6 = 0.2 mA

Step 2: Compute (W/L)s (Vov= 0.2 V)


NMOS: Qref, Q1, Q2, and Q7 (all have same ID and VOV)
2
0.2 10 3 = I ref = 0.5 n Cox (W / L) ref VOV
(W / L) ref = 25

I D1 = I D 2 = I D 7 = I ref = 0.2 mA (W / L)1 = (W / L) 2 = (W / L) 7 = (W / L) ref = 25


I D 5 = 2 I ref = 0.4 mA (W / L) 5 = 2(W / L) ref = 50

PMOS: Q3, Q4, and Q6 (all have same ID and VOV)


2
0.2 10 3 = I 3 = 0.5 p Cox (W / L) 3 VOV
(W / L) 3 = 100

I D 3 = I D 4 = I D 6 = 0.2 mA (W / L) 3 = (W / L) 4 = (W / L) 6 = 100
F. Najmabadi, ECE102, Fall 2012 (34/37)

b) Find input common mode range:


VCM VS 1 = VGS 1 = VOV + Vtn VS 1 = VCM 0.6 V

Similar to problem 9, we look at VS1 limits:


1) Q5 in saturation:
VDS 5 = VD 5 (1) VOV VS 1 = VD 5 0.2 1 = 0.8 V

2) Q1/Q3 and Q2/Q4 in saturation (because the circuit is NOT symmetric,


we need to consider both cases and choose the most restrictive one).
2A) Q1/Q3

2B) Q2/Q4

VSD 3 = VSG 3 = VOV 3 + | Vtp | = 0.6 V

VSG 6 = VOV 6 + | Vtp | = 0.6 V

VSD 3 = 1 VD 3 VD 3 = 0.4 V = VD1

VSG 6 = 1 VG 6 VG 6 = 0.4 V = VD 2

VDS 1 = VD1 VS 1 = 0.4 VS 1 VOV = 0.2 V

VDS 2 = VD 2 VS 2 = 0.4 VS 1 VOV = 0.2 V

VS 1 0.2 V
0.8 VS 1 0.2 V
F. Najmabadi, ECE102, Fall 2012 (35/37)

VS 1 0.2 V

0.8 VCM 0.6 0.2 V

0.2 VCM 0.6 V

c) Find the differential gain ( = 0.2 V-1):


I D1 = I D 2 = I D 3 = I D 4 = I D 6 = 0.2 mA
I D 5 = I D1 + I D 2 = 0.4 mA
I D 6 = I D 7 = 0.2 mA

gm2

2 I D1 2 0.2 10 3
= g m1 =
=
= 2 10 3 A/V
0.2
VOV 1

ro 2 = ro1 =

1
1
=
= 25 k
3
I D1 0.2 0.2 10

1
1
=
= 25 k
3
I D 3 0.2 0.2 10
1
1
=
= 12.5 k
ro 5 =
3
I D 5 0.2 0.4 10

g m6

2 I D 6 2 0.2 10 3
=
=
= 2 10 3 A/V
0.2
VOV 6

ro 6 =

1
1
=
= 25 k
I D 6 0.2 0.2 10 3

ro 7 =

1
1
=
= 25 k
I D 7 0.2 0.2 10 3

ro 4 = ro 3 =

F. Najmabadi, ECE102, Fall 2012 (36/37)

vx

Q1 & Q2: NMOS Differential


amplifier with single-ended
output (1st stage)

Q6: PMOS CS amplifier


(2nd stage)

vo
= g m 6 (r o 6 || ro 7 )
vx

vx
= g m1 (r o1|| ro 3 || RL )
vd
vx
= 2 10 3 (25k || 25k) = 25
vd

Ad =
F. Najmabadi, ECE102, Fall 2012 (37/37)

vo
= 2 10 3 (25k || 25k) = 25
vx
R i2 =

vo vo v x
= = 25 25 = 625
vd v x vd

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