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TPS51125
SLUS786H OCTOBER 2007 REVISED JANUARY 2015

TPS51125 Dual-Synchronous, Step-Down Controller With Out-of-Audio Operation and

100-mA LDOS for Notebook System Power
1 Features

3 Description

The TPS51125 is a cost-effective, dual-synchronous

buck controller targeted for notebook system power
supply solutions. The device provides 5-V and 3.3-V
LDOs and requires few external components. The
270-kHz VCLK output can be used to drive an
external charge pump, thus generating gate drive
voltage for the load switches without reducing the
efficiency of the main converter. The TPS51125
supports high-efficiency, fast-transient response and
provides a combined power-good signal. Out-ofAudio mode light-load operation enables low acoustic
noise at much higher efficiency than conventional
forced PWM operation. Adaptive on-time D-CAP
control provides convenient and efficient operation.
The part operates with supply input voltages ranging
from 5.5 V to 28 V and supports output voltages from
2 V to 5.5 V. The TPS51125 is available in a 24-pin
QFN package and is specified from -40C to 85C
ambient temperature range.

Wide Input Voltage Range: 5.5 V to 28 V

Output Voltage Range: 2 V to 5.5 V
Built-In 100-mA, 5-V and 3.3-V LDO With
Switches
Built-In 1% 2-V Reference Output
With or Without Out-of-Audio Mode Selectable
Light-Load and PWM-Only Operation
Internal 1.6-ms Voltage Servo Soft-Start
Adaptive On-Time Control Architecture With Four
Selectable Frequency Setting
4500 ppm/C RDS(on) Current Sensing
Built-In Output Discharge
Powergood Output
Built-In OVP/UVP/OCP
Thermal Shutdown (Nonlatch)
QFN, 24-Pin (RGE)

Device Information(1)

2 Applications

PART NUMBER

PACKAGE

TPS51125

Notebook Computers
I/O Supplies
System Power Supplies

BODY SIZE (NOM)

VQFN (24)

4.00 mm x 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Schematic
13 kW

20 kW

20 kW

VIN

30 kW
VIN

220 nF
130 kW

VIN

3.3mH

VFB2

VREF

VFB1

ENTRIP1

VO2

VREG3

PGOOD 23

VBST2

VBST1 22

10 DRVH2

3.3mH

5.1W

PowerPAD

VO1
5V

LL1 20

EN0

SKIPSEL

GND

330mF

13

14

15

12 DRVL2

VREG5
0.1mF

DRVH1 21

DRVL1 19

VIN

11 LL2
330mF

EN0

100 kW

VREG5

3.3 V

VO1 24

TPS51125RGE

5.1W

5.5 V
to
28 V

16

17

18

VCLK

0.1mF

TONSEL

10mF

ENTRIP2

10mF x 2

10mF x 2

VO2

130 kW

VREG5
100 nF
VREF

VIN

33mF

100 nF

15 V

VO1

620 kW
100 nF

100 nF

1mF
UDG-09019

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS51125
SLUS786H OCTOBER 2007 REVISED JANUARY 2015

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Table of Contents
1
2
3
4
5
6

Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6

1
1
1
2
3
5

Absolute Maximum Ratings ..................................... 5

ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 23

8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23

9 Power Supply Recommendations...................... 27

10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28

11 Device and Documentation Support ................. 30

11.1
11.2
11.3
11.4

Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................

30
30
30
30

12 Mechanical, Packaging, and Orderable

Information ........................................................... 30

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2012) to Revision H

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision F (March 2012) to Revision G

Page

Added electrostatic discharge ratings in Absolute Maximum Ratings table. ......................................................................... 5

Changes from Revision E (May 2011) to Revision F

Page

Page

Added Input voltage range parameter, LL1, LL2, pulse width < 20 ns with a value of -5 V to 30 V...................................... 5

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5 Pin Configuration and Functions

VO1

PGOOD

VBST1

DRVH1

LL1

DRVL1

RGE PACKAGE
24 PINS
TOP VIEW

24

23

22

21

20

19

ENTRIP1

18 VCLK

VFB1

17 VREG5

VREF

16 VIN
TPS51125RGE

14 SKIPSEL

ENTRIP2

13 EN0

VO2

10

11

12
DRVL2

LL2

VFB2

DRVH2

15 GND

VBST2

VREG3

TONSEL

Pin Functions
PIN
NAME

NO.

DRVH1

21

DRVH2

10

DRVL1

19

DRVL2

12

ENTRIP1

ENTRIP2

I/O
O
O
I/O

DESCRIPTION
High-side N-channel MOSFET driver outputs. LL referenced drivers.
Low-side N-channel MOSFET driver outputs. GND referenced drivers.
Channel 1 and Channel 2 enable and OCL trip setting pins.Connect resistor from this pin to GND to set
threshold for synchronous RDS(on) sense. Short to ground to shutdown a switcher channel.
Master enable input.
Open : LDOs on, and ready to turn on VCLK and switcher channels.

EN0

13

I/O

620 k to GND : enable both LDOs, VCLK off and ready to turn on switcher channels. Power
consumption is almost the same as the case of VCLK = ON.
GND : disable all circuit

GND

15

LL1

20

LL2

11

PGOOD

23

I
O

Ground.
Switch node connections for high-side drivers, current limit and control circuitry.
Power Good window comparator output for channel 1 and 2. (Logical AND)
Selection pin for operation mode:

SKIPSEL

14

OOA auto skip : Connect to VREG3 or VREG5

Auto skip : Connect to VREF
Auto skip : Connect to VREF
On-time adjustment pin
365 kHz/460 kHz setting : connect to VREG5

TONSEL

300 kHz/375 kHz setting : connect to VREG3

245 kHz/305 kHz setting : connect to VREF
200 kHz/250 kHz setting : connect to GND
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Pin Functions (continued)

PIN
NAME

NO.

VBST1

22

VBST2

VCLK

18

VFB1

VFB2

VIN

16

VO1

24

VO2

VREF

I/O
I
O
I
I

DESCRIPTION
Supply input for high-side N-channel MOSFET driver (boost terminal).
270-kHz clock output for 15-V charge pump.
SMPS feedback inputs. Connect with feedback resistor divider.
High voltage power supply input for 5-V/3.3-V LDO.

I/O

Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge inputs.
VO1 and VO2 also work as 5 V and 3.3 V switch over return power input respectively.

2-V reference voltage output. Connect 220-nF to 1-F ceramic capacitor to Signal GND near the device.

VREG3

3.3-V power supply output. Connect 10-F ceramic capacitor to Power GND near the device. A 1-F
ceramic capacitor is acceptable when not loaded.

VREG5

17

5-V power supply output. Connect 33-F ceramic capacitor to Power GND near the device.

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)

Input voltage (1)

MIN

MAX

VBST1, VBST2

0.3

36

VIN

0.3

30

LL1, LL2

2.0

30

LL1, LL2, pulse width < 20 ns

5.0

30

VBST1, VBST2

Output voltage (1)

(2)

0.3

EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL,

SKIPSEL

0.3

DRVH1, DRVH2

1.0

36

0.3

DRVH1, DRVH2

(2)

PGOOD, VCLK, VREG3, VREG5, VREF, DRVL1, DRVL2

UNIT

0.3

Junction temperature, TJ

40

125

Storage temperature, Tstg

55

150

(1)
(2)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the corresponding LLx terminal.

6.2 ESD Ratings

VALUE
V(ESD)
(1)
(2)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)

2000

Charged-device model (CDM), per JEDEC specification JESD22C101 (2)

1500

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage

Output voltage

VIN

MIN

MAX

5.5

28

VBST1, VBST2

0.1

34

VBST1, VBST2 (with respect to LLx)

0.1

5.5

EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL

0.1

5.5

DRVH1, DRVH2

0.8

34

DRVH1, DRVH2 (with respect to LLx)

0.1

5.5

LL1, LL2

1.8

28

VREF, VREG3, VREG5

0.1

5.5

PGOOD, VCLK, DRVL1, DRVL2

0.1

5.5

40

85

Operating free-air temperature

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6.4 Thermal Information

TPS51125
THERMAL METRIC (1)

VQFN

UNIT

24 PINS
RJA

Junction-to-ambient thermal resistance

34.2

RJC(top)

Junction-to-case (top) thermal resistance

37.2

RJB

Junction-to-board thermal resistance

12.4

JT

Junction-to-top characterization parameter

0.4

JB

Junction-to-board characterization parameter

12.4

RJC(bot)

Junction-to-case (bottom) thermal resistance

2.8

(1)

C/W

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT
IVIN1

VIN supply current1

VIN current, TA = 25C, no load, VO1 = 0 V,

VO2 = 0 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V

0.55

mA

IVIN2

VIN supply current2

VIN current, TA = 25C, no load, VO1 = 5 V,

VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V

6.5

IVO1

VO1 current

VO1 current, TA = 25C, no load, VO1 = 5 V,

VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V

0.8

1.5

mA

IVO2

VO2 current

VO2 current, TA = 25C, no load, VO1 = 5 V,

VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V

12

100

IVINSTBY

VIN standby current

VIN current, TA = 25C, no load,

EN0 = 1.2 V, ENTRIPx = 0 V

95

250

IVINSDN

VIN shutdown current

VIN current, TA = 25C, no load,

EN0 = ENTRIPx = 0 V

10

25

VREF OUTPUT
VVREF

VREF output voltage

IVREF = 0 A

1.98

2.00

2.02

-5 A < IVREF < 100 A

1.97

2.00

2.03

4.8

5.2

4.75

5.25

4. 75

5.25

VO1 = 0 V, VREG5 = 4.5 V

100

175

250

Turns on

4.55

4.7

4.85

Hysteresis

0.15

0.25

0.3

3.2

3.33

3.46

VO2 = 0 V, IVREG3 < 100 mA, 6.5 V < VIN <

28 V

3.13

3.33

3.5

VO2 = 0 V, IVREG3 < 50 mA, 5.5 V < VIN < 28

V

3.13

3.33

3.5

VREG5 OUTPUT
VO1 = 0 V, IVREG5 < 100 mA, TA = 25C
VVREG5

VREG5 output voltage

VO1 = 0 V, IVREG5 < 100 mA, 6.5 V < VIN <

28 V
VO1 = 0 V, IVREG5 < 50 mA, 5.5 V < VIN < 28
V

IVREG5

VREG5 output current

VTH5VSW

Switch over threshold

R5VSW

5 V SW RON

VO1 = 5 V, IVREG5 = 100 mA

mA
V

VREG3 OUTPUT
VO2 = 0 V, IVREG3 < 100 mA, TA= 25C
VVREG3

IVREG3

VREG3 output voltage

VREG3 output current

VTH3VSW

Switch over threshold

R3VSW

3 V SW RON

VO2 = 0 V, VREG3 = 3 V

100

175

250

Turns on

3.05

3.15

3.25

0.1

0.2

0.25

1.5

Hysteresis
VO2 = 3.3 V, IVREG3 = 100 mA

mA
V

INTERNAL REFERENCE VOLTAGE

VIREF

VVFB

Internal reference voltage

VFB regulation voltage

IVREF = 0 A, beginning of ON state

1.95

1.98

2.01

FB voltage, IVREF = 0 A, skip mode

1.98

2.01

2.04

2.00

2.035

2.07

20

nA

FB voltage, IVREF = 0 A, OOA mode

(1)

FB voltage, IVREF = 0 A, continuous

conduction (1)
IVFB
(1)

VFB input current

VFBx = 2.0 V, TA= 25C

2.00
20

Ensured by design. Not production tested.

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Electrical Characteristics (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

10

60

MAX

UNIT

VOUT DISCHARGE
IDischg

VOUT discharge current

ENTRIPx = 0 V, VOx = 0.5 V

mA

OUTPUT DRIVERS
RDRVH

DRVH resistance

RDRVL

DRVL resistance

tD

Dead time

Source, VBSTx - DRVHx = 100 mV

1.5

Sink, VDRVLx = 100 mV

1.5

DRVHx-off to DRVLx-on

10

DRVLx-off to DRVHx-on

30

Sink, VDRVHx - LLx = 100 mV

Source, VVREG5 - DRVLx = 100 mV

ns

CLOCK OUTPUT
VCLKH

High level voltage

IVCLK = -10 mA, VO1 = 5 V, TA = 25 C

VCLKL

Low level voltage

IVCLK = 10 mA, VO1 = 5 V, TA = 25 C

fCLK

Clock frequency

TA = 25 C

4.84

4.92
0.06

0.12

175

270

325

0.7

V
kHz

INTERNAL BST DIODE

VFBST

Forward voltage

VVREG5-VBSTx, IF = 10 mA, TA = 25 C

0.8

0.9

IVBSTLK

VBST leakage current

VBSTx = 34 V, LLx = 28 V, TA = 25 C

0.1

DUTY AND FREQUENCY CONTROL

tON11

CH1 on time 1

VIN = 12 V, VO1 = 5 V, 200 kHz setting

2080

tON12

CH1 on time 2

VIN = 12 V, VO1 = 5 V, 245 kHz setting

1700

tON13

CH1 on time 3

VIN = 12 V, VO1 = 5 V, 300 kHz setting

1390

tON14

CH1 on time 4

VIN = 12 V, VO1 = 5 V, 365 kHz setting

1140

tON21

CH2 on time 1

VIN = 12 V, VO2 = 3.3 V, 250 kHz setting

1100

tON22

CH2 on time 2

VIN = 12 V, VO2 = 3.3 V, 305 kHz setting

900

tON23

CH2 on time 3

VIN = 12 V, VO2 = 3.3 V, 375 kHz setting

730

tON24

CH2 on time 4

VIN = 12 V, VO2 = 3.3 V, 460 kHz setting

600

tON(min)

Minimum on time

TA = 25 C

80

tOFF(min)

Minimum off time

TA = 25 C

300

Internal SS time

Internal soft start

ns

SOFT-START
tSS

1.1

1.6

2.1

ms

POWERGOOD
VTHPG

PG threshold

PG in from lower

92.50%

95%

97.50%

PG in from higher

102.50%

105%

107.50%

2.50%

5%

7.50%

PG hysteresis
IPGMAX

PG sink current

PGOOD = 0.5 V

tPGDEL

PG delay

Delay for PG in

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350

510

mA
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Electrical Characteristics (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC THRESHOLD AND SETTING CONDITIONS

Shutdown
VEN0

EN0 setting voltage

IEN0

EN0 current

VEN

ENTRIP1, ENTRIP2
threshold

0.4

Enable, VCLK = off

0.8

Enable, VCLK = on

2.4

1.6

VEN0 = 0.2 V

3.5

VEN0 = 1.5 V

1.75

2.5

Shutdown

350

400

450

Hysteresis

10

30

60

200 kHz/250 kHz

VTONSEL

TONSEL setting voltage

SKIPSEL setting voltage

A
mV

1.5

245 kHz/305 kHz

1.9

2.1

300 kHz/375 kHz

2.7

3.6

365 kHz/460 kHz

4.7

PWM only
VSKIPSEL

1.5

Auto skip

1.9

OOA auto skip

2.7
9.4

2.1

PROTECTION: CURRENT SENSE

IENTRIP

ENTRIPx source current

VENTRIPx = 920 mV, TA= 25C

TCIENTRIP

ENTRIPx current
temperature coefficient

On the basis of 25C (1)

VOCLoff

OCP comparator offset

((VENTRIPx-GND/9)-24 mV -VGND-LLx) voltage,

VENTRIPx-GND = 920 mV

VOCL(max)

Maximum OCL setting

VENTRIPx = 5 V

VZC

Zero cross detection

comparator offset

VGND-LLx voltage

VENTRIP

Current limit threshold

VENTRIPx-GND voltage,

10
4500

(1)

ppm/C

185

205

225

0.515

10.6

mV

PROTECTION: UNDERVOLTAGE AND OVERVOLTAGE

VOVP

OVP trip threshold

tOVPDEL

OVP prop delay

OVP detect

110%

115%

UVP detect

55%

60%

120%
s

2
65%

VUVP

Output UVP trip threshold

tUVPDEL

Output UVP prop delay

20

32

40

tUVPEN

Output UVP enable delay

1.4

2.6

ms

4.1

4.2

4.3

0.43

0.48

Hysteresis

10%

UVLO
VUVVREG5

VREG5 UVLO threshold

VUVVREG3

VREG3 UVLO threshold

Wake up
Hysteresis
Shutdown

0.38
(1)

VO2-1

THERMAL SHUTDOWN
TSDN

Thermal shutdown threshold

Shutdown temperature
Hysteresis

(1)

(1)

150
10

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800

800

700

700
IVIN1 - VIN Supply Current1 - mA

IVIN1 - VIN Supply Current1 - mA

6.6 Typical Characteristics

600
500
400
300
200
100
0
-50

600
500
400
300
200
100

50

100

150

TJ - Junction Temperature - C

10

15

20

25

V IN - Input Voltage - V

Figure 2. VIN Supply Current1 vs Input Voltage

8
IVIN2 - VIN Supply Current2 - mA

IVIN2 - VIN Supply Current2 - mA

Figure 1. VIN Supply Current1 vs Junction Temperature

7
6
5
4
3
2

7
6
5
4
3
2
1

0
-50

50

100

150

10

Figure 3. VIN Supply Current2 vs Junction Temperature

IVINSTBY VIN Standby Current nA

IVINSTBY - VIN Standby Current - mA

25

250

200

150

100

50

50

200

150

100

50

0
0

50

100

150

TJ - Junction Temperature - C

10

15

20

25

V IN - Input Voltage - V

Figure 5. VIN Standby Current vs Junction Temperature

10

20

Figure 4. VIN Supply Current1 vs Input Voltage

250

15
V IN - Input Voltage - V

T J - Junction Temperature - C

Figure 6. VIN Standby Current vs Input Voltage

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Typical Characteristics (continued)

25

IVINSDN - VIN Shutdown Current - mA

IVINSDN - VIN Shutdown Current

mA-

25

20

15

10

20

15

10

0
-50

50

100

150

10

Figure 7. VIN Shutdown Current vs Junction Temperature

20

25

Figure 8. VIN Shutdown Current vs Input Voltage

14

325

13

300
f CLK - VCLK Frequency - kHz

IENTRIP - Current Sense Current - mA

15

V IN - Input Voltage - V

T J - Junction Temperature - C

12
11
10
9
8

275

250

225

200
7

175
-50

6
T J - Junction Temperature - C

0
50
100
T J - Junction Temperature - C

Figure 9. Current Sense Current vs Junction Temperature

Figure 10. VCLK Frequency vs Junction Temperature

-50

50

100

150

500

500

TONSEL = 2V

f SW - Swithching Frequency - kHz

TONSEL = GND

fSW - Swithching Frequency - kHz

150

400

300
CH2

200
CH1
100

400

CH2
300

CH1

200

100

10

12

14

16

18

20

22

24

26

V IN - Input Voltage - V

10

12

14

16

18

20

22

24

26

V IN - Input Voltage - V

Figure 11. Switching Frequency vs Input Voltage

Figure 12. Switching Frequency vs Input Voltage

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Typical Characteristics (continued)

500

500

CH2

400

f SW - Swithching Frequency - kHz

f SW - Swithching Frequency - kHz

TONSEL = 3.3V

300
CH1
200

100

CH1
300

200

100

10

12

14

16

18

20

22

24

26

10

V IN - Input Voltage - V

12

14

16

24

26

f SW - Swithching Frequency - kHz

TONSEL = 2V

400

300
CH2 PWM Only
200
CH1 PWM Only
100

CH2 Auto-skip
CH2 OOA

400

CH2 PWM Only

300

200

CH1 PWM Only

CH2 Auto-skip

100

CH1 OOA

CH2 OOA
CH1 OOA

CH1 Auto-skip
0
0.001

0.01

0.1

CH1 Auto-skip
0
0.001

10

0.01

IOUT - Output Current - A

0.1

10

IOUT - Output Current - A

Figure 15. Switching Frequency vs Output Current

Figure 16. Switching Frequency vs Output Current

500

500

TONSEL = 3.3V

TONSEL = 5V

f SW - Swithching Frequency - kHz

f SW - Swithching Frequency - kHz

22

500
TONSEL = GND

CH2 PWM Only

300
CH1 PWM Only
200
CH2 Auto-skip

100

CH2 OOA

400

CH2 PWM Only

CH1 PWM Only

300

200
CH2 Auto-skip
CH2 OOA

100

CH1 OOA

CH1 OOA

CH1 Auto-skip

CH1 Auto-skip
0
0.001

12

20

Figure 14. Switching Frequency vs Input Voltage

500

400

18

V IN - Input Voltage - V

Figure 13. Switching Frequency vs Input Voltage

f SW - Swithching Frequency - kHz

CH2

TONSEL = 5V

400

0.01

0.1

0
0.001

10

0.01

0.1

10

IOUT - Output Current - A

IOUT - Output Current - A

Figure 17. Switching Frequency vs Output Current

Figure 18. Switching Frequency vs Output Current

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Typical Characteristics (continued)

150

5.05

V VREG5 - VREG5 Output Voltage - V

V OVP/VUVP - OVP/UVP Threshold - %

140
130
120
110
100
90
80
70
60

5.00

4.95

50

4.90

40
-50

0
TJ

50
100
- Junction Temperature - C

150

20

40

60

80

100

IVREG5 - VREG5 Output Current - m A

Figure 19. OVP/UVP Threshold Voltage vs Junction

Temperature

Figure 20. VREG5 Output Voltage vs Output Current

3.35

2.020

V VREF - VREF Output Voltage - V

VVREG3- VREG3 Output Voltage - V

2.015

3.3

3.25

2.010
2.005
2.000
1.995
1.990
1.985
1.980

3.2
0

20

40

60

80

100

20

Figure 21. VREG5 Output Voltage vs Output Current

100

OOA

OOA
V OUT2 - 3.3-V Output Voltage - V

V OUT1 - 5-V Output Voltage - V

80

3.360

5.050

5.000

60

Figure 22. VREG5 Output Voltage vs Output Current

5.075

5.025

40

IVREF - VREF Output Currentm-A

IVREG3 - VREG3 Output Current - m A

Auto-skip

PWM Only

4.975

4.950
0.001

0.01

0.1

10

3.330
Auto-skip
3.300
PWM Only

3.270

3.240
0.001

0.01

0.1

10

IOUT1 - 5-V Output Current - A

IOUT2 - 3.3-V Output Current - A

Figure 23. 5-V Output Voltage vs Output Current

Figure 24. 3.3-V Output Voltage vs Output Current

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Typical Characteristics (continued)

3.360

5.050

V OUT2 - 3.3-V Output Voltage - V

V OUT1 - 5-V Output Voltage - V

5.075

IO = 0A

5.025

5.000
IO = 6A
4.975

4.950

3.330
IO = 0A
3.300
IO = 6A

3.270

3.240

10

12

14

16

18

20

22

24

26

10

14

16

18

20

22

24

26

V IN - Input Voltage - V

Figure 25. 5-V Output Voltage vs Input Voltage

Figure 26. 3.3-V Output Voltage vs Input Voltage

100

100

Auto-skip

VIN=8V
60
VIN=12V
VIN=20V
40

20

Auto-skip

80

h- Efficiency - %

h- Efficiency - %

80

OOA

VIN=8V

60

VIN=12V
40

VIN=20V

20

OOA

PWM Only
0
0.001

0.01

PWM Only
0.1

0
0.001

10

0.01

0.1

5-V Switcher ON
1

10

IOUT2 - 3.3-V Output Current - A

IOUT1 - 5-V Output Current - A

Figure 27. 5-V Efficiency vs Output Current

14

12

V IN - Input Voltage - V

Figure 28. 3.3-V Efficiency vs Output Current

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7 Detailed Description
7.1 Overview
The TPS51125 is a cost-effective, dual-synchronous buck controller targeted for notebook system-power supply
solutions. It provides 5 V and 3.3 V LDOs and requires few external components. With D-CAP control mode
implemented, compensation network can be removed. Besides, the fast transient response also reduced the
output capacitance.

7.2 Functional Block Diagram

Figure 29. TPS51125 Functional Block Diagram

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Functional Block Diagram (continued)

Figure 30. Switcher Controller Block

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7.3 Feature Description

7.3.1 PWM Operations
The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width
modulation (PWM) controller. It supports a proprietary D-CAP mode. D-CAP mode does not require external
compensation circuit and is suitable for low external component count configuration when used with appropriate
amount of ESR at the output capacitor(s).
At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET
is turned off, or becomes OFF state, after internal one-shot timer expires. This one shot is determined by VIN and
VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control. The
MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal 2-V
reference. The inductor current information is also monitored and should be below the overcurrent threshold to
initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The
synchronous bottom or the rectifying MOSFET is turned on at the beginning of each OFF state to keep the
conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching
cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this
enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is
kept over broad range of load current.
7.3.2 Adaptive On-Time Control and PWM Frequency
TPS51125 does not have a dedicated oscillator onboard. However, the part runs with pseudo-constant frequency
by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is controlled inverse
proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as
VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal connection as
Table 1.
Table 1. Tonsel Connection and Switching Frequency
TONSEL CONNECTION

SWITCHING FREQUENCY
CH1

CH2

GND

200 kHz

250 kHz

VREF

245 kHz

305 kHz

VREG3

300 kHz

375 kHz

VREG5

365 kHz

460 kHz

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7.3.3 Loop Compensation

From small-signal loop analysis, a buck converter using D-CAPTM mode can be simplified as shown in Figure 31.

VIN
R1

DRVH
PWM

VFB

+
+

R2

Control
logic
&
Driver

Lx

Ic

IL

DRVL

Io

2V
ESR
Vc

Voltage Divider

RL

Switching Modulator
Co
Output Capacitor

Figure 31. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high
enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the
0dB frequency, f0, defined below need to be lower than 1/4 of the switching frequency.
f0 =

f
1
SW
2p ESR CO
4

(1)

As f0 is determined solely by the characteristics of the output capacitor, loop stability of D-CAP mode is
determined by the chemistry of the capacitor. For example, specialty polymer capacitors (SP-CAP) have Co in
the order of several 100 F and ESR in range of 10 m. These will make f0 in the order of 100 kHz or less and
the loop will be stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this
operational mode.
7.3.4 Ramp Signal
The TPS51125 adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in
the previous section, the feedback voltage is compared with the reference information to keep the output voltage
in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle
is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with
20 mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in steady state. By using this
scheme, the TPS51125 improve jitter performance without sacrificing the reference accuracy.
7.3.5 Light-Load Condition in Auto-Skip Operation
The TPS51125 automatically reduces switching frequency at light-load conditions to maintain high efficiency.
This reduction of frequency is achieved smoothly and without increase of VOUT ripple. Detail operation is
described as follows. As the output current decreases from heavy load condition, the inductor current is also
reduced and eventually comes to the point that its valley touches zero current, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero
inductor current is detected. As the load current further decreased, the converter runs in discontinuous

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conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next
ON cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current
increase from light load to heavy load, switching frequency increases to the preset value as the inductor current
reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (that is, the
threshold between continuous and discontinuous conduction mode) can be calculated as follows;
IOUT(LL) =

1
2Lf

(VIN - VOUT ) VOUT

VIN

where

f is the PWM switching frequency

(2)

Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportional to the output current from the IOUT(LL) given above. For example, it will be 60 kHz
at IOUT(LL)/5 if the frequency setting is 300 kHz.
7.3.6

Out-of-Audio Light-Load Operation

Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion
efficiency. When the Out-of-Audio operation is selected, OOA control circuit monitors the states of both MOSFET
and force to change into the ON state if both of MOSFETs are off for more than 32 s. This means that the top
MOSFET is turned on even if the output voltage is higher than the target value so that the output capacitor is
tends to be overcharged.
The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output
voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation.
7.3.7 VREG5/VREG3 Linear Regulators
There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5
serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers.
The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.
Add a ceramic capacitor with a value of at least 33 F and place it close to the VREG5 pin, and add at most 10
F to the VREG3 pin. Total capacitance connected to the VREG3 pin should not exceed 10 F.
7.3.8 VREG5 Switch Over
When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal
5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The
510-s powergood delay helps a switch over without glitch.
7.3.9 VREG3 Switch Over
When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated,
internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over
MOSFET. The 510-s powergood delay helps a switch over without glitch.
7.3.10 Powergood
The TPS51125 has one powergood output that indicates 'high' when both switcher outputs are within the targets
(AND gated). The powergood function is activated with 2-ms internal delay after ENTRIPx goes high. If the
output voltage becomes within +/-5% of the target value, internal comparators detect power good state and the
powergood signal becomes high after 510-s internal delay. Therefore PGOOD goes high around 2.5 ms after
ENTRIPx goes high. If the output voltage goes outside of +/-10% of the target value, the powergood signal
becomes low after 2-s internal delay. The powergood output is an open-drain output and is needed to be pulled
up outside.
Also note that, in the case of Auto-skip or Out-of-Audio mode, if the output voltage goes +10% above the
target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the
low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and
the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-Audio mode.
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7.3.11 Output Discharge Control

When ENTRIPx is low, the TPS51125 discharges outputs using internal MOSFET which is connected to VOx
and GND. The current capability of these MOSFETs is limited to discharge slowly.
7.3.12 Low-Side Driver
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFETs. The drive capability is
represented by its internal resistance, which are 4 for VREG5 to DRVLx and 1.5 for DRVLx to GND. A dead
time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and
bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous
drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current
is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the highside gate drive current times 5 V makes the driving power which need to be dissipated from TPS51125 package.
7.3.13 High-Side Driver
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFETs. When configured as a
floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by
the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are
4 for VBSTx to DRVHx and 1.5 for DRVHx to LLx.
7.3.14 VCLK for Charge Pump
270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock
signal becomes available when EN0 becomes higher than 2.4 V or open state. Example of control circuit is
shown in Figure 32. Note that the clock driver uses VO1 as its power supply. Regardless of enable or disable of
VCLK, power consumption of the TPS51125 is almost the same. Therefore even if VCLK is not used, one can let
EN0 pin open or supply logic high, as shown in Figure 32, and let VCLK pin open. This approach further
reduces the external part count.
3.3V
TPS51125

TPS51125

EN0

EN0
Control
Input

13

13

GND

GND

Control
Input

15

15

(a) Control by MOSFET switch

(b) Control by Logic

Figure 32. Control Example of EN0 Master Enable

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VCLK 18

100nF

100nF

VO1 (5V)
D0

D1

100nF

PGND

D2

15V/10mA

D4

100nF

PGND

1uF

PGND

Figure 33. 15-V / 10-mA Charge Pump Configuration

7.3.15 Current Protection
TPS51125 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF
state and the controller keeps the OFF state during the inductor current is larger than the over current trip level.
In order to provide both good accuracy and cost effective solution, TPS51125 supports temperature
compensated MOSFET RDS(on) sensing. ENTRIPx pin should be connected to GND through the trip voltage
setting resistor, RTRIP. ENTRIPx terminal sources ITRIP current, which is 10 A typically at room temperature, and
the trip level is set to the OCL trip voltage VTRIP as below. Note that the VTRIP is limited up to about 205 mV
internally.
VTRIP (mV ) =

RTRIP (kW ) ITRIP (mA )

9

- 24 (mV )
(3)

External leakage current to ENTRIPx pin should be minimized to obtain accurate OCL trip voltage.
The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be
connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/C temperature slope to
compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so
that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom
MOSFET.
As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load
current at over current threshold, IOCP, can be calculated in Equation 4.
IOCP =

(VIN - VOUT ) VOUT

VTRIP
I
V
1
+ RIPPLE = TRIP +

RDS(on )
2
RDS(on ) 2 L f
VIN

(4)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and
shutdown both channels.
7.3.16 Overvoltage and Undervoltage Protection
TPS51125 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback
voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit
latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

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Also, TPS51125 monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51125 turns off the
top MOSFET driver.
When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 32 s, TPS51125 latches OFF both top and
bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after 2 ms
following ENTRIPx has become high.
7.3.17 UVLO Protection
TPS51125 has VREG5 undervoltage lockout protection (UVLO). When the VREG5 voltage is lower than UVLO
threshold voltage both switch mode power supplies are shut off. This is nonlatch protection. When the VREG3
voltage is lower than (VO2 - 1 V), both switch mode power supplies are also shut off.
7.3.18 Thermal Shutdown
TPS51125 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150C),
TPS51125 is shut off including LDOs. This is nonlatch protection.

7.4 Device Functional Modes

7.4.1 Enable and Soft-Start
EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those
three regulators and minimize the shutdown supply current to 10 A. Pulling this node up to 3.3 V or 5 V will turn
the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become
ready to enable at this standby mode. The TPS51125 has an internal, 1.6 ms, voltage servo softstart for each
channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV,
an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output
voltage is maintained during start up. As TPS51125 shares one DAC with both channels, if ENTRIPx pin
becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed
until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable
threshold voltage at a same time (within 60 s), both channels start up at same time.
Table 2. Enabling State

22

EN0

ENTRIP1

ENTRIP2

VREF

VREG5

VREG3

CH1

CH2

VCLK

GND

Dont Care

Dont Care

Off

Off

Off

Off

Off

Off

R to GND

Off

Off

On

On

On

Off

Off

Off

R to GND

On

Off

On

On

On

On

Off

Off

R to GND

Off

On

On

On

On

Off

On

Off

R to GND

On

On

On

On

On

On

On

Off

Open

Off

Off

On

On

On

Off

Off

Off

Open

On

Off

On

On

On

On

Off

On

Open

Off

On

On

On

On

Off

On

Off

Open

On

On

On

On

On

On

On

On

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS51125 is typically used as a dual-synchronous buck controller, which convert an input voltage ranging
from 5.5 V to 28 V, to output voltage 5 V and 3.3 V respectively, targeted for notebook system-power supply
solutions.

8.2 Typical Application

SGND
R1
13kW

R2
20kW

C6
0.22mF

R5
130kW

3.3V/100mA

R4
30kW

R3
20kW

SGND

R6
130kW
SGND

VREF

VF
B1

VIN

VIN
5.5 ~ 28V

RI
P1

EN
T

3
VR
E

EL

VF
B2

7 VO2

4
TO
NS

C2
10mF

VO1

24

8 VREG3

PGOOD

23

PGND

9 VBST2

VBST1

22

VREG5
PGND

PGND
Q1
IRF7821

C4
0.1mF

C9
10mF

C8
10mF
R8
100kW

C3
10mF

L1
3.3mH

EN
T

C1
10mF

6
RI
P2

VIN

R7
5.1W

C7
0.1mF

R9
5.1W

TPS51125RGE
(QFN24)
10 DRVH2

DRVH1

21

LL1

20

Q3
IRF7821

L2
3.3mH

VO2
3.3V/8A
11 LL2

VIN

VR
E

VC
LK

13

14

15

16

17

18

G5
GN

PGND

DRVL1

SK
IPS
EL

12 DRVL2

VO2_GND
PGND

PowerPAD

VO1
5V/8A

Q2
FDS6690AS

EN
0

C5
POSCAP
330mF

Q4
FDS6690AS

19

C10
POSCAP
330mF

VO1_GND
PGND

PGND

SGND

VREG5

EN0

5V/100mA
S1
C11
33mF

R10
620kW

SGND

PGND

C13
100nF

D1

VO1

VREF

D3

C15
100nF
15V/10mA

C12
100nF

PGND

D4

D2
C14
100nF

C16
1uF
PGND

Figure 34. 5-V/8-A, 3.3-V/8-A Application Circuit (245-kHz/305-kHz Setting)

8.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER

VALUE

Input voltage range

5.5 V to 28 V

Channel 1 output voltage

5V

Channel 1 output current

8A

Channel 2 output voltage

3.3 V

Channel 2 output current

8A

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8.2.2 Detailed Design Procedure

Table 4. List of Materials for 5-V / 8-A, 3.3-V / 8-A Application Circuit
SYMBOL

SPECIFICATION

MANUFACTURER

PART NUMBER
TMK325BJ106MM

C1, C2, C8, C9

10 F, 25 V

Taiyo Yuden

C3

10 F, 6.3 V

TDK

C2012X5R0J106K

C11

33 F, 6.3 V

TDK

C3216X5RBJ336M

C5, C10

330 F, 6.3 V, 25 m

Sanyo

6TPE330ML

L1, L2

3.3 H, 15.6 A, 5.92

m

TOKO

FDA1055-3R3M

30 V, 9.5 m

IR

IRF7821

30 V, 12 m

Fairchild

FDS6690AS

Q1, Q3
Q2, Q4
(1)

(1)

Please use MOSFET with integrated Schottky barrier diode (SBD) for low side, or add SBD in parallel
with normal MOSFET.

8.2.2.1 Determine Output Voltage

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 31. R1 is
connected between VFBx pin and the output, and R2 is connected betwen the VFBx pin and GND.
Recommended R2 value is from 10 k to 20 k. Determine R1 using equation as below.
R1 =

(VOUT - 2.0 ) R2
2.0

(5)

8.2.2.2 Choose the Inductor

The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable
operation.
L=

1
IIND(ripple ) f

(V

IN(max ) - VOUT

) V

OUT

VIN(max )

3
IOUT(max ) f

(V

IN(max ) - VOUT

VIN(max )

) V

OUT

(6)

The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as follows.
IIND(peak ) =

VTRIP
RDS (on )

1
Lf

(V

IN(max )

- VOUT

) V

OUT

VIN(max )

(7)

8.2.2.3 Choose the Output Capacitors

Organic semiconductor capacitors or specialty polymer capacitors are recommended. Determine ESR to meet
required ripple voltage. A quick approximation is as shown in Equation 8.
ESR =

VOUT 20 (mV ) (1 - D )
2 (V ) IRIPPLE

20 (mV ) L f
2 (V )

where

D is the duty cycle

the required output ripple slope is approximately 20 mV per tSW (switching period) in terms of VFB terminal
voltage
(8)

8.2.2.4 Choose the Low-Side MOSFET

It is highly recommended that the low-side MOSFET should have an integrated Schottky barrier diode, or an
external Schottky barrier diode in parallel to achieve stable operation.
24

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8.2.3 Application Curves

VOUT2 (100mV/div)

VOUT1 (100mV/div)

IIND (5A/div)

IIND (5A/div)

IOUT2 (5A/div)

IOUT1 (5A/div)

Figure 35. 5-V Load Transient Response

Figure 36. 3.3-V Load Transient Response

ENTRIP2 (2V/div)

ENTRIP1 (2V/div)

VOUT1 (2V/div)
VOUT2 (2V/div)

PGOOD (5V/div)

PGOOD (5V/div)

Figure 37. 5-V Start-up Waveforms

VREG5 (200mV/div)

Figure 38. 3.3-V Start-up Waveforms

VREG3 (200mV/div)

VOUT2 (200mV/div)

VOUT1 (200mV/div)

Figure 39. 5-V Switchover Waveforms

Figure 40. 3.3-V Switchover Waveforms

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ENTRIP1 (5V/div)

VOUT1 (2V/div)

PGOOD (5V/div)

DRVL1 (5V/div)

Figure 41. 5-V Soft-Stop Waveforms

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ENTRIP2 (5V/div)

VOUT2 (2V/div)

PGOOD (5V/div)

DRVL2 (5V/div)

Figure 42. 3.3-V Soft-Stop Waveforms

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9 Power Supply Recommendations

The TPS51125 is designed to operate from input supply voltage in the range of 5.5 V to 28 V, make sure power
supply voltage in this range.

10 Layout
10.1 Layout Guidelines
Consider these points before starting layout work using the TPS51125.
TPS51125 has only one GND pin and special care of GND trace design makes operation stable, especially
when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF
capacitor as close as possible, connect them to an inner GND plane with PowerPad, overcurrent setting
resistor, EN0 pull-down resistor and EN0 bypass capacitor as shown in the thin GND line of Figure 43. This
trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and
source of low-side MOSFETs as close as possible, and connect them to another inner GND plane with GND
pin of the device, GND terminal of VREG3 and VREG5 capacitors and 15-V charge-pump circuit as shown in
the bold GND line of Figure 43. This trace is named Power Ground (PGND). SGND should be connected to
PGND at the middle point between ground terminal of VOUT capacitors.
Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be
placed on one side of the PCB (solder side). Power components of each channel should be at the same
distance from the TPS51125. Other small signal parts should be placed on another side (component side).
Inner GND planes above should shield and isolate the small signal traces from noisy power lines.
PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET
and high-voltage side of the inductor, should be as short and wide as possible.
VREG5 requires capacitance of at least 33 F and VREG3 requires capacitance of at most 10 F. VREF
requires a 220-nF ceramic bypass capacitor which should be placed close to the device and traces should be
no longer than 10 mm.
Connect the overcurrent setting resistors from ENTRIPx to SGND and close to the device, right next to the
device if possible.
The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output
voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3
is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just
monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the
device. Place on the component side and avoid vias between this resistor and the device.
Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, ENTRIPx, PGOOD,
TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx,
DRVHx and VCLK nodes to avoid coupling.
Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel
interference.
In order to effectively remove heat from the package, prepare thermal land and solder to the packages
thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land
to the internal ground plane should be used to help dissipation. This thermal land underneath the package
should be connected to SGND, and should NOT be connected to PGND.

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10.2 Layout Example

SGND

VIN

VIN
220 nF

VOUT2

VFB2

VREF

VFB1

DRVL2

VOUT1

DRVL1

12

19
TPS51125

PGND

VREG5

PowerPAD
17

GND VREG3
15

33 mF

PGND

15 V
OUT

10 mF
VCLK

Charge
Pump

SGND

UDG-09020

Figure 43. Ground System

28

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Layout Example (continued)

*
CH1 Vout divider

Driver and switch node traces are shown for CH1 only.

TPS51125

Top Layer

DRVH1*
LL1*

CVREF

DRVL1*

CVREG5
CH2 Vout divider

Connection to GND island

Connection to GND
Connection of Vout
Through hole

Connection to
GND island

CVREG3

Inner Layer
GND
GND island

Cout

HS-MOSFET

Vout1

To CH1 Vout divider

LS-MOSFET
To VO1
Cin

VIN

GND

To VO2

Cin

Vout2

To CH2 Vout divider

HS-MOSFET

L
Cout

Bottom Layer

LS-MOSFET

Figure 44. PCB Layout

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Trademarks
D-CAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TPS51125RGER

VQFN

RGE

24

3000

330.0

12.4

4.25

4.25

1.15

8.0

12.0

Q2

TPS51125RGET

VQFN

RGE

24

250

180.0

12.4

4.25

4.25

1.15

8.0

12.0

Q2

TPS51125RGET

VQFN

RGE

24

250

180.0

12.4

4.25

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2014

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

TPS51125RGER

VQFN

RGE

24

3000

367.0

367.0

35.0

TPS51125RGET

VQFN

RGE

24

250

210.0

185.0

35.0

TPS51125RGET

VQFN

RGE

24

250

210.0

185.0

35.0

Pack Materials-Page 2

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