DEPARTMENT

OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

VLSI Laboratory
The students are required to design the schematic diagrams using CMOS logic and to
draw the layout diagrams to perform the following experiments using CMOS 130nm
Technology with necessary EDA tools (Mentor Graphics/Tanner).

List of Experiments:
1. Design and implementation of an inverter
2. Design and implementation of universal gates
3. Design and implementation of full adder
4. Design and implementation of full subtractor
5. Design and implementation of RS-latch
6. Design and implementation of D-latch
7. Design and implementation asynchronous counter
8. Design and Implementation of static RAM cell
9. Design and Implementation of differential amplifier
10. Design and Implementation of ring oscillator

Equipment Required:
1. Microwind3.1 and DSCH3 software-latest version
2. Personal computer with necessary peripherals.

DSCH3
DSCH is software for logic design. Based on primitives, a hierarchical circuit can be
built and simulated. It also includes delay and power consumption evaluation. With the help
of this software one can implement digital circuits at its basic gate primitives or at its
transistor level.
The following step by step procedure gives you how to use this software to implement
circuits at transistor level.
1. To open the software double click on the DSCH3 icon on your desktop

It opens the default window as shown below

2. To design the circuit, select the necessary components which are shown in symbol
library on right hand side and drag and drop on the work area, use buttons for input
and LED for output and also insert VDD and GND which are also part of symbol
library as shown below.

3. Made the interconnections as per the circuit diagram using add a line option

4. Now to observe the functionality of the circuit, run simulation using this icon

When LED glow, it indicates a high output, thats what the functionality of inverter
with low input it produces a high output, we can change the input to high also which
produces a low output as shown below.

5. We can also obtain the response in wave forms also, after completion of simulation
click on this icon

After successful completion of circuit design, we will go for layout

Microwind 3.1
Microwind is a tool for designing and simulating circuits at layout level. The tool features
full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics,
2D cross section, 3D process viewer), and an analog simulator.

1. To open the software double click on the microwind31 icon on your desktop

It opens the default window as shown below

On the right hand side it contains all the necessary layers used in layout design under palette
window.

2. Before start designing the layout, select the design rule file as follows, flieselect
foundrychoose default.rul

3. To design an inverter we need two transistors NMOS and PMOS, a MOS transistor is
formed when a poly silicon layer is crossed with diffusion layer

4. The ploy silicon layer indicates gate terminal, where the diffusion layer ends acts as
source and drain which are interchangeable.
Now the interconnections can be completed by using metal1 layer as shown

5. Now to join different layers use contact cuts, as given in palette window.

6. Now add input to ploy layer, by choosing add pulse, for output add a visible node at
drain-drain contact metal layer as shown below

7. Now run the simulation by using the icon

LAYOUT DESIGN RULES

Minimum width
Between wells
Minimum well Area

10
10
144 2

Diffusion
r201

Minimum N+ and P+ diffusion width

r202

Between two P+ and N+ diffusions

r203

Extra N-well after P+ diffusion

r204

Between N+ diffusion and n-well

r210

Minimum diffusion area

162

Polysilicon
r301

Polysilicon Width

r302

Polysilicon gate on Diffusion

r307

Extra Polysilicon surrounding Diffusion 3

r304

Between two Polysilicon boxes

Contact
r401

Contact width

r403

Extra diffusion surrounding contact

r404

Extra Poly surrounding contact

r405

Extra metal surrounding contact

r501

Between two Metals

r510

Minimum Metal area

162

Metal

Experiment 1
CMOS INVERTER
AIM: To design and implement the layout of CMOS inverter
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
LOGIC SYMBOL & TRUTH TABLE:

CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:

Experiment 2
UNIVERSAL GATES
AIM: Design and Implementation of Universal Gates
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
LOGIC SYMBOL, CMOS CIRCUIT DIAGRAM, TRUTH TABLE:

DSCH3 SCHEMATIC:
NAND

NOR

MICROWIND3.1 LAYOUT:
NAND

DSCH3 SCHEMATIC SIMULATION:

NOR

NOR

MICROWIND3.1 LAYOUT SIMULATION:

NOR

RESULT:

Exercise 1
BASIC GATES
AIM: Design and Implementation of Basic Gates (AND, OR, EX-OR)
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
LOGIC SYMBOL & TRUTH TABLE:

CMOS CIRCUIT DIAGRAM (AND GATE):

DSCH3 SCHEMATIC (AND GATE):

MICROWIND3.1 LAYOUT (AND GATE):

DSCH3 SCHEMATIC SIMULATION (AND GATE):

MICROWIND3.1 LAYOUT SIMULATION (AND GATE):

LOGIC SYMBOL & TRUTH TABLE:

CMOS CIRCUIT DIAGRAM (OR GATE):

DSCH3 SCHEMATIC (OR GATE):

MICROWIND3.1 LAYOUT (OR GATE):

DSCH3 SCHEMATIC SIMULATION (OR GATE):

MICROWIND3.1 LAYOUT SIMULATION (OR GATE):

LOGIC SYMBOL & TRUTH TABLE:

CMOS CIRCUIT DIAGRAM (EX-OR GATE):

DSCH3 SCHEMATIC (EX-OR GATE):

MICROWIND3.1 LAYOUT (EX-OR GATE):

DSCH3 SCHEMATIC SIMULATION (EX-OR GATE):

MICROWIND3.1 LAYOUT SIMULATION (EX-OR GATE):

RESULT:

Exercise 2
HALF ADDER
AIM: To design and implement the layout of half adder
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:
OUTPU
INPUTS
TS
A
B
CARRY
0
0
0
0
1
0
1
0
0
1
1
1

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 3
FULL ADDER
AIM: To design and implement the layout of full adder
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 4
FULL SUBTRACTOR
AIM: To design and implement the layout of full subtractor
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 5
RS LATCH
AIM: To design and implement the layout of RS-Latch
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 6
D LATCH
AIM: To design and implement the layout of D-Latch
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 7
ASYNCHRONOUS COUNTER
AIM: To design and implement the layout of asynchronous counter
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 8
STATIC RAM CELL
AIM: To design and implement the layout of Static RAM Cell
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 9
DIFFERENTIAL AMPLIFIER
AIM: To design and implement the layout of Differential Amplifier
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT:
Experiment 10
RING OSCILLATOR
AIM: To design and implement the layout of Ring Oscillator
SOFTWARE TOOLS:
DSCH3 (Schematic Editor)
MICROWIND3.1 (Layout Editor)
CMOS CIRCUIT DIAGRAM:

DSCH3 SCHEMATIC:

MICROWIND3.1 LAYOUT:

DSCH3 SCHEMATIC SIMULATION:

MICROWIND3.1 LAYOUT SIMULATION:

RESULT: