ni.

com

LabVIEW FPGA Programming Best Practices

Presented by:
Zach Hawkins, Software Developer, Averna
CLA, CPI
ni.com

Agenda

About Averna

Things to Keep in Mind

Structure

Style

Naming Conventions and Designs

Standardization

Project Organization, Reuse and Portability

Synchronization and Multi-FPGA Systems

Summary
Q&A

ni.com

33

Averna at a Glance
Test Engineering Solutions

300
Employees

30+

5
Locations

1250

Custom test solutions, turnkey ATE

Professional Services
Special on-site technical or consulting
expertise for client project teams

Global Support
Completed
Projects

Substantial LabVIEW, FPGA,

Test-system and logistics support

R&D Staff

Test Instruments
Tools to accelerate your DOCSIS,
RF and multimedia device testing

Over 65 NI-certified
architects, developers
and instructors

Industry-leading RF,
GPS/GNSS,
optics/photonics
and multimedia experts

Our Industries

AEROSPACE
& DEFENSE

AUTOMOTIVE &
TRANSPORTATION

CONSUMER
ELECTRONICS

LIFE
SCIENCES

Multi-industry expertise allows us to leverage best practices to

Visit us in
Booth #203.

TELECOM
INFRASTRUCTURE

Things to Keep in Mind

If the code fits onto the FPGA, it fits!

Know that ~70% means its full

You may need to optimize later if/when new features are added

We dont believe in complexity for the sake of complexity

We almost exclusively use the SCTL

Some targets have IO nodes that will prevent using them inside SCTLs

NI has a course for this: High Throughput LabVIEW FPGA

Remember that the determinism of hardware is your friend

ni.com

Well, most of the time

66

Structure: Project Organization

Setup for test-benching

Two high-level testing categories

On-chip testing
Off-chip testing

Requirements

ni.com

FPGA code
Host code
Shared code
Testing code

77

Structure: Project Organization

Reuse and portability

How can we write FPGA code that can just be dropped into a new
project?

What if the code has configuration items?

ni.com

Use the Register Bus!

88

Style: Naming Conventions & Project Organization

<Module>_FPGA

<Module>_Host

API VIs

<Module>_Shared

<Module>.vi
CreateResources.vi (Register Bus optional)
Registers.vi (Register Bus optional)

Resources.ctl (Register Bus optional)

FPGA_<Test/Module/Main>
Model_<Module/Algorithm>
Test_<TestName>

ni.com

99

Style: Designs State Machine

Makes code easier to read and follow

Normally, we would put all the logic in the case structure

Have you ever tried to implement a state machine in pure logic? We have

On an FPGA, additional enable chain logic is added to know which state is active

Think of it more as a State Controller

Only state control logic is necessary

Use handshaking to control logic that gets placed outside the case structure

Remember that each new case can cause a new MUX to be added in
the HW implementation

ni.com

10
10

Style: Designs State Controller

ni.com

11
11

Ever Seen Something Like This Before?

Solved with the Register Bus!

ni.com

12
12

Style: Designs Register Bus

Controls and indicators get implemented as MMRAs

Configuration data will come down from the host on a single DMA
channel

Think of it as a Pipe for both controls and indicators

ni.com

Can become costly/cumbersome

Put whatever you want on it!

13
13

Style: Before Using the Register Bus

ni.com

14
14

Style: After Using the Register Bus

ni.com

15
15

Style: Designs Register Bus

Pros

Saves space on large applications

Cons

A little more code to write

ni.com

Solved for special cases by adding additional DMA FIFOs

16
16

Style: Designs Basic Elements

Dont try to reinvent the wheel

There are some basic

ni.com

If you install an instrument

17
17

Style: Designs Counters

NI Decrement

Useful for a terminal count

NI Increment

Zero isnt really a valid number, except on the first set

But as programmers, we often like base-zero!

A Different Increment

ni.com

Supports reset and increment on the same cycle

18
18

Style: Designs NI Increment & Decrement

ni.com

19
19

Style: Designs A Different Increment

ni.com

20
20

Style: Designs Accessing Memory Items

Size of memory items: What gets implemented regardless of what you

36 bit port width for BRAM

Use Base-2 addressing

ni.com

Easier logic but it can be wasteful . . . or is it?

21
21

Style: No Pink in a Case

Using the case structure causes additional underlying logic that we

Fanout

Exceptions: Items without handshaking interfaces

ni.com

Memory writes

Registers.vi of the Register Bus

22
22

Style: Avoid Costly/Unnecessary Operations

Many operations on FPGA that are free

Example: Shift/scale by power of 2

Many other operations are dependent on the width of the data type

Use only the bits that you need (FXP)

Unnecessarily large data types propagate through the chain

How would the operation be performed with hardware logic?

No unnecessary math on the FPGA

Example of a width-dependent operation:

Greater/less than or equal to

ni.com

Determinism normally allows you to simply use equal to!

Standardization: Synchronization

How will data flow in your system?

How does the system respond when data isnt flowing?

What tells modules to start?

How are modules reset?

ni.com

24
24

Standardization: Feedback Nodes & Reset

Three options:

Uninitialized

Initialize on Compile or Load

Initialize on First Call

ni.com

Additional code is added to return the register to the default value when a
Reset command is sent (RESET = FANOUT!)
25
25

Standardization: Multi-FPGA Systems

Do the FPGAs need to be synchronized?

What kind of synchronization?

Data-driven synchronization
o

Hardware synchronization
o
o

ni.com

P2P FIFOs

Clocks
Triggers

26
26

Summary

Set up the project with testing in mind

Agree on standard naming conventions

Think of state machines as state controllers

Use the Register Bus to modularize designs and preserve space

Dont reinvent the wheel!

Make accessing memory simple with Base-2 addressing

No pink in a case (with some exceptions)

Develop to a standardized strategy for synchronization (or lack of!)

ni.com

27
27

Thank You!

Questions?

Zach Hawkins

Software Developer, Averna

28
28

ni.com

29