Lesson

Module 13
3 Interfacing bus, Protocols,
Embedded Systems I/O ISA bus etc.
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Instructional Objectives

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After going through this lesson the student would learn

USB Power
7.5V/12V/15V LCD/CCD Supply

Supply
Inverter

Wall
ƒ Bus, Wires and Ports
ƒ Basic Protocols of data transfer
ƒ

TFT Panel

Controller
1.6in/1.8in
Bus arbitration

Monitor

TFT
TV

Charge
Pump
ƒ ISA bus signals and handshaking
ƒ Memory mapped I/O and simple I/O

Battery Charger
ƒ Parallel I/O and Port Based I/O

Removable Storage
ƒ

Op Amps
Example of interfacing memory to the ports of 8051

Video

RS232c

Converter
1394
USB

Boost

Alkaline
Pre-Requisite

Remote
Ir Rx
Digital Electronics, Microprocessors

Measurement

3.3-V/5-V System Supply

Battery Management
Zoom Lens
Position

Li+NiMH
TI Digital Media Processor
13.1 Introduction

Buck Boost
½-MB Flash

Converter
Memory

Fig. 13.1
Buttons
The traditional definition of input-output is the devices those create a medium of interaction with

MCU
the human users. They fall into the following categories such as:
1. Printers

USB Voltage
Battery and

Monitoring
2. Visual Display Units
3. Keyboard
4. Cameras

Converter
1.5-V/1.8-/2.5V Core Supply
32164-MB
SDRAM

Buck
5. Plotters

Status
LCD
6. Scanners

LI-Ion Protector

Battery Monitor
However in Real-Time embedded systems the definition of I/O devices is very different. An
embedded controller needs to communicate with a wide range of devices namely

Generator
1. Analog to Digital (A-D) and Digital to Analog (D-A) Converters

TI AFE
Timing
Drivers
Motors
2. CODECs

Codec Module

Power Amplifier

Low Dropout
3. Small Screen Displays such as TFT, LCD etc

Regulator
Audio
4. Antennas

Audio
5. Cameras

Module
CCD
6. Microphones

V/H
7. Touch Screens

Speed light
Etc.

Motors

Power Management
A typical Embedded system is a Digital Camera as shown in Fig. 13.1. As it can be seen it

Supervisor
possesses broad range of input-output devices such as Lens, Microphone, speakers, Serial

Voltage
Supply
Reset
interface standards, TFT screens etc.

Lens
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The functionality of an Embedded System can be broadly classified as

Processing rd'/wr
• Transformation of data
enable
• Implemented using processors
Storage addr
• Retention of data
• Implemented using memory
And Communication (also called Interfacing) data
• Transfer of data between processors and memories
tsetup tread
• Implemented using buses
read protocol
Interfacing Fig. 13.2(b)
For write (Fig. 13.2(c))
Interfacing is a way to communicate and transfer information in either way without ending into The CPU must send the memory address
deadlocks. In our context it is a way of effective communication in real time. The write line must be enabled
This involves The processor sends the data over the data lines
– Addressing The processor must wait till the memory is ready
– Arbitration
– Protocols
rd'/wr
Master Slave enable
addr
Control Lines
Address Lines
Data Lines data

tsetup twrite
Fig. 13.2(a) The Bus structure
write protocol
Addressing: The data sent by the master over a specified set of lines which enables just the
device for which it is meant Fig. 13.2(c)
Protocols: The literal meaning of protocol is a set of rules. Here it is a set of formal rules Arbitration: When the same set of address/data/control lines are shared by different units then
describing how to transfer data, especially between two devices. the bus arbitration logic comes into play. Access to a bus is arbitrated by a bus master. Each
A simple example is memory read and write protocol. The set of rules or the protocol is node on a bus has a bus master which requests access to the bus, called a bus request, when then
For read (Fig. 13.2 (b)) node requires to use the bus. This is a global request sent to all nodes on the bus. The node that
The CPU must send the memory address currently has access to the bus responds with either a bus grant or a bus busy signal, which is
The read line must be enabled also globally known to all bus masters. (Fig. 13.3)
The processor must wait till the memory is ready
Then accept the bits in the data lines

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 Time-multiplexed data transfer
Master req Servant Master req Servant
CPU Memory Memory data(15.0) data(15.0)
addr data addr data
1 2
mux demux mux demux
data(8) addr/data

I/O I/O req req

Device Device DMA
1 2 data 15:8 7:0 addr/data addr data

Fig. 13.3 The bus arbitration of the DMA, known as direct memory access Data serializing Address/data muxing
controller which is responsible for transferring data between an I/O device and
memory without involving the CPU. It starts with a bus request to the CPU and Fig. 13.4 The Time multiplexing data transfer. The left hand side transmits 16-bits
after it is granted it takes over the address/data and control bus to initiate the data of data in an 8-bit line MSB after the LSB. The transfer is synchronized with the
transfer. After the data transfer is complete it passes the control over to the CPU. req signal. In the example shown on the right hand side the same set of wires carry
address followed by data in synchronism with the req signal. mux: stands for
Before learning more details about each of these concepts a concrete definition of the following multiplexer
terms is necessary.
Wire: It is just a passive physical connection with least resistance The Handshaking Protocol
Bus: A group of signals (such as data, address etc). It may be augmented with buffers latches etc.
A bus has standard specification such as number of bits, the clock speed etc. Strobe Protocol
Port: It is the set of physical wires available so that any device which meets the specified
standard can be directly plugged in. Example is the serial, parallel and USB port of the PC. Master Servant
req
Time multiplexing: This is to Share a single set of wires for multiple pieces of data. It saves wires
at expense of time

data

req 1 3

data 2 4

Fig. 13.5(a) Strobe Protocol

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 1. Master asserts req to receive data The Strobe & Handshake combined
2. Servant puts data on bus within time taccess
3. Master receives data and deasserts req
4. Servant ready for next request Master req Servant

Handshake Protocol wait

Master Servant data

req

ack
req 1 3 req 1 4

wait wait 2 3
data
data 2 4 data 5

taccess taccess

1 3 1. Master asserts req to receive data 1. Master asserts req to receive data
req 2. Servant puts data on bus within time taccess 2. Servant can’t put data within taccess, asserts wait ack
4 (wait line is unused) 3. Servant puts data on bus and deasserts wait
2
ack 3. Master receives data and deasserts req 4. Master receives data and deasserts req
4. Servant ready for next request 5. Servant ready for next request
data
Fast-response case Slow-response case

Fig. 13.5(c) Strobe and Handshake Combined

Fig. 13.5(b) Handshake Protocol

1. Master asserts req to receive data

2. Servant puts data on bus and asserts ack
Handshaking Example in ISA Bus
3. Master receives data and deasserts req
The Industry Standard Architecture (ISA Bus) has been described as below
4. Servant ready for next request
This is a standard bus architecture developed to help the various designers to customize their
product and the interfaces. The pin configuration and the signals are discussed below.

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 address, data, and read/write signals. This signal should be included as part of ISA board select
decodes to prevent incorrect board selects during DMA cycles.

BALE
Buffered Address Latch Enable is used to latch the LA23 to LA17 signals or decodes of these
signals. Addresses are latched on the falling edge of BALE. It is forced high during DMA cycles.
When used with AEN, it indicates a valid microprocessor or DMA address.

CLK
System Clock is a free running clock typically in the 8MHz to 10MHz range, although its exact
frequency is not guaranteed. It is used in some ISA board applications to allow synchronization
with the system microprocessor.

SD15 to SD0
System Data serves as the data bus bits for devices on the ISA bus. SD15 is the most significant
bit. SD0 is the least significant bits. SD7 to SD0 are used for transfer of data with 8-bit devices.
SD15 to SD0 are used for transfer of data with 16-bit devices. 16-bit devices transferring data
Fig. 13.6 The ISA bus with 8-bit devices shall convert the transfer into two 8-bit cycles using SD7 to SD0.

ISA Signal Descriptions DACK0 to DACK3 and DACK5 to DACK7

SA19 to SA0 (SA for System Address) DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests on DRQ0 to DRQ3
and DRQ5 to DRQ7.
System Address bits 19:0 are used to address memory and I/O devices within the system. These
signals may be used along with LA23 to LA17 to address up to 16 megabytes of memory. Only DRQ0 to DRQ3 and DRQ5 to DRQ7
the lower 16 bits are used during I/O operations to address up to 64K I/O locations. SA19 is the
most significant bit. SA0 is the least significant bit. These signals are gated on the system bus DMA Requests are used by ISA boards to request service from the system DMA controller or to
when BALE is high and are latched on the falling edge of BALE. They remain valid throughout request ownership of the bus as a bus master device. These signals may be asserted
a read or write command. These signals are normally driven by the system microprocessor or asynchronously. The requesting device must hold the request signal active until the system board
DMA controller, but may also be driven by a bus master on an ISA board that takes ownership of asserts the corresponding DACK signal.
the bus.
I/O CH CK
LA23 to LA17
I/O Channel Check signal may be activated by ISA boards to request than an non-maskable
Unlatched Address bits 23:17 are used to address memory within the system. They are used interrupt (NMI) be generated to the system microprocessor. It is driven active to indicate a
along with SA19 to SA0 to address up to 16 megabytes of memory. These signals are valid when uncorrectable error has been detected.
BALE is high. They are "unlatched" and do not stay valid for the entire bus cycle. Decodes of
these signals should be latched on the falling edge of BALE.
I/O CH RDY
AEN I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by inserting wait
states. This signals normal state is active high (ready). ISA boards drive the signal inactive low
Address Enable is used to degate the system microprocessor and other devices from the bus (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low
during DMA transfers. When this signal is active the system DMA controller has control of the

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immediately after detecting a valid address decode and an active read or write command. The REFRESH
signal is release high when the device is ready to complete the cycle.
Memory Refresh is driven low to indicate a memory refresh operation is in progress.
IOR
OSC
I/O Read is driven by the owner of the bus and instructs the selected I/O device to drive read data
onto the data bus. Oscillator is a clock with a 70ns period (14.31818 MHz). This signal is not synchronous with the
system clock (CLK).
IOW
RESET DRV
I/O Write is driven by the owner of the bus and instructs the selected I/O device to capture the
write data on the data bus. Reset Drive is driven high to reset or initialize system logic upon power up or subsequent system
reset.
IRQ3 to IRQ7 and IRQ9 to IRQ12 and IRQ14 to IRQ15
TC
Interrupt Requests are used to signal the system microprocessor that an ISA board requires
attention. An interrupt request is generated when an IRQ line is raised from low to high. The line Terminal Count provides a pulse to signal a terminal count has been reached on a DMA channel
must be held high until the microprocessor acknowledges the request through its interrupt service operation.
routine. These signals are prioritized with IRQ9 to IRQ12 and IRQ14 to IRQ15 having the
highest priority (IRQ9 is the highest) and IRQ3 to IRQ 7 have the lowest priority (IRQ7 is the
lowest). MASTER
Master is used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon
SMEMR receiving a -DACK a device can pull -MASTER low which will allow it to control the system
address, data, and control lines. After MASTER is low, the device should wait one CLK period
System Memory Read instructs a selected memory device to drive data onto the data bus. It is before driving the address and data lines, and two clock periods before issuing a read or write
active only when the memory decode is within the low 1 megabyte of memory space. SMEMR is command.
derived from MEMR and a decode of the low 1 megabyte of memory.
MEM CS16
SMEMW
Memory Chip Select 16 is driven low by a memory slave device to indicate it is capable of
System Memory Write instructs a selected memory device to store the data currently on the data performing a 16-bit memory data transfer. This signal is driven from a decode of the LA23 to
bus. It is active only when the memory decode is within the low 1 megabyte of memory space. LA17 address lines.
SMEMW is derived from MEMW and a decode of the low 1 megabyte of memory.
I/O CS16
MEMR
I/O Chip Select 16 is driven low by a I/O slave device to indicate it is capable of performing a
Memory Read instructs a selected memory device to drive data onto the data bus. It is active on 16-bit I/O data transfer. This signal is driven from a decode of the SA15 to SA0 address lines.
all memory read cycles.
0WS
MEMW
Zero Wait State is driven low by a bus slave device to indicate it is capable of performing a bus
Memory Write instructs a selected memory device to store the data currently on the data bus. It is cycle without inserting any additional wait states. To perform a 16-bit memory cycle without
active on all memory write cycles. wait states, -0WS is derived from an address decode.

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SBHE – Port-based I/O (parallel I/O)
• Processor has one or more N-bit ports
System Byte High Enable is driven low to indicate a transfer of data on the high half of the data • Processor’s software reads and writes a port just like a register
bus (D15 to D8). – Bus-based I/O
• Processor has address, data and control ports that form a single bus
• Communication protocol is built into the processor
The Memory Read bus cycle in ISA bus • A single instruction carries out the read or write protocol on the bus
• Parallel I/O peripheral
CYCLE C1 C2 WAIT C3 C4 – When processor only supports bus-based I/O but parallel I/O needed
– Each port on peripheral connected to a register within peripheral that is read/written by the
CLOCK processor

D[7-0] DATA Processor Memory Processor Port 0

Port 1
A[19-0] ADDRESS Port 2
System bus Port 3
ALE

/MEMR Parallel I/O peripheral Parallel I/O peripheral

CHRDY
Port A Port B Port C Port A Port B Port C
Fig. 13.7(a) The Handshaking Mode of Data Transfer in ISA bus
Adding parallel I/O to a bus- Extended parallel I/O
The Memory Write bus cycle in ISA bus based I/O processor

Fig. 13.8 Parallel I/O and extended Parallel I/O

CYCLE C1 C2 WAIT C3 C4
• Extended parallel I/O
CLOCK – When processor supports port-based I/O but more ports needed
– One or more processor ports interface with parallel I/O peripheral extending total number
D[7-0] DATA
of ports available for I/O
ADDRESS – e.g., extending 4 ports to 6 ports in figure
A[19-0]
Types of bus-based I/O:
ALE
Memory-mapped I/O and standard I/O
/MEMW • Processor talks to both memory and peripherals using same bus – two ways to talk to
peripherals
CHRDY – Memory-mapped I/O
• Peripheral registers occupy addresses in same address space as memory
• e.g., Bus has 16-bit address
Fig. 13.7(b) The Handshaking Mode of Data Transfer in ISA bus – lower 32K addresses may correspond to memory
– upper 32k addresses may correspond to peripherals
13.2 I/O addressing – Standard I/O (I/O-mapped I/O)
• Additional pin (M/IO) on bus indicates whether a memory or peripheral access
• A microprocessor communicates with other devices using some of its pins. Broadly we can • e.g., Bus has 16-bit address
classify them as – all 64K addresses correspond to memory when M/IO set to 0

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 – all 64K addresses correspond to peripherals when M/IO set to 1
Memory-mapped I/O vs. Standard I/O
• Memory-mapped I/O
– Requires no special instructions Clock
• Assembly instructions involving memory like MOV and ADD work with peripherals as
well
P0 Adr. 7..0 Data
• Standard I/O requires special instructions (e.g., IN, OUT) to move data between
peripheral registers and memory
• Standard I/O P2 Adr. 15…8
– No loss of memory addresses to peripherals
– Simpler address decoding logic in peripherals possible
• When number of peripherals much smaller than address space then high-order address Q Adr. 7…0
bits can be ignored
– smaller and/or faster comparators
A basic memory protocol ALE
/RD
Interfacing an 8051 to external memory
8051 has three 8-bit ports through which it can communicate with the outside world.
Fig. 13.9(b) The timing diagram
– Ports P0 and P2 support port-based I/O when 8051 internal memory being used
– Those ports serve as data/address buses when external memory is being used
The timing of the various signals is shown in Fig. 13.9(b). The lower byte of the address is
– 16-bit address and 8-bit data are time multiplexed; low 8-bits of address must therefore be
placed along P0 and the address latch enable signal is enabled. The higher byte of the address is
latched with aid of ALE (address latch enable) signal placed along P2. The ALE signal enables the 74373 chip to latch the address as the P0 bus will
be used for data. The P0 bus goes into tri-state (high impedance state) and switches internally for
D<0…7> data path. The RD (read) line is enabled. The bar over the read line indicates that it is active
P0 D Q when low. The data is received from the memory on the P0 bus. A memory write cycle can be
A<0…15> explained similarly.
/CS
/OE
ALE G /WE 13.3 Conclusion
74373 CS2 /CS1
8 HM6264 In this lesson you learnt about the basics of Input Output interfacing. In the previous
P2 chapter you also studied about some input output concepts. But most of those I/O such as Timer,
/WR /CS Watch Dog circuits, PWM generator, Serial and Parallel ports were part of the microcontroller.
/RD D<0…7> In this lesson the basics of interfacing with external devices have been discussed. The difference
/PSEN between a Bus and a Port should be kept in mind. The ISA bus is discussed to give an idea about
A<0…14>
the various bus architectures which will discussed in the later part of this course. You must
/OE browse various websites as listed below for further knowledge.
8051 27C256 http://esd.cs.ucr.edu/slide_index.html
http://esd.cs.ucr.edu/wres.html
www.techfest.com/hardware/bus/isa.htm
Fig. 13.9(a) A basic memory interface You should be able to be in a position to learn any microcontroller and their interfacing
protocols.

13.4 Questions
1. List at least 4 differences between the I/O devices for a Real Time Embedded System
(RTES) and a Desktop PC?

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 RTES I/O PC I/O Ans:
It has to operate in real time. The timing May take little longer and need not satisfy I/O CH RDY
requirement has to met. the stringent timing requirement of the user I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by inserting wait
The I/O devices need not be meant for the The I/O for desktop encompasses a broad states. This signals normal state is active high (ready). ISA boards drive the signal inactive low
human user and may consists of analog range. Generally the keypad, monitor, (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low
interfaces, digital controllers, mixed signal
mouse etc which are meant for the human immediately after detecting a valid address decode and an active read or write command. The
circuits. users are termed as I/O. But it could have signal is release high when the device is ready to complete the cycle.
also the similar I/Os as in case of RTES
The power consumption of these I/O There is virtually no strict limit to the 4. What additional handshaking signals are necessary for bidirectional data transfer over the
devices should be limited. power in such I/Os same set data lines.
The size of the I/O devices should be small Generally the size is not a problem as it is
to make it coexist with the processor and not meant to be portable Ans:
other devices For an 8-bit data transfer we need at least 4 additional lines for hand shaking. As shown in
Fig.Q4 there are two ports shown. Port A acts as the 8-bit bidirectional data bus. Port C carries
2. Draw the timing diagram of a memory read protocol for slower memory. What additional the handshaking signals.
handshaking signals are necessary?
Write operation: When the data is ready the /OBFA (PC7 output buffer full acknowledge active
Ans: An additional handshaking signal from the memory namely /ready is necessary. The low) signal is made 0. The device which is connected acknowledges through /ACKA( PC6
microcontroller inserts wait states as long as the /ready line is not inactive. The ready line in this acknowledge that it is ready to accept data. It is active low). The data transfer takes place over
case is sampled at the rising edge of the third clock phase. Fig.Q2 reveals the timing of such an PA0-PA7.
operation. Read operation: When the data is ready the external device makes the /STBA (PC4 Strobe
acknowledge active low) line low. The acknowledgement is sent through IBFA (Input Buffer
Empty Acknowledge that it is ready to accept data. It is active high). The data transfer takes
T1 T2 Twait T4 T5 place.

Clock
PA7-PA0 8

Address PC7 OBFA

PC6 ACKA
/RD
PC4 STBA

PC5 IBFA
/Ready
Fig. Q4 The master

Data 5. List the various bus standards used in industry.

Ans:

ISA Bus
Fig. Q2 The Timing Diagram of memory read from a slower The Industry Standard Architecture (ISA) bus is an open, 8-bit (PC and XT) or 16-bit (AT)
asymmetrical I/O channel with numerous compatible hardware implementations.
3. Enlist the handshaking signals in the ISA bus for dealing with slower I/O devices.
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EISA Bus address each other. All data is entered into system memory before being transferred to another
I/O option. The design facilitates a concise and compact protocol with very high performance.
The Extended Industry Standard Architecture (EISA) bus is an open, 32-bit, asymmetrical I/O
channel with numerous compatible hardware implementations. The system bus and allows data XMI Bus
transfer rates at a bandwidth of up to 33 MB per second, supports a 4 GB address space, 8 DMA
channels, and is backward compatible with the Industry Standard Architecture (ISA) bus. The XMI bus is a 64-bit wide parallel bus that can sustain a 100 MB per second bandwidth in a
single processor configuration. The bandwidth is exclusive of addressing overhead; the XMI bus
PCI Bus can transmit 100 MB per second of data.
The XMI bus implements a "pended protocol" design so that the bus does not stall between
The Peripheral Component Interconnect Local Bus (PCI) is an open, high-performance 32-bit or requests and transmissions of data. Several transactions can be in progress at a given time. Bus
64-bit synchronous bus with multiplexed address and data lines, and numerous compatible cycles not used by the requesting device are available to other devices on the bus. Arbitration
hardware implementations. PCI bus support a PCI frequency of 33 MHz and a transfer rate of and data transfers occur simultaneously, with multiplexed data and address lines. These design
132 MB per second. features are particularly significant when a combination of multiple devices has a wider
bandwidth than the bus itself.
Futurebus+
VME Bus
Futurebus+ is an open bus, designed by the IEEE 896 committee, whose architecture and
interfaces are publicly documented, and that is independent of any underlying architecture. It has Digital UNIX includes a generic VME interface layer that provides customers with a consistent
broad-base, cross-industry support; very high throughput (the maximum rate for 64-bit interface to VME devices across Alpha AXP workstation and server platforms. Currently, VME
bandwidth is 160 MB per second; for the 128-bit bandwidth, 180 MB per second). Futurebus+ adapters are only supported on the TURBOchannel bus. To use the VME interface layer to write
supports a 64-bit address space and a set of control and status registers (CSRs) that provides all VMEbus device drivers, you must have the Digital UNIX TURBOchannel/VME Adapter Driver
the necessary ability to enable or disable features; thus supporting multivendor interoperablity. Version 2.0 software (Software Product Description 48.50.00) and its required processor and/or
hardware configurations (Software Support Addendum 48.50.00-A).
SCSI Bus
The Small Computer Systems Interface (SCSI) bus is an ANSI standard for the interconnection
of computers with each other and with disks, floppies, tapes, printers, optical disks, and scanners.
The SCSI standard includes all the mechanical, electrical, and
Data transfer rates are individually negotiated with each device attached to a given SCSI bus. For
example, a 4 MB per second device and a 10 MB per second device may share a fast narrow bus.
When the 4 MB per second device is using the bus, the transfer rate is 4 MB per second. When
the 10 MB per second device is using the bus, the transfer rate is 10 MB per second. However,
when faster devices are placed on a slower bus, their transfer rate is reduced to allow for proper
operation in that slower environment.
Note that the speed of the SCSI bus is a function of cable length, with slow, single-ended SCSI
buses supporting a maximum cable length of 6 meters, and fast, single-ended SCSI buses
supporting a maximum cable length of 3 meters.

TURBOchannel Bus
The TURBOchannel bus is a synchronous, 32-bit, asymmetrical I/O channel that can be operated
at any fixed frequency in the range 12.5 MHz to 25 MHz. It is also an open bus, developed by
Digital, whose architecture and interfaces are publicly documented.
At 12.5 MHz, the peak data rate is 50 MB per second. At 25 MHz, the peak data rate is 100 MB
per second.
The TURBOchannel is asymmetrical in that the base system processor and system memory are
defined separately from the TURBOchannel architecture. The I/O operations do not directly

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