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02 - Modulo-5 Counter

This document describes designing and simulating a modulo-5 counter circuit using Proteus VSM software. It provides background on modulo-5 counters and explains how to implement one using a 4-bit binary counter. The circuit is built by placing components from the library, including dual 4-stage counters, AND gates, resistors and LEDs. The design is then tested through simulation to verify the correct modulo-5 counting operation. Exercises are included to modify the circuit into other modulo counters.

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Usman Qadeer
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
506 views

02 - Modulo-5 Counter

This document describes designing and simulating a modulo-5 counter circuit using Proteus VSM software. It provides background on modulo-5 counters and explains how to implement one using a 4-bit binary counter. The circuit is built by placing components from the library, including dual 4-stage counters, AND gates, resistors and LEDs. The design is then tested through simulation to verify the correct modulo-5 counting operation. Exercises are included to modify the circuit into other modulo counters.

Uploaded by

Usman Qadeer
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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2 Modulo-5 Counter

LAB Objectives
The aim of this LAB experiment is to familiarize students with the techniques required
to design and simulate digital circuits using Proteus Virtual System Modeling (VSM)
software package. The experiment is designed to guide the students through the process of
designing, editing and simulating a simple modulo-n counter circuit using the schematic
editor ISIS. The LAB covers basic schematic editing topics such as placing and wiring up
components, and then moves on to circuit testing using virtual modeling and simulation. 

2.1 Background
In this experiment we will design a a modulo-5 binary counter which counts (0,1, 2,
3, 4, 0, 1, 2, . . ., etc). This counter can be implemented using a 4-bit binary counter
with asynchronous reset input. The modulo-5 count is achieved by gating the outputs of
the 4-bit binary counter (Q3 Q2 Q1 Q0 ) through an "AND" gate and connecting it to the
asynchronous reset input M R such that the counter is cleared when the count reaches 5
(Q3 Q2 Q1 Q0 = 0101). Note that, the binary value 0101 can be distinguished from lower
binary counts (0000, 0001, 0010, 0011, 0100) by the values of Q2 and Q0 together. Thus, as
shown in Figure 2.1, the asynchronous reset input of the counter is connected to Q2 Q0 .
Exercise 2.1 List the binary counts for a modulo-3 counter and show how to gate the outputs of the
4-bit binary counter to implement this modulo counter. Repeat the exercise for modulo-4, modulo-6,

and modulo-7 counters.

18

Modulo-5 Counter

CO U N T E R 4

CLK
1

CLK

M R

7 4 LS 3 9 3

Q 0
Q 1
Q 2
Q 3

Q 0
4

Q 1
5

Q 2
6

A N D 2

Q 3

1
2

7 4 LS 0 8

Figure 2.1 Modulo 5 binary counter.

2.2 Required Components


1. Dual 4-Stage Binary Counters (74LS393)
2. Quadruple 2-Input Positivve AND Gates (74LS08)
3. Resistor 100 (MINRES100R)
4. Animated Red LED Model (LED-RED)

2.3 Schematic Entry


To design the modulo-5 binary counter shown in Figure 2.2 follow the procedure described
below :
1. Create a new project file and save it as "mod5_counter.pdsprj".
2. Get the required circuit components from the Library.
3. Place the selected circuit components on the schematic sheet.
4. Place a GROUND terminal from the Terminals list box.
5. Place a clock generator by choosing the Generator Mode from the left menu bar and
then selecting DCLOCK from the Generators list box as shown in Figure 2.3(a).
6. Place a ground terminal by choosing the Terminals Mode and then selecting GROUND
from the Terminals list box as shown in Figure 2.3(b).
7. Edit the properties of the circuit components and modify their names according to
Figure 2.2.
8. Connect the circuit components as shown in Figure 2.2.

2.4 Testing the Design


After completing the schematic entry of the modulo-5 counter, simulate your design by
clicking on the Play button at the bottom of the Editing Widow. If there are no errors in
your design, then you will notice that the LEDs are blinking to reflect the modulo-5 count.

19

2.4 Testing the Design

Figure 2.2 Schematic of the modulo-5 binary counter.

(a)

(b)

Figure 2.3 Placing components using Editing Modes. (a) clock generator, (b)
ground terminal.

20

Modulo-5 Counter

Exercise 2.2 Referring to Figure 2.2, modify the design of the modulo-5 counter into modulo-3 counter

and simulate the resulting counter.

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