AEC - Q100 - Rev-H

September 11, 2014

FAILURE MECHANISM BASED

STRESS TEST QUALIFICATION
FOR
INTEGRATED CIRCUITS

Automotive Electronics Council

Component Technical Committee

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

TABLE OF CONTENTS
AEC-Q100 Failure Mechanism Based Stress Test Qualification for Integrated Circuits
Appendix 1:

Definition of a Qualification Family

Appendix 2:

Q100 Certification of Design, Construction and Qualification

Appendix 3:

Plastic Package Opening for Wire Bond Testing

Appendix 4:

Minimum Requirements for Qualification Plans and Results

Appendix 5:

Part Design Criteria to Determine Need for EMC Testing

Appendix 6:

Part Design Criteria to Determine Need for SER Testing

Appendix 7

AEC-Q100 and the Use of Mission Profiles

Attachments
AEC-Q100-001:

WIRE BOND SHEAR TEST

AEC-Q100-002:

HUMAN BODY MODEL (HBM) ELECTROSTATIC DISCHARGE (ESD) TEST

AEC-Q100-003:

MACHINE MODEL (MM) ELECTROSTATIC DISCHARGE (ESD) TEST

(DECOMMISSIONED)

AEC-Q100-004:

IC LATCH-UP TEST

AEC-Q100-005:

NONVOLATILE MEMORY WRITE/ERASE ENDURANCE, DATA RETENTION,

AND OPERATIONAL LIFE TEST

AEC-Q100-006:

ELECTRO-THERMALLY INDUCED PARASITIC GATE LEAKAGE (GL) TEST

(DECOMMISSIONED)

AEC-Q100-007:

FAULT SIMULATION AND TEST GRADING

AEC-Q100-008:

EARLY LIFE FAILURE RATE (ELFR)

AEC-Q100-009:

ELECTRICAL DISTRIBUTION ASSESSMENT

AEC-Q100-010:

SOLDER BALL SHEAR TEST

AEC-Q100-011:

CHARGED DEVICE MODEL (CDM) ELECTROSTATIC DISCHARGE (ESD)

TEST

AEC-Q100-012:

SHORT CIRCUIT RELIABILITY CHARACTERIZATION OF SMART POWER

DEVICES FOR 12V SYSTEMS

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Revision Summary
This informative section briefly describes the changes made in the AEC-Q100 Rev-H document, compared to
previous document version, AEC-Q100 Rev-G (May 14, 2007). Punctuation and text improvements are not
included in this summary.

Section 1.2.1 Automotive Reference Documents: Added reference to AEC-Q005 Pb-Free

Requirements
NEW Section 1.2.4 Decommissioned Reference Documents: Added new section providing guidance
on elimination of AEC-Q100-003 Machine Model ESD (removed due to industry test obsolescence) and
Q100-006 Electrothermally Induced Gate Leakage (removed due to lack of industry need as a
qualification test)
Section 1.3.1 AEC Q100 Qualification: Added recommendation that passing ESD voltage level be
specified in supplier datasheet with footnote on any pin exceptions
NEW Section 1.3.2 AEC Certification: Added new definition clarifying that AEC-Q100 certification
does not exist, suppliers perform qualification testing according to AEC standards
Section 1.3.4 Definition of Part Operating Temperature Grade: Added new Table 1 defining part
operating temperature grades and guidance on use of temperature (e.g., endpoint, junction) during tests;
eliminated Grade 4 (0C to +70C) entry
NEW Section 1.3.5 Capability Measure, Cpk: Added new definition and reference to AEC-Q003
Characterization document
Section 2.2 Precedence of Requirements: Added clarification to Purchase Order and Device
Specification entries
Section 2.3.1 Definition of Generic Data: Moved existing Table 1, Part Qualification/Requalification Lot
Requirements, and portion of section text to Appendix 1 Definition of a Product Qualification Family
Section 2.3.2 Time Limit for Acceptance of Generic Data: Added text on use of diagram in Figure 1
Section 2.4.1 Lot Requirements: Added statement that deviation from Table 2 requires technical
explanation
Section 2.5 Definition of Test Failure After Stressing: Added statement on EOS
Section 3.1.1 Qualification of A New Device Manufactured in A Currently Qualified Family: Deleted this
entire section, subject is covered in Appendix 1.
Section 3.2.3 Criteria for Passing Requalification: Modified text to provide better guidance on AECQ100 requalification
NEW Section 3.3 Qualification of A Pb-Free Device: Added new section with requirements for Pb-Free
devices and references to AEC-Q005 Pb-Free Requirements document
Figure 2 Qualification Test Flow:
o Test Group A: Removed statement of PC before PTC
o Test Group B: Corrected test temperature order for post-HTOL testing to Room, Cold, & Hot
o Test Group E: Removed reference to MM ESD and GL tests
Table 2 Qualification Test Methods:
o Test A3 Autoclave or Unbiased HAST or Temperature Humidity (without Bias): Added TH
reference to Additional Requirements column
o Test A4 Temperature Cycling: Revised low-end temperature and minimum duration; added
legacy test temperature note; eliminated Grade 4 entry
o Test A6 High Temperature Storage Life: Added reference to Ta (ambient temperature)
o Test A7 High Temperature Operating Life: Removed 408 hour test duration option; added
notes regarding use of Ta (ambient temperature) and Tj (junction temperature)
o Test C1 Wire Bond Shear: Removed Ppk requirement; modified Cpk accept criteria to
Cpk>1.67; added reference to AEC-Q003
o Test C2 Wire Bond Pull: Removed Ppk requirement; modified Cpk accept criteria to
Cpk>1.67; added reference to AEC-Q003
o Test C3 Solderability: Added reference to J-STD-002D and statement on use of dry bake

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Automotive Electronics Council

Component Technical Committee

Revision Summary (continued)

Table 2 Qualification Test Methods (continued):

o Test C4 Physical Dimension: Removed Ppk requirement; modified Cpk accept criteria to
Cpk>1.67; added reference to AEC-Q003
o Test C5 Solder Ball Shear: Removed Ppk requirement; modified Cpk accept criteria to
Cpk>1.67; added reference to AEC-Q003
o Test E2 Electrostatic Discharge Human Body Model/Machine Model: Eliminated Machine
Model (MM) ESD entry; added reference to Section 1.3.1
o Test E3 Electrostatic Discharge Charged Device Model: Added reference to Section 1.3.1
o Test E5 Electrical Distribution: Added Cpk>1.67 accept criteria and reference to AEC-Q003
o Eliminated Test E8 Electrothermally Induced Gate Leakage entry
o NEW Test E12 Lead (Pb) Free: Added new test entry
o Test F1 Part Average Testing: Modified Additional Requirements providing guidance on
sample sizes and accept criteria
o Test F2 Statistical Bin/Yield Analysis: Modified Additional Requirements providing
guidance on sample sizes and accept criteria
o Test G1 Mechanical Shock: Modified sample size/lot and number of lots
o Test G2 Variable Frequency Vibration: Modified sample size/lot and number of lots
o Test G3 Constant Acceleration: Modified sample size/lot and number of lots
o Test G4 Gross/Fine Leak: Modified sample size/lot and number of lots
o Test G8 Internal Water Vapor: Modified sample size/lot
o Table 2 Legend: Added Note L reference for Pb-Free devices
Table 3 Process Change Qualification Guidelines for the Selection of Tests: Removed MM (Machine
Model) ESD and GL (Gate Leakage) entries; added LF (Lead Free) entry
Appendix 1 Definition of a Product Qualification Family: Complete revision
o NEW Section A1.1 Product: Added new section and text
o NEW Section A1.4 Qualification/Requalification Lot Requirements: Relocated original
AEC-Q100 Rev G Table 1 to Appendix 1 and renumbered as Table A1.1
o Revised Table A1.1 Part Qualification/Requalification Lot Requirements: Deleted row titled
A new part that has some applicable generic data; added NEW entry where The part to be
qualified is slightly more complex
o NEW Table A1.2 Examples for Generic Data Use: Added new Table and content
Appendix Template 4A AEC-Q100 Qualification Test Plan:
o Test C3, SD - Solderability: Added reference to J-STD-002D and requirement of steam aging
o Test E2, HBM/MM ESD Human Body/machine Model: Eliminated MM entry
o Test E8, GL Electrothermally Induced Gate Leakage: Eliminated GL entry
o Tests G1-G4, MECH Hermetic Package Tests: Modified sample size and lot requirements
Appendix Template 4B AEC-Q100 Generic Data:
o Test C3, SD: Added reference to J-STD-002D and requirement of steam aging
o Test E2, HBM/MM: Eliminated MM entry
o Test E8, GL: Eliminated GL entry
o Test G1, MS: Modified sample size and lot requirements
o Test G2, VFV: Modified sample size and lot requirements
o Test G3, CA: Modified sample size and lot requirements
o Test G4, GFL: Modified sample size and lot requirements
o Complete revision of Generic Data Part Attributes Section
NEW Appendix 7 Guideline on Relationship of Robustness Validation to AEC-Q100: Added NEW
Section and text, including NEW Figures A7.1 & A7.2 and NEW Table A7.1

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Automotive Electronics Council

Component Technical Committee

Acknowledgment
Any document involving a complex technology brings together experience and skills from many sources. The
Automotive Electronics Council would especially like to recognize the following significant contributors to the
revision of this document:
Sustaining Members:
Bankim Patel

Autoliv

Drew Hoffman

Earl Fischer

Autoliv

Gary Fisher

John Schlais
Hadi Mehrooz
Brad Ulery
Mark A. Kelly
Ramon Aziz
Mike Wiegand

Continental Corporation
Continental Corporation
Cummins
Delphi Corporation
Delphi Corporation
Denso International

Steve Sibrel
Ludger Kappius
Joe Lucia
Eric Honsowetz
Thomas VanDamme
Jorge Marta

Gentex
Gentex (formerly with Johnson
Controls)
Harmon
Hella
John Deere
Lear Corporation
TRW Automotive
Visteon Corporation

Technical Members:
Tim Haifley
Jean-Pierre Guerre
Heinz Reiter
James Molyneaux
Xin Miao Zhao
Rene Rodgers
Nick Lycoudes
Werner Kanert
Scott Daniels
Lyn Zastrow
Banjie Bautista
Tom Lawler
John Grogan
Warren Chen
Jeff Aquino
Mike Buzinski
Nick Martinez
Angelo Visconti

Altera
Altera
AMS
Analog Devices
Cirrus Logic
Cypress Semiconductor
Freescale
Infineon Technologies
International Rectifier
ISSI
ISSI
Lattice Semiconductor
Macronix
Macronix
Maxim Integrated
Microchip
Microchip
Micron

Zhongning Liang
Bob Knoell [Q100 Team Leader]
Peter Turlo
Daniel Vanderstraeten
Pamela Finer
Tony Walsh
Futoshi Tagami
Francis Classe
Bassel Atala
Mike Cannon
Larry Ting
James Williams
Gerardo Sepulveda
Arthur Chiang
David Leandri
Anca Voicu
Dean Tsaggaris

NXP Semiconductors
NXP Semiconductors
ON Semiconductor
ON Semiconductor
Pericom Semiconductor
Renesas Electronics
Renesas Electronics
Spansion
STMicroelectronics
TDK
Texas Instruments
Texas Instruments
Tyco Electronics
Vishay
Vishay
Xilinx
Xilinx

Associate Members:
James McLeish
Jeff Darrow
Andy Mackie
Weiyen Kuo

DfR Solutions
Global Foundries
Indium Corporation
TSMC

Guest Members:
Jeff Jarvis

AMRDEC

Other Contributors:
Wolfgang Reinprecht
Alan Righter
John Timms
Richard Forster
John Monteiro
Paul Ngan
Theo Smedes
Rene Rongen

AMS
Analog Devices
Continental Corporation
Continental Corporation
formerly with Delphi
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors

Thomas Hough
Thomas Stich
Donna Moreland
Scott Ward
Marty Johnson
Colin Martin
Kedar Bhatawadekar
Cesar Avitia

Renesas Electronics
Renesas Electronics
Texas Instruments
Texas Instruments
Texas Instruments
formerly withTexas Instruments
Tyco Electronics
Visteon Corporation

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Automotive Electronics Council

Component Technical Committee

NOTICE

AEC documents contain material that has been prepared, reviewed, and approved through the AEC
Technical Committee.
AEC documents are designed to serve the automotive electronics industry through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of
products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for
use by those other than AEC members, whether the standard is to be used either domestically or
internationally.
AEC documents are adopted without regard to whether or not their adoption may involve patents or articles,
materials, or processes. By such action AEC does not assume any liability to any patent owner, nor does it
assume any obligation whatever to parties adopting the AEC documents. The information included in AEC
documents represents a sound approach to product specification and application, principally from the
automotive electronics system manufacturer viewpoint. No claims to be in Conformance with this document
shall be made unless all requirements stated in the document are met.
Inquiries, comments, and suggestions relative to the content of this AEC document should be addressed to
the AEC Technical Committee on the link http://www.aecouncil.com.
Published by the Automotive Electronics Council.
This document may be downloaded free of charge, however AEC retains the copyright on this material. By
downloading this file, the individual agrees not to charge for or resell the resulting material.
Printed in the U.S.A.
All rights reserved
Copyright 2014 by the Automotive Electronics Council. This document may be freely reprinted with this
copyright notice. This document cannot be changed without approval from the AEC Component Technical
Committee.

AEC - Q100 - REV-H

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Automotive Electronics Council

Component Technical Committee

FAILURE MECHANISM BASED STRESS TEST QUALIFICATION

FOR PACKAGED INTEGRATED CIRCUITS
Text enhancements and differences made since the last revision of this document
are shown as underlined areas. Several figures and tables have also been revised,
but changes to these areas have not been underlined.
Unless otherwise stated herein, the date of implementation of this standard for new
qualifications and re-qualifications is as of the publish date above.
1.

SCOPE
This document contains a set of failure mechanism based stress tests and defines the minimum
stress test driven qualification requirements and references test conditions for qualification of
integrated circuits (ICs). These tests are capable of stimulating and precipitating semiconductor
device and package failures. The objective is to precipitate failures in an accelerated manner
compared to use conditions. This set of tests should not be used indiscriminately. Each qualification
project should be examined for:
a.
b.
c.

Any potential new and unique failure mechanisms.

Any situation where these tests/conditions may induce failures that would not be seen in the
application.
Any extreme use condition and/or application that could adversely reduce the acceleration.

Use of this document does not relieve the IC supplier of their responsibility to meet their own
company's internal qualification program. In this document, "user" is defined as all customers using a
device qualified per this specification. The user is responsible to confirm and validate all qualification
data that substantiates conformance to this document. Supplier usage of the device temperature
grades as stated in this specification in their part information is strongly encouraged.
1.1

Purpose
The purpose of this specification is to determine that a device is capable of passing the specified
stress tests and thus can be expected to give a certain level of quality/reliability in the application.

1.2

Reference Documents
Current revision of the referenced documents will be in effect at the date of agreement to the
qualification plan. Subsequent qualification plans will automatically use updated revisions of these
referenced documents.

1.2.1

Automotive
AEC-Q001 Guidelines for Part Average Testing
AEC-Q002 Guidelines for Statistical Yield Analysis
AEC-Q003 Guidelines for Characterizing the Electrical Performance
AEC-Q004 Zero Defects Guideline (DRAFT)
AEC-Q005 Pb-Free Requirements
SAE J1752/3 Integrated Circuits Radiated Emissions Measurement Procedure

1.2.2

Military
MIL-STD-883 Test Methods and Procedures for Microelectronics

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Component Technical Committee

1.2.3

Industrial
JEDEC JESD-22 Reliability Test Methods for Packaged Devices
UL-STD-94 Tests for Flammability of Plastic materials for parts in Devices and Appliances
IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Plastic Integrated Circuit
Surface Mount Devices
JESD89 Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft
Errors in Semiconductor Devices
JESD89-1 System Soft Error Rate (SSER) Test Method
JESD89-2 Test Method For Alpha Source Accelerated Soft Error Rate
JESD89-3 Test Method for Beam Accelerated Soft Error Rate

1.2.4

Decommissioned
AEC Q100-003 ESD Machine Model
Removed from JEDEC due to obsolescence. HBM and CDM cover virtually all known
ESD-related failure mechanisms.
AEC Q100-006 Electrothermally-Induced Gate Leakage
Removed due to the lack of need for it as a qualification test.

1.3

Definitions

1.3.1

AEC Q100 Qualification

Successful completion and documentation of the test results from requirements outlined in this
document allows the supplier to claim that the part is AEC Q100 qualified. For ESD, it is highly
recommended that the passing voltage be specified in the supplier datasheet with a footnote on any
pin exceptions. This will allow suppliers to state, e.g., "AEC-Q100 qualified to ESD Classification 2".

1.3.2

AEC Certification
Note that there are no "certifications" for AEC-Q100 qualification and there is no certification board
run by AEC to qualify parts. Each supplier performs their qualification to AEC standards, considers
customer requirements and submits the data to the customer to verify compliance to Q100.

1.3.3

Approval for Use in an Application

"Approval" is defined as user approval for use of a part in their application. The user's method of
approval is beyond the scope of this document.

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Component Technical Committee

1.3.4

Definition of Part Operating Temperature Grade

The part operating temperature grades are defined in Table 1 below:

Table 1: Part Operating Temperature Grades

Grade

Ambient Operating Temperature Range

-40C to +150C

-40C to +125C

-40C to +105C

-40C to +85C

The endpoint test temperatures for hot and cold test, if required for that stress test, must be
equivalent to those specified for the particular grade. If accounting for junction heating during
powered test, hot test endpoint test temperature can be greater.
For Test Group B Accelerated Lifetime Simulation Tests: High Temperature Operating Life (HTOL),
Early Life Failure Rate (ELFR) and NVM Endurance, Data Retention, and Operational Life (EDR), the
junction temperature of the device during stressing should be equal to or greater than the hot
temperature for that grade.
1.3.5

Capability Measures Cpk

Refer to AEC-Q003 Characterization to understand how the Cpk measure will be used in this
standard.

2.

GENERAL REQUIREMENTS

2.1

Objective
The objective of this specification is to establish a standard that defines operating temperature grades
for integrated circuits based on a minimum set of qualification requirements.

2.1.1

Zero Defects
Qualification and some other aspects of this document are a subset of, and contribute to, the
achievement of the goal of Zero Defects. Elements needed to implement a zero defects program can
be found in AEC-Q004 Zero Defects Guideline.

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Component Technical Committee

2.2

Precedence of Requirements
In the event of conflict in the requirements of this standard and those of any other documents, the
following order of precedence applies:
a.
b.
c.
d.
e.

The purchase order (or master purchase agreement terms and conditions)
The (mutually agreed) individual device specification
This document
The reference documents in Section 1.2 of this document
The supplier's data sheet

For the device to be considered a qualified part per this specification, the purchase order and/or the
individual device specification cannot waive or detract from the requirements of this document.
2.3

Use of Generic Data to Satisfy Qualification and Requalification Requirements

2.3.1

Definition of Generic Data

The use of generic data to simplify the qualification process is strongly encouraged. Generic data
can be submitted to the user as soon as it becomes available to determine the need for any additional
testing. To be considered, the generic data must be based on a matrix of specific requirements
associated with each characteristic of the device and manufacturing process as shown in Table 3 and
Appendix 1. If the generic data contains any failures, the data is not usable as generic data
unless the supplier has documented and implemented corrective action or containment for
the failure condition that is acceptable to the user.
Appendix 1 defines the criteria by which components are grouped into a qualification family for the
purpose of considering the data from all family members to be equal and generically acceptable for
the qualification of the device in question. For each stress test, two or more qualification families can
be combined if the reasoning is technically sound (i.e., supported by data).
Table 3 defines a set of qualification tests that must be considered for any changes proposed for the
component. The Table 3 matrix is the same for both new processes and requalification associated
with a process change. This table is a superset of tests that the supplier and user should use as a
baseline for discussion of tests that are required for the qualification in question. It is the supplier's
responsibility to present rationale for why any of the recommended tests need not be
performed.

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Component Technical Committee

2.3.3

Time Limit for Acceptance of Generic Data

There are no time limits for the acceptability of generic data. Use the diagram below for appropriate
sources of reliability data that can be used. This data must come from the specific part or a part in
the same qualification family, as defined in Appendix 1. Potential sources of data could include any
customer specific data (withhold customer name), process change qualification, and periodic
reliability monitor data (see Figure 1).

Supplier Start
of Production

Internal Device
Characterization

Supplier Internal
Qualification

Qualification data + Process

change qualification data +
Reliability monitor data =
acceptable generic data

Present

Process Change
Qualification

Customer #2
Specific
Qualification

Customer #1
Specific
Qualification

Process Change
Qualification

History

Periodic Reliability
Monitor Tests

Note: Some process changes (e.g., die shrink) will affect the use of
generic data such that data obtained before these types of
changes will not be acceptable for use as generic data.

Figure 1: Generic Data Time Line

2.4

Test Samples

2.4.1

Lot Requirements
Test samples shall consist of a representative device from the qualification family. Where multiple lot
testing is required due to a lack of generic data, test samples as indicated in Table 2 must be
composed of approximately equal numbers from non-consecutive wafer lots, assembled in nonconsecutive molding lots. That is, they must be separated in the fab or assembly process line by at
least one non-qualification lot. Any deviation from the above requires technical explanation from the
supplier.

2.4.2

Production Requirements
All qualification devices shall be produced on tooling and processes at the manufacturing site that will
be used to support part deliveries at production volumes. Other electrical test sites may be used for
electrical measurements after their electrical quality is validated.

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Component Technical Committee

2.4.3

Reusability of Test Samples

Devices that have been used for nondestructive qualification tests may be used to populate other
qualification tests. Devices that have been used for destructive qualification tests may not be used
any further except for engineering analysis.

2.4.4

Sample Size Requirements

Sample sizes used for qualification testing and/or generic data submission must be consistent with
the specified minimum sample sizes and acceptance criteria in Table 2.
If the supplier elects to use generic data for qualification, the specific test conditions and results must
be recorded and available to the user (preferably in the format shown in Appendix 4). Existing
applicable generic data should first be used to satisfy these requirements and those of Section 2.3 for
each test requirement in Table 2. Device specific qualification testing should be performed if the
generic data does not satisfy these requirements.

2.4.5

Pre- and Post-stress Test Requirements

End-point test temperatures (room, hot and/or cold) are specified in the "Additional Requirements"
column of Table 2 for each test.

2.5

Definition of Test Failure After Stressing

Test failures are defined as those devices not meeting the individual device specification, criteria
specific to the test, or the supplier's data sheet, in the order of significance as defined in Section 2.2.
Any device that shows external physical damage attributable to the environmental test is also
considered a failed device. If the cause of failure is due to mishandling during stressing or testing
such as EOS or ESD, or some other cause unrelated to the component reliability, the failure shall be
discounted but reported as part of the data submission.

3.

QUALIFICATION AND REQUALIFICATION

3.1

Qualification of a New Device

The stress test requirement flow for qualification of a new device is shown in Figure 2 with the
corresponding test conditions defined in Table 2. For each qualification, the supplier must have data
available for all of these tests, whether it is stress test results on the device to be qualified or
acceptable generic data. A review shall also be made of other devices in the same generic family to
ensure that there are no common failure mechanisms in that family. Justification for the use of
generic data, whenever it is used, must be demonstrated by the supplier and approved by the user.
For each device qualification, the supplier must have available the following:

3.2

Certificate of Design, Construction and Qualification (see Appendix 2)

Stress Test Qualification data (see Table 2 & Appendix 4)
Data indicating the level of fault grading of the software used for qualification (when applicable to
the device type) per Q100-007 that will be made available to the customer upon request

Requalification of a Changed Device

Requalification of a device is required when the supplier makes a change to the product and/or
process that impacts (or could potentially impact) the form, fit, function, quality and/or reliability of the
device (see Table 3 for guidelines).

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Component Technical Committee

3.2.1

Process Change Notification

The supplier will meet the user requirements for product/process changes.

3.2.2

Changes Requiring Requalification

As a minimum, any change to the product, as defined in Appendix 1, requires performing the
applicable tests listed in Table 2, using Table 3 to determine the requalification test plan. Table 3
should be used as a guide for determining which tests are applicable to the qualification of a
particular part change or whether equivalent generic data can be submitted for that test(s).

3.2.3

Criteria for Passing Requalification

All requalification failures shall be analyzed for root cause. Only when corrective and preventative
actions are in place, the part may then be considered AEC Q100 qualified again.

3.2.4

User Approval
A change may not affect a device's operating temperature grade, but may affect its performance in an
application. Individual user authorization of a process change will be required for that users
particular application(s), and this method of authorization is outside the scope of this document.

3.3

Qualification of a Pb-Free Device

Added requirements needed to address the special quality and reliability issues that arise when Lead
(Pb)-Free processing is utilized is specified in AEC-Q005 Pb-Free Requirements. Materials used in
Pb-Free processing include the termination plating and the board attach (solder). These new
materials usually require higher board attach temperatures to yield acceptable solder joint quality and
reliability. These higher temperatures may adversely affect the moisture sensitivity level of plastic
packaged semiconductors. As a result, new, more robust mold compounds may be required. If an
encapsulation material change is required to provide adequate robustness for Pb-Free processing of
the device, the supplier should refer to the process change qualification requirements in this
specification. Preconditioning should be performed at the Pb-free reflow classification temperatures
described in IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices before environmental stress tests.

4.

QUALIFICATION TESTS

4.1

General Tests
Test flows are shown in Figure 2 and test details are given in Table 2. Not all tests apply to all
devices. For example, certain tests apply only to ceramic packaged devices, others apply only to
devices with NVM, and so on. The applicable tests for the particular device type are indicated in the
Note column of Table 2. The Additional Requirements column of Table 2 also serves to highlight
test requirements that supersede those described in the referenced test method. Any unique
qualification tests or conditions requested by the user and not specified in this document shall be
negotiated between the supplier and user requesting the test.

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4.2

Device Specific Tests

The following tests must be performed on the specific device to be qualified for all hermetic and
plastic packaged devices. Generic data is not allowed for these tests. Device specific data, if it
already exists, is acceptable.
1. Electrostatic Discharge (ESD) - All product.
2. Latch-up (LU) - All product.
3. Electrical Distribution - The supplier must demonstrate, over the operating temperature grade,
voltage, and frequency, that the device is capable of meeting the parametric limits of the device
specification. This data must be taken from at least three lots, or one matrixed (or skewed)
process lot, and must represent enough samples to be statistically valid, see Q100-009. It is
strongly recommended that the final test limits be established using AEC-Q001 Guidelines For
Part Average Testing.
4. Other Tests - A user may require other tests in lieu of generic data based on his experience with
a particular supplier.

4.3

Wearout Reliability Tests

Testing for the failure mechanisms listed below must be available to the user whenever a new
technology or material relevant to the appropriate wearout failure mechanism is to be qualified. The
data, test method, calculations, and internal criteria need not be demonstrated or performed on the
qualification of every new device, but should be available to the user upon request.

Electromigration
Time-Dependent Dielectric Breakdown (or Gate Oxide Integrity Test) - for all MOS technologies
Hot Carrier Injection - for all MOS technologies below 1 micron
Negative Bias Temperature Instability
Stress Migration

Page 8 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Figure 2: Qualification Test Flow

Page 9 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods

TEST GROUP A ACCELERATED ENVIRONMENT STRESS TESTS
STRESS

ABV

Preconditioning

PC

TemperatureHumidity-Bias or
Biased HAST

THB or
HAST

Autoclave or
Unbiased HAST or
TemperatureHumidity (without
Bias)

AC or
UHST
or TH

NOTES

A1

P, B, S,
N, G

A2

P, B, D,
G

A3

P, B, D,
G

SAMPLE
SIZE / LOT

77

77

77

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST METHOD

ADDITIONAL REQUIREMENTS

0 Fails

JEDEC
J-STD-020
JESD22-A113

Performed on surface mount devices only. PC performed

before THB/HAST, AC/UHST, TC, and PTC stresses. It is
recommended that J-STD-020 be performed to determine
what preconditioning level to perform in the actual PC
stress per JA113. The minimum acceptable level for
qualification is level 3 per JA113. Where applicable,
preconditioning level and Peak Reflow Temperature must
be reported when preconditioning and/or MSL is
performed. Delamination from the die surface in JA113/JSTD-020 is acceptable if the device passes the
subsequent Qualification tests.
Any replacement of
devices must be reported. TEST before and after PC at
room temperature.

0 Fails

JEDEC
JESD22-A101 or
A110

For surface mount devices, PC before THB (85oC/85%RH

for 1000 hours) or HAST (130oC/85%RH for 96 hours, or
110oC/85%RH for 264 hours). TEST before and after
THB or HAST at room and hot temperature.

JEDEC
JESD22-A102,
A118, or A101

For surface mount devices, PC before AC (121oC/15psig

for 96 hours) or unbiased HAST (130C/85%RH for 96
hours, or 110oC/85%RH for 264 hours). For packages
sensitive to high temperatures and pressure (e.g., BGA),
PC followed by TH (85oC/85%RH) for 1000 hours may be
substituted. TEST before and after AC, UHST, or TH at
room temperature.

0 Fails

Page 10 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP A ACCELERATED ENVIRONMENT STRESS TESTS (CONTINUED)
STRESS

Temperature
Cycling

ABV

TC

A4

NOTES

H, P, B,
D, G

SAMPLE
SIZE / LOT

77

NUMBER
OF LOTS

ACCEPT
CRITERIA

0 Fails

TEST
METHOD

JEDEC
JESD22-A104
and Appendix 3

ADDITIONAL REQUIREMENTS
PC before TC for surface mount devices.
Grade 0: -55C to +150C for 2000 cycles or equivalent.
Grade 1: -55oC to +150oC for 1000 cycles or equivalent.
Note: -65oC to 150oC for 500 cycles is also an
allowed test condition due to legacy use with no
known lifetime issues.
Grade 2: -55C to +125C for 1000 cycles or equivalent.
Grade 3: -55C to +125C for 500 cycles or equivalent.
TEST before and after TC at hot temperature. After
completion of TC, decap five devices from one lot and
perform WBP (test #C2) on corner bonds (2 bonds per
corner) and one mid-bond per side on each device.
Preferred decap procedure to minimize damage and chance
of false data is shown in Appendix 3.

Power
Temperature
Cycling

High Temperature
Storage Life

PTC

HTSL

A5

A6

H, P, B,
D, G

H, P, B,
D, G, K

45

45

0 Fails

0 Fails

Page 11 of 42

JEDEC
JESD22-A105

PC before PTC for surface mount devices. Test required

only on devices with maximum rated power 1 watt or TJ
40C or devices designed to drive inductive loads.
Grade 0: Ta of -40C to +150C for 1000 cycles.
Grade 1: Ta of -40C to +125C for 1000 cycles.
Grades 2 and 3: Ta -40C to +105C for 1000 cycles.
Thermal shut-down shall not occur during this test. TEST
before and after PTC at room and hot temperature.

JEDEC
JESD22-A103

Plastic Packaged Parts

Grade 0: +175C Ta for 1000 hours or +150C Ta for
2000 hours.
Grade 1: +150C Ta for 1000 hours or +175C Ta for 500
hours.
Grades 2 and 3: +125C Ta for 1000 hours or +150C Ta
for 500 hours.
Ceramic Packaged Parts
+250C Ta for 10 hours or +200C Ta for 72 hours.
TEST before and after HTSL at room and hot
temperature.
* NOTE: Data from Test B3 (EDR) can be substituted for
Test A6 (HTSL) if package and grade level requirements
are met.

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP B ACCELERATED LIFETIME SIMULATION TESTS
STRESS

ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS
For devices containing NVM, endurance preconditioning
must be performed before HTOL per Q100-005.
Grade 0: +150C Ta for 1000 hours.
Grade 1: +125oC Ta for 1000 hours.
Grade 2: +105C Ta for 1000 hours.
Grade 3: +85C Ta for 1000 hours.
HTOL NOTES:
1) HTOL stress times for the appropriate grade Ta are
the min requirement; the Tj of the test (measured or
calculated ) should be available.
2) Tj may be used instead of Ta when performing HTOL
provided that Tj of the device under HTOL conditions
is equal to or higher than the Tj maximum operating
(Tjopmax) of the particular device, but below the
absolute maximum Tj.
3) If Tj is used to set the HTOL conditions, the minimum
stress of 1000 hours at the Ta of the device is to be
shown using activation energy of 0.7ev or other value
technically justified.
4) Vcc (max) at which dc and ac parametrics are
guaranteed. Thermal shut-down shall not occur during
this test. TEST before and after HTOL at room, cold,
and hot temperature (in that order).

High Temperature
Operating Life

HTOL

B1

H, P, B,
D, G, K

77

0 Fails

JEDEC
JESD22-A108

Early Life Failure

Rate

ELFR

B2

H, P, B,
N, G

800

0 Fails

AEC Q100-008

Devices that pass this stress can be used to populate other

stress tests. Generic data is applicable. TEST before and
after ELFR at room and hot temperature.

NVM Endurance,
Data Retention, and
Operational Life

EDR

B3

H, P, B,
D, G, K

77

0 Fails

AEC Q100-005

TEST before and after EDR at room and hot

temperature. Sample size and lot requirement applies
to EACH of the NVM tests per Q100-005.

Page 12 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP C PACKAGE ASSEMBLY INTEGRITY TESTS
STRESS

Wire Bond Shear

Wire Bond Pull

ABV

NOTES

WBS

C1

H, P, D,
G

WBP

30 bonds from a minimum

of 5 devices

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS

CPK >1.67

AEC
Q100-001
AEC Q003

At appropriate time interval for each bonder to be

used.

CPK >1.67
or 0 Fails
after TC (test
#A4)

MIL-STD883
Method 2011
AEC Q003

Condition C or D. For Au wire diameter 1mil,

minimum pull strength after TC = 3 grams. For
Au wire diameter <1mil, refer to Figure 2011-1 in
MIL-STD-883 Method 2011 as a guideline for
minimum pull strength. For Au wire diameter
<1mil, wire bond pull shall be performed with the
hook over the ball bond and not at mid-wire.
If burn-in screening is normally performed on the
device before shipment, samples for SD must
first undergo burn-in. Perform 8 hour steam
aging prior to testing (1 hour for Au-plated leads).
The customer can request justification for using
dry bake in place of steam aging.

C3

H, P, D,
G

15

>95% lead
coverage

PD

C4

H, P, D,
G

10

CPK >1.67

JEDEC
JESD22-B100
and B108
AEC Q003

See applicable JEDEC standard outline and

individual device spec for significant dimensions
and tolerances.

SBS

C5

5 balls from
a min. of 10
devices

CPK >1.67

AEC
Q100-010
AEC Q003

PC thermally (two 220C reflow cycles) before

integrity (mechanical) testing. Refer to J-STD020 for Pb-free reflow profiles to be used for this
test.

LI

C6

H, P, D,
G

10 leads
from each
of 5 parts

No lead
breakage or
cracks

JEDEC
JESD22-B105

SD

Physical
Dimensions

Lead Integrity

H, P, D,
G

NUMBER
OF LOTS

JEDEC
JESD22-B102
or
JEDEC
J-STD-002D

Solderability

Solder Ball Shear

C2

SAMPLE
SIZE / LOT

Not required for surface mount devices.

required for through-hole devices.

Only

TEST GROUP D DIE FABRICATION RELIABILITY TESTS

ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS

Electromigration

EM

D1

---

---

---

---

---

The data, test method, calculations and internal

criteria should be available to the user upon
request for new technologies.

Time Dependent
Dielectric
Breakdown

TDDB

D2

---

---

---

---

---

The data, test method, calculations and internal

criteria should be available to the user upon
request for new technologies.

STRESS

Page 13 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP D DIE FABRICATION RELIABILITY TESTS (CONTINUED)
STRESS

Hot Carrier Injection

Negative Bias
Temperature
Instability
Stress Migration

ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS

HCI

D3

---

---

---

---

---

The data, test method, calculations and internal

criteria should be available to the user upon
request for new technologies.

NBTI

D4

---

---

---

---

---

The data, test method, calculations and internal

criteria should be available to the user upon
request for new technologies.

SM

D5

---

---

---

---

---

The data, test method, calculations and internal

criteria should be available to the user upon
request for new technologies.

TEST GROUP E ELECTRICAL VERIFICATION TESTS

STRESS

Pre- and Post-Stress

Function/Parameter

Electrostatic
Discharge Human
Body Model

Electrostatic
Discharge Charged
Device Model

ABV

TEST

HBM

CDM

E1

E2

E3

NOTES

H, P, B,
N, G

H, P, B,
D

H, P, B,
D

SAMPLE
SIZE / LOT

All

See Test
Method

See Test
Method

NUMBER
OF LOTS

ACCEPT
CRITERIA

All

0 Fails

Target:
0 Fails
2KV HBM
(Classification 2
or better)

Target:
0 Fails
750V corner
pins, 500V all
other pins
(Classification
C4B or better)

Page 14 of 42

TEST
METHOD

ADDITIONAL REQUIREMENTS

Test program to
supplier data
sheet or user
specification

Test is performed as specified in the applicable

stress reference and the additional requirements
in Table 2 and illustrated in Figure 2. Test
software used shall meet the requirements of
Q100-007. All electrical testing before and after
the qualification stresses are performed to the
limits of the individual device specification in
temperature and limit value.

AEC
Q100-002

TEST before and after ESD at room and hot

temperature.
Device shall be classified
according to the maximum withstand voltage
level.
Device levels <2000V HBM require
specific user approval. Refer to Section 1.3.1.

AEC
Q100-011

TEST before and after ESD at room and hot

temperature.
Device shall be classified
according to the maximum withstand voltage
level. Device levels <750V corner pins and/or
<500V all other pins CDM require specific user
approval. Refer to Section 1.3.1.

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP E ELECTRICAL VERIFICATION TESTS (CONTINUED)
STRESS

Latch-Up

ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS

LU

E4

H, P, B,
D

0 Fails

AEC
Q100-004

See attached procedure for details on how to

perform the test. TEST before and after LU at
room and hot temperature.

30

Where
applicable,
CPK >1.67

AEC
Q100-009
AEC Q003

Supplier and user to mutually agree upon

electrical parameters to be measured and accept
criteria.
TEST at room, hot, and cold
temperature.

Electrical Distributions

ED

E5

H, P, B,
D

Fault Grading

FG

E6

---

---

---

AEC Q100-007
unless otherwise
specified

AEC
Q100-007

For production testing, see Q100-007 for test

requirements.

CHAR

E7

---

---

---

---

AEC Q003

To be performed on new technologies and part

families.

---

SAE J1752/3
Radiated
Emissions

See Appendix 5 for guidelines on determining the

applicability of this test to the device to be
qualified. This test and its accept criteria is
performed per agreement between user and
supplier on a case-by-case basis.

0 Fails

AEC
Q100-012

Applicable to all smart power devices. This

test and statistical evaluation (see Section 4 of
Q100-012) shall be performed per agreement
between user and supplier on a case-by-case
basis.
Applicable to devices with memory sizes
1Mbit SRAM or DRAM based cells. Either
test option (un-accelerated or accelerated) can
be performed, in accordance to the referenced
specifications. This test and its accept criteria is
performed per agreement between user and
supplier on a case-by-case basis. Final test
report shall include detailed test facility location
and altitude data.
Applicable to ALL Pb-free devices. Note the
recommendations for all related solderability,
solder heat resistance and whisker requirements.

Characterization

Electromagnetic
Compatibility

Short Circuit
Characterization

EMC

SC

E9

E10

---

D, G

10

Soft Error Rate

SER

E11

H, P, D,
G

---

JEDEC
Unaccelerated:
JESD89-1
or
Accelerated:
JESD89-2 &
JESD89-3

Lead (Pb) Free

LF

E12

See Test
Method

See Test
Method

See Test
Method

AEC Q005

Page 15 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP F DEFECT SCREENING TESTS
ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

Process Average
Testing

PAT

F1

---

---

---

---

AEC Q001

Statistical Bin/Yield
Analysis

SBA

F2

---

---

---

---

AEC Q002

STRESS

ADDITIONAL REQUIREMENTS
The supplier determines the sample sizes and
accept criteria per the test methods. If these tests
are not possible for a given part, the supplier must
provide justification. The supplier determines the
sample sizes and accept criteria per the test
methods. If these tests are not possible for a given
part, the supplier must provide justification. The
supplier must perform some variant of PAT and
SBA that meets the intent of the guideline.

TEST GROUP G CAVITY PACKAGE INTEGRITY TESTS

STRESS

Mechanical Shock

ABV

NOTES

SAMPLE
SIZE / LOT

NUMBER
OF LOTS

ACCEPT
CRITERIA

TEST
METHOD

ADDITIONAL REQUIREMENTS

MS

G1

H, D, G

15

0 Fails

JEDEC
JESD22-B104

Y1 plane only, 5 pulses, 0.5 msec duration, 1500 g

peak acceleration. TEST before and after at room
temperature.
20 Hz to 2 KHz to 20 Hz (logarithmic variation) in >4
minutes, 4X in each orientation, 50 g peak
acceleration. TEST before and after at room
temperature.

Variable Frequency
Vibration

VFV

G2

H, D, G

15

0 Fails

JEDEC
JESD22-B103

Constant Acceleration

CA

G3

H, D, G

15

0 Fails

MIL-STD-883
Method 2001

Y1 plane only, 30 K g-force for <40 pin packages,

20 K g-force for 40 pins and greater. TEST before
and after at room temperature.

Gross/Fine Leak

GFL

G4

H, D, G

15

0 Fails

MIL-STD-883
Method 1014

Any single-specified fine test followed by any singlespecified gross test. For ceramic packaged cavity
devices only.

DROP

G5

H, D, G

0 Fails

---

Drop part on each of 6 axes once from a height of

1.2m onto a concrete surface. This test is for
MEMS cavity devices only. TEST before and after
DROP at room temperature.

Lid Torque

LT

G6

H, D, G

0 Fails

MIL-STD-883
Method 2024

For ceramic packaged cavity devices only.

Die Shear

DS

G7

H, D, G

0 Fails

MIL-STD-883
Method 2019

To be performed before cap/seal for all cavity

devices.

Internal Water Vapor

IWV

G8

H, D, G

0 Fails

MIL-STD-883
Method 1018

For ceramic packaged cavity devices only.

Package Drop

Page 16 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Legend for Table 2

Notes: H
P
B
N

Required for hermetic packaged devices only.

Required for plastic packaged devices only.
Required Solder Ball Surface Mount Packaged (BGA) devices only.
Nondestructive test, devices can be used to populate other tests or they can be used for
production.
Destructive test, devices are not to be reused for qualification or production.
Required for surface mount plastic packaged devices only.
Generic data allowed. See Section 2.3 and Appendix 1.
Use method AEC-Q100-005 for preconditioning a stand-alone Non-Volatile Memory integrated
circuit or an integrated circuit with a Non-Volatile Memory module.
Required for Pb-free devices only.

Reference Number for the particular test.

All electrical testing before and after the qualification stresses are performed to the limits of the
individual device specification in temperature and limit value.

D
S
G
K

Page 17 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table 3: Process Change Qualification Guidelines for the Selection of Tests

A2
A3
A4
A5
A6
B1
B2
B3
C1
C2
C3

Temperature Humidity Bias or HAST

Autoclave or Unbiased HAST
Temperature Cycling
Power Temperature Cycling
High Temperature Storage Life
High Temperature Operating Life
Early Life Failure Rate
NVM Endurance, Data Retention
Wire Bond Shear
Wire Bond Pull
Solderability

C4
C5
C6
D1
D2
D3
D4
D5
E2
E3
E4

Physical Dimensions
Solder Ball Shear
Lead Integrity
Electromigration
Time Dependent Dielectric Breakdown
Hot Carrier Injection
Negative Bias Temperature Instability
Stress Migration
Human Body Model ESD
Charged Device Model ESD
Latch-up

E5
E7
E9
E10
E11
E12
G1-4
G5
G6
G7
G8

Electrical Distribution
Characterization
Electromagnetic Compatibility
Short Circuit Characterization
Soft Error Rate
Lead Free
Mechanical Series
Package Drop
Lid Torque
Die Shear
Internal Water Vapor

G6

G7

G8
IWV

LT

DS

E E E

G5

D

DROP

G1G4

SER
LF

MECH

E9

E10
E11
E12

SC

E7

G

EMC

E5

M
M

CHAR

E4

TDDB

ED

D2

EM

E3

D1

LI

LU

C6

SBS

E2

C5

PD

Wafer Dimension / Thickness

CDM

C4

SD

D5

C3

WBP

HBM

C2

WBS

DJ

SM

C1

EDR

D4

B3

ELFR

D3

B1
HTOL

M
A M

NBTI

A6
HTSL

Circuit Rerouting

HCI

A5
PTC

B2

A4

A3

TC

A2

Test Abbreviation

AC

Table 2 Test #

THB

Note: A letter or "
" indicates that performance of that stress test should be considered for the appropriate process change. Reason for not
performing a considered test should be given in the qualification plan or results.

DESIGN
Active Element Design

WAFER FAB

Lithography
Die Shrink

DJ

M
M

Metallization / Vias / Contacts

Passivation / Oxide / Interlevel

Dielectric

GN DJ K

M M

Leadframe Plating
Bump Material / Metal System

Leadframe Material

Leadframe Dimension

Diffusion/Doping
Polysilicon

Backside Operation
FAB Site Transfer

DJ

ASSEMBLY
Die Overcoat / Underfill

M
M
M

C

Wire Bonding

Die Scribe/Separate

Die Preparation / Clean

L
L
L

M

H
H

H
H

H
B

Package Marking

H

H

M
M
M

H

New Package

Substrate / Interposer

Assembly Site Transfer

Die Attach
Molding Compound
Molding Process
Hermetic Sealing

A
B
C
D
E

Only for peripheral routing

For symbol rework, new cure time, temp
If bond to leadfinger
Design rule change
Thickness only

F
G
H
J
K

H

H

T

T

H

Page 18 of 42

L
L

MEMS element only

Only from non-100% burned-in parts
Hermetic only
EPROM or E2PROM
Passivation only

L
M
N
Q
T

For Pb-free devices only

For devices requiring PTC
Passivation and gate oxide
Wire diameter decrease
For Solder Ball SMD only

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

Appendix 1: Definition of a Product Qualification Family

AECQ100 provides the following guideline for use of generic data to accelerate and streamline the
qualification process for suppliers and customers. Suppliers and customers can use this guideline to reach
mutual agreement on how to utilize generic data when it is appropriate.
For devices to be categorized in a product qualification family, they all must share the same major product,
process and materials elements as defined below. The qualification of a particular product will be defined
within, but not limited to, the categories listed below. Critical product functional details as defined in Section
A1.1 and critical process steps and materials as defined in Sections A1.2 and A1.3 do not need to be
matched exactly, but shall cover worst cases in application of the family generic data through technical
justification.
All products in the same product qualification family are qualified by association when one family member
successfully completes qualification with the exception of the device specific requirements of Section 4.2.
For broad changes that involve multiple attributes (e.g., site, materials, processes), refer to Section A1.5 of
this appendix and Section 2.3 of Q100, which allows for the selection of worst-case test vehicles to cover all
the possible permutations.
A1.1

Product
a.
b.
c.
d.
e.

Product functionality (e.g., Op-Amp, regulator, microprocessor, Logic - HC/TTL)

Operating supply voltage range(s)
Specified operating temperature range
Specified operating frequency range
Design library cells for the fab technology
Memory IP (e.g., cell structure, building block)
Digital design library cells (e.g., circuit blocks, IO modules, ESD cells) and/or analog design
library cells (e.g., active circuit elements, passive circuit elements) at data sheet voltage
level(s) and at data sheet or better temperature range, and power dissipation
Speed/performance of the library cells
f. Memory type(s) and sizes
g. Design rules for active circuits under pads
h. Other functional characteristics as defined by supplier
For parts specified to operate at different power supplies (e.g., 5.0 V and 3.3 V), product qualification
family data should be presented for both supply ranges.
For parts specified to operate at different temperature range, three (3) lots of data from the product
qualification family at the temperature of the device in the data sheet need to be presented with Table
2 E1 TEST data. Stress classification at the temperature specified Q100 Table 2 groups A, B, E, and
G must be equal or higher than device qualified. Three (3) lots of data from the product family at the
frequency of the device in the data sheet need to be presented with Table 2 E1 TEST data at the
temperature specified Q100 Table 2 groups A, B, E, and G. All memory types must be demonstrated
to be qualified over three (3) lots using largest memory size to be qualified for devices in the family. If
the part to be qualified has a larger memory size than the one already qualified, the supplier must
perform at least one lot of testing on the larger memory configuration.

Page 19 of 42

AEC - Q100 - REV-H

September 11, 2014

Automotive Electronics Council

Component Technical Committee

A1.2

Fab Process
Each process technology (e.g., CMOS, NMOS, Bipolar) must be considered and qualified separately.
No matter how similar, processes from one fundamental fab technology cannot be used for another.
For BiCMOS devices, data must be taken from the appropriate technology based on the circuit under
consideration.
Worst case family requalification with the appropriate tests is required when the process or a
material is changed (see Table A1 for guidelines). The important attributes defining a fab process are
listed below:
a. Wafer Fab Technology (e.g., CMOS, NMOS, Bipolar)
b. Wafer Fab Process - consisting of the same attributes listed below:
Circuit element feature size (e.g., layout design rules, die shrinks, contacts, gates, isolations)
Substrate (e.g., orientation, doping, epi, wafer size)
Number of masks (supplier must show justification for waiving this requirement)
Lithographic process (e.g., contact vs. projection, E-beam vs. X-ray, photoresist polarity)
Doping process (e.g., diffusion vs. ion implantation)
Gate structure, material and process (e.g., polysilicon, metal, salicide, wet vs. dry etch)
Polysilicon material, thickness range & number of levels
Oxidation process and thickness range (e.g., gate & field oxides)
Interlayer dielectric material & thickness range
Metallization material, thickness range & number of levels
Passivation process (e.g., passivation oxide opening), material, & thickness range
Die backside preparation process & metallization
c.

A1.3

Wafer Fab Site

Assembly Process - Plastic or Ceramic

The processes for plastic and ceramic package technologies must be considered and qualified
separately. For devices to be categorized in a qualification family, they all must share the same major
process and material elements as defined below. Family requalification with the appropriate tests is
required when the process or a material is changed. The supplier must submit technical justification
to the user to support the acceptance of generic data with pin (ball) counts, die sizes, substrate
dimensions/material/thickness, paddle sizes and die aspect ratios different than the device to be
qualified. The supplier must possess technical data to justify the acceptance of generic data. The
important attributes defining a qualification family are listed below:
a. Package Type (e.g., DIP, SOIC, PLCC, QFP, PGA, PBGA)
Worst case within same package type (e.g., package warpage due to coefficients of thermal
expansion mismatch)
Range of paddle (flag) size (maximum & minimum dimensions) qualified for the die
size/aspect ratio under consideration
Substrate base material (e.g., PBGA)
b. Assembly Process - consisting of the same attributes listed below:
Leadframe base material
Leadframe plating process & material (internal & external to the package)
Die header / Thermal pad material
Die attach material
Wire bond material & diameter
Wire bond method, presence of downbonds, & process

Page 20 of 42

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Automotive Electronics Council

Component Technical Committee

c.

A1.4

Plastic mold compound material, organic substrate material, or ceramic package material
Solder Ball metallization system (if applicable)
Heatsink type, material, & dimensions
Plastic Mold Compound Supplier/ID
Die Preparation/Singulation

Assembly Site

Qualification/Requalification Lot Requirements

Table A1.1: Part Qualification/Requalification Lot Requirements

Part Information

Lot Requirements for Qualification

New device and no applicable generic data.

A part in a product family is qualified with 3 lots
of generic data. The part to be qualified is less
complex and meets the product Family
Qualification Definition per Appendix 1.
A part in a product family is qualified with 3 lots
of generic data. The part to be qualified is
slightly more complex, with similar product
functionality, meeting the product family
qualification definition per Appendix 1.
Examples for one (1) lot wafer / assembly
qualification, would be, increasing ADC
performance from 12 to 14 bits or package pin
count from 16 to 20.

Lot and sample size requirements per Table 2.

Only device specific tests as defined in Section
4.2 are required. Lot and sample size
requirements per Table 2 for the required tests.

Review Table 3 to determine which tests from

Table 2 should be considered. One (1) lot
wafer / assembly lot and sample sizes per
Table 2 for the required tests.

Part process change.

Review Table 3 to determine which tests from

Table 2 should be considered. Lot and sample
sizes per Table 2 for the required tests.

Part was environmentally tested to all the test

extremes, but was electrically end-point tested
at a temperature less than the Grade required.

The electrical end-point testing on at least 3 lots

(that completed qualification testing) must meet
or exceed the temperature extremes for the
device Grade required. Sample sizes shall be
per Table 2.

Qualification/Requalification involving multiple

sites.

Refer to Appendix 1, Section A1.5.

Qualification/Requalification involving multiple

families.

Refer to Appendix 1, Section A1.5.

Page 21 of 42

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Automotive Electronics Council

Component Technical Committee

Table A1.2: Examples for Generic Data Use

The cases listed in the generic data portion of the table signify those scenarios in which a product and site
combination has been previously qualified and generic data exists. The use options of generic data described
in each case define the allowable generic data for device An in the qualification portion of the table.
Guidelines for using Table A1.2:
1. Product An is a product to be qualified that belongs to Product Family A.
2. Product A1 should be representative of the product family, possibly a more complex case family part
(e.g., 60V regulator vs. 45V regulator, 8 channel vs. 4 channel amplifier) that would cover most, if not
all, other family parts.
3. Same Fab is same process node and materials. Different Fab has one or more different process
elements.
4. Same Assembly is same process, materials and package type. Different Assembly has one or more
different process, material elements or package elements.
5. New test is qualification tests per Section 4.1
6. Fab process C1 is the same as C except for one or more different elements (e.g., Al to Cu metal).
7. Assembly process E1 is the same as E except for one or more different elements (e.g. Al to Cu bond
wire, mold compound).
8. Product B is functionally different from Product A (e.g., logic vs. analog, voltage regulator vs.
amplifier).
9. Increased product complexity can decrease the applicability for portion of the table below.
New Qualification Scenario (Definition of Part to be Qualified)
Case

New
Device /
Product

Description

Product

This is the unqualified

device / product

An

Fab Site

Min. Lots of
Assembly
Product/Process
Data Needed for
Site
(defined in Appendix A1)
Qualification

1 lot ESD and LU; 3 lots

ED AC(E) and 1 lot HTOL
minimum on AnCE in
addition to below for all
cases

Previously Qualified Scenario (Existing Generic Data)

Assembly Lots of Generic
Site
Data Available

Use Options of Generic

Data

Case

Description

Product

Fab Site

B from a different
product family

No Option
3 lots AnCE (new test)

No Option
3 lots using An (new test)

No Option
3 lots AnCE (new test)

No Option
3 lots using An (new test)

2A
B from a different
product family

2B
Different Fab Process
and different site as A1
A1

3
Different Assembly and
different site as A1

Page 22 of 42

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Automotive Electronics Council

Component Technical Committee

Table A1.2: Examples for Generic Data Use (Continued)

Previously Qualified Scenario (Existing Generic Data) (continued)
Case

Description

4A

One or more elements

of the fab process is
different than the base
process
Same Assembly
Process and site as A1
Same Fab Process and
same site as A1

4B

Product

Fab Site

C1

Assembly Lots of Generic

Site
Data Available

3 lots AnCE (new test)

OR
2 lots AnCE (new test)
+ 2 lots A1C1E (generic)
OR
1 lot AnCE (new test)
+ 3 lots A1C1E (generic)

3 lots AnCE (new test)

OR
2 lots A1CE (new test)
+ 2 lots A1CE1 (generic)
OR
1 lot A1CE (new test)
+ 3 lots A1CE1 (generic)

3 lots AnCE (new test)

OR
2 lots AnCE (new test)
+ 2 lots A1CF (generic)
OR
1 lot AnCE (new test)
+ 3 lots A1CF (generic)
3 lots AnCE (new test)
OR
2 lots AnCE (new test)
+ 2 lots A1DE (generic)
OR
1 lot AnCE (new test)
+ 3 lots A1DE (generic)

A1

One or more elements

of the assembly
process is different than
the base process E

E1

Same Fab Process and

site as An
5A

Same Assembly
Process but different
site as An

A1
Same Fab Process, but
different site as An
5B

Use Options of Generic

Data

Same Assembly
Process and site as An
Same Fab Process and
site as An
A1

6
Same Assembly
Process and site as An

Page 23 of 42

3 lots A1CE (Generic)

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Automotive Electronics Council

Component Technical Committee

A1.5

Qualification of Changes in Multiple Sites and Families

A1.5.1 Multiple Sites

When the specific product or process attribute to be qualified or requalified will affect more than one
wafer fab site or assembly site, a minimum of one lot of testing per affected site is required.
A1.5.2 Multiple Families
When the specific product or process attribute to be qualified or requalified will affect more than one
wafer fab family or assembly family, the qualification test vehicles should be: 1) One lot of a single
device type from each of the families that are projected to be most sensitive to the changed attribute,
or 2) Three lots total (from any combination of acceptable generic data and stress test data) from the
most sensitive families if only one or two families exist.
Below is the recommended process for qualifying changes across many process and product
families:
a. Identify all products affected by the proposed process changes.
b. Identify the critical structures and interfaces potentially affected by the proposed process change.
c.

Identify and list the potential failure mechanisms and associated failure modes for the critical
structures and interfaces (see the example in Table A1.3). Note that steps (a) to (c) are
equivalent to the creation of an FMEA.

d. Define the product groupings or families based upon similar characteristics as they relate to the
structures and device sensitivities to be evaluated, and provide technical justification to document
the rationale for these groupings.
e. Provide the qualification test plan, including a description of the change, the matrix of tests, and
the representative products, that will address each of the potential failure mechanisms and
associated failure modes.
f.

Robust process capability must be demonstrated at each site (e.g., control of each process step,
capability of each piece of equipment involved in the process, equivalence of the process stepby-step across all affected sites) for each of the affected process steps.

Table A1.3: Example of Failure Mode/Mechanism List for a Passivation Change

Critical Structure or
Interface

Potential Failure
Mechanism

Passivation to Mold
Compound Interface

Passivation Cracking Corrosion

Mold Compound Passivation Delamination

Passivation to
Metallization Interface
Polysilicon and Active
Resistors

Associated Failure
Modes

On These Products

Functional Failures

All Die

Corner Wire Bond

Failures

Large Die

Stress-Induced Voiding

Functional Failures

Die with Minimum

Width Metal Lines

Ionic Contamination

Leakage, Parametric
Shifts

All Die

Piezoelectric Leakage

Parametric Shifts (e.g.,

Resistance, Gain, Offset)

Analog Products

Page 24 of 42

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Automotive Electronics Council

Component Technical Committee

Appendix 2: Q100 Certification of Design, Construction and Qualification

Supplier Name:

Date:

The following information is required to identify a device that has met the requirements of AEC-Q100. Submission of the
required data in the format shown below is optional. All entries must be completed; if a particular item does not
apply, enter "Not Applicable". This template can be downloaded from the AEC website at http://www.aecouncil.com.

This template is available as a stand-alone document.

1.
2.
3.
4.

5.

6.

7.

8.

9.

10.

11.

Item Name
Users Part Number:
Suppliers Part Number/Data Sheet:
Device Description:
Wafer/Die Fab Location & Process ID:
a. Facility name/plant #:
b. Street address:
c. Country:
Wafer Probe Location:
a. Facility name/plant #:
b. Street address:
c. Country:
Assembly Location & Process ID:
a. Facility name/plant #:
b. Street address:
c. Country:
Final Quality Control A (Test) Location:
a. Facility name/plant #:
b. Street address:
c. Country:
Wafer/Die:
a. Wafer size:
b. Die family:
c. Die mask set revision & name:
d. Die photo:
Wafer/Die Technology Description:
a. Wafer/Die process technology:
b. Die channel length:
c. Die gate length:
d. Die supplier process ID (Mask #):
e. Number of transistors or gates:
f. Number of mask steps:
Die Dimensions:
a. Die width:
b. Die length:
c. Die thickness (finished):
Die Metallization:
a. Die metallization material(s):
b. Number of layers:
c. Thickness (per layer):
d. % of alloys (if present):

Supplier Response

See attached

Page 25 of 42

Not available

AEC - Q100 - REV-H

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Automotive Electronics Council

Component Technical Committee

12. Die Passivation:

a. Number of passivation layers:
b. Die passivation material(s):
c. Thickness(es) & tolerances:
13. Die Overcoat Material (e.g., Polyimide):
14. Die Cross-Section Photo/Drawing:
15. Die Prep Backside:
a. Die prep method:
b. Die metallization:
c. Thickness(es) & tolerances:
16. Die Separation Method:
a. Kerf width (m):
b. Kerf depth (if not 100% saw):
c. Saw method:
17. Die Attach:
a. Die attach material ID:
b. Die attach method:
c. Die placement diagram:
18. Package:
a. Type of package (e.g., plastic, ceramic,
unpackaged):
b. Ball/lead count:
c. JEDEC designation (e.g., MS029,
MS034):
d. Lead (Pb) free (< 0.1% homogenous
material):
e. Package outline drawing:
19. Mold Compound:
a. Mold compound supplier & ID:
b. Mold compound type:
c. Flammability rating:
d. Fire Retardant type/composition:
e. Tg (glass transition temperature)(C):
f. CTE (above & below Tg)(ppm/C):
20. Wire Bond:
a. Wire bond material:
b. Wire bond diameter (mils):
c. Type of wire bond at die:
d. Type of wire bond at leadframe:
e. Wire bonding diagram:
21. Leadframe (if applicable):
a. Paddle/flag material:
b. Paddle/flag width (mils):
c. Paddle/flag length (mils):
d. Paddle/flag plating composition:
e. Paddle/flag plating thickness (inch):
f. Leadframe material:
g. Leadframe bonding plating composition:
h. Leadframe bonding plating thickness
(inch):
i. External lead plating composition:
j. External lead plating thickness (inch):

See attached

Single

Not available

Dual

See attached

Not available

Yes
No
See attached

Not available

UL 94 V1

CTE1 (above Tg) =

See attached

Page 26 of 42

UL 94 V0

CTE2 (below Tg) =

Not available

AEC - Q100 - REV-H

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Automotive Electronics Council

Component Technical Committee

22. Substrate (if applicable):

a. Substrate material (e.g., FR5, BT):
b. Substrate thickness (mm):
c. Number of substrate metal layers:
d. Plating composition of ball solderable
surface:
e. Panel singulation method:
f. Solder ball composition:
g. Solder ball diameter (mils):
23. Unpackaged Die (if not packaged):
a. Under Bump Metallurgy (UBM)
composition:
b. Thickness of UBM metal:
c. Bump composition:
d. Bump size:
24. Header Material (if applicable):
25. Thermal Resistance:
a. JA C/W (approx):
b. JC C/W (approx):
c. Special thermal dissipation construction
techniques:
26. Test circuits, bias levels, & operational
conditions imposed during the suppliers life
and environmental tests:
27. Fault Grade Coverage (%)
28. Maximum Process Exposure Conditions:
a. MSL @ rated SnPb temperature:
b. MSL @ rated Pb-free temperature:
c. Maximum dwell time @ maximum
process temperature:
Attachments:
Die Photo
Package Outline Drawing
Die Cross-Section Photo/Drawing
Wire Bonding Diagram

Not available

%
Not digital circuitry
* Note: Temperatures are as measured on the center of
the plastic package body top surface.
at
C (SnPb)
at
C (Pb-free)

Requirements:
1. A separate Certification of Design, Construction
& Qualification must be submitted for each P/N,
wafer fab, and assembly location.
2. Design, Construction & Qualification shall be
signed by the responsible individual at the supplier
who can verify the above information is accurate
and complete. Type name and sign below.

Die Placement Diagram

Test Circuits, Bias Levels, &
Conditions
Completed by:

See attached

Date:

Certified by:

Typed or
Printed:
Signature:
Title:

Page 27 of 42

Date:

AEC - Q100 - REV-H

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Automotive Electronics Council

Component Technical Committee

Appendix 3: Plastic Package Opening for Wire Bond Testing

A3.1

Purpose
The purpose of this Appendix is to define a guideline for opening plastic packaged devices so that
reliable wire pull or bond shear results will be obtained. This method is intended for use in opening
plastic packaged devices to perform wire pull testing after temperature cycle testing or for bond shear
testing.

A3.2

Materials and Equipment

A3.2.1 Etchants
Various chemical strippers and acids may be used to open the package dependent on your
experience with these materials in removing plastic molding compounds. Red Fuming Nitric Acid has
demonstrated that it can perform this function very well on novolac type epoxies, but other materials
may be utilized if they have shown a low probability for damaging the bond pad material.
A3.2.2 Plasma Strippers
Various suitable plasma stripping equipment can be utilized to remove the plastic package material.
A3.3

Procedure
a. Using a suitable end mill type tool or dental drill, create a small impression just a little larger than
the chip in the top of the plastic package. The depth of the impression should be as deep as
practical without damaging the loop in the bond wires.
b. Using a suitable chemical etchant or plasma etcher, remove the plastic material from the surface
of the die, exposing the die bond pad, the loop in the bond wire, and at least 75% of the bond
wire length. Do not expose the wire bond at the lead frame (these bonds are frequently made to
a silver plated area and many chemical etchants will quickly degrade this bond making wire pull
testing impossible).
c.

Using suitable magnification, inspect the bond pad areas on the chip to determine if the package
removal process has significantly attacked the bond pad metallization. If a bond pad shows
areas of missing metallization, the pad has been degraded and shall not be used for bond shear
or wire pull testing. Bond pads that do not show attack can be used for wire bond testing.

Page 28 of 42

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Component Technical Committee

Appendix 4: Minimum Requirements for Qualification Plans and Results

The following information is required as a minimum to identify a device that has met the requirements of AECQ100 (see Appendix Templates 4A and 4B). Submission of data in this format is optional. However, if these
templates are not used, the supplier must ensure that each item on the template is adequately addressed.
The templates can be downloaded from the AEC website at http://www.aecouncil.com.
A4.1

Plans
1. Part Identification: Customer P/N and supplier P/N.
2. Site or sites at which life testing will be conducted.
3. List of tests to be performed (e.g., JEDEC method, Q100 method, MIL-STD method) along with
conditions. Include specific temperature(s), humidity, and bias to be used.
4. Sample size and number of lots required.
5. Time intervals for end-points (e.g., 0 hour, 500 hour, 1000 hour).
6. Targeted start and finish dates for all tests and end-points.
7. Supplier name and contact.
8. Submission date.
9. Material and functional details and test results of devices to be used as generic data for
qualification. Include rationale for use of generic data.

A4.2

Results
All of above plus:
1.
2.
3.
4.
5.
6.

Date codes and lot codes of parts tested.

Process identification.
Fab and assembly locations.
Mask number or designation.
Number of failures and number of devices tested for each test.
Failure analyses for all failures and corrective action reports to be submitted with results.

Page 29 of 42

AEC - Q100 - REV-H

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Component Technical Committee

Appendix Template 4A: AEC-Q100 Qualification Test Plan

Q100H QUALIFICATION TEST PLAN
USER COMPANY:

DATE:

USER P/N:

TRACKING NUMBER:

USER SPEC #:

USER COMPONENT ENGINEER:

SUPPLIER COMPANY:

SUPPLIER MANUFACTURING SITES:

SUPPLIER P/N:

PPAP SUBMISSION DATE:

SUPPLIER FAMILY TYPE:

REASON FOR QUALIFICATION:

STRESS TEST
Preconditioning
Temperature Humidity Bias or HAST
Autoclave or Unbiased HAST
Temperature Cycle

TEST METHOD

Test Conditions/S.S. per Lot/# REQUIREMENTS

Lots (identify temp, RH, & bias)
S.S
# LOTS

ABV

TEST#

PC

A1

JEDEC J-STD-020

THB / HAST
AC / UHST

A2
A3

JESD22-A101/A110
JESD22-A102/A118

77
77

3
3
3

Peak Reflow Temp. =

Preconditioning used =

Min. MSL = 3

TC

A4

JESD22-A104

77

Power Temperature Cycling

PTC

A5

JESD22-A105

45

High Temperature Storage Life

HTSL

A6

JESD22-A103

45

High Temperature Operating Life

HTOL

B1

JESD22-A108

77

Early Life Failure Rate

NVM Endurance, Data Retention, &
Operational Life
Wire Bond Shear

ELFR

B2

AEC Q100-008

800

EDR

B3

AEC Q100-005

77

WBS

C1

AEC Q100-001

Wire Bond Pull Strength

WBP

C2

MIL-STD-883 - 2011
JESD22-B102
J-STD-002D
JESD22-B100/B108

15

10

8 hr steam aging prior to

testing

Solderability

SD

C3

Physical Dimensions

PD

C4

Solder Ball Shear

SBS

C5

AEC Q100-010

10

LI

C6

JESD22-B105

EM

D1

TDDB

D2

Lead Integrity
Electromigration
Time Dependent Dielectric Breakdown
Hot Carrier Injection

HCI

D3

Negative Bias Temperature Instability

NBTI

D4

SM

D5

Stress Migration
Pre- and Post-Stress Electrical Test

TEST

E1

Test to spec

ESD - Human Body Model

HBM

E2

AEC Q100-002

See Test Method

ESD - Charged Device Model

See Test Method

CDM

E3

AEC Q100-011

Latch-Up

LU

E4

AEC Q100-004

Electrical Distributions

ED

E5

AEC Q100-009

30

Fault Grading
Characterization

FG

E6

AEC-Q100-007

CHAR

E7

AEC Q003

Electromagnetic Compatibility

EMC

E9

SAE J1752/3

Short Circuit Characterization

SC

E10

AEC Q100-012

10

SER

E11

JESD89-1, -2, -3

LF

E12

PAT

F1

15

Soft Error Rate

Lead Free
Process Average Test
Statistical Bin/Yield Analysis

SBA

F2

Hermetic Package Tests

MECH

G1-4

Package Drop

DROP

G5

Lid Torque

LT

G6

Die Shear Strength

DS
IWV

Internal Water Vapor

Q005
AEC Q001
AEC Q002
Series

MIL-STD-883 - 2024

G7

MIL-STD-883 - 2019

G8

MIL-STD-883 - 1018

Approved by:
(User Engineer)

Supplier:

Page 30 of 42

RESULTS
Fails/S.S./# lots

MSL =

AEC - Q100 - REV-H

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Automotive Electronics Council

Component Technical Committee

Appendix Template 4B: AEC-Q100 Generic Data

Objective:
Device:
Cust PN:
Maskset:
Die Size:

Package:
Fab/Assy/Test:
Device Engr:
Product Engr:
Component Engr:

Qual Plan Ref #:

Date Prepared:
Prepared by:
Date Approved:
Approved by:

Test #

ABV

Q100 Test Conditions

End-Point
Requirements

Sample
Size/Lot

# of
Lots

Total #
Units

A1

PC

JEDEC J-STD-020

TEST = ROOM

All surface mount parts prior

to A2, A3, A4, A5

JESD22-A101/A110

TEST = ROOM and

HOT

77

231

JESD22-A102/A118

TEST = ROOM

77

231
231

A4

THB /
HAST
AC /
UHST
TC

JESD22-A104

TEST = HOT

77

A5

PTC

JESD22-A105

TEST = ROOM and

HOT

45

A6

HTSL

JESD22-A103

TEST = ROOM and

HOT

45

77

231

A2
A3

B1

HTOL

JESD22-A108

TEST = ROOM,
COLD, and HOT

B2

ELFR

AEC Q100-008

TEST = ROOM and

HOT

800

2400

77

231

B3

EDR

AEC Q100-005

TEST = ROOM and

HOT

C1

WBS

AEC Q100-001

Cpk>1.5 and in SPC

C2

WBP

C3

SD

MIL-STD-883 2011
JESD22-B102
J-STD-002D
JESD22-B100/B108

>95% solder
coverage

15

15

Cpk > 1.5 per

JESD95

10

30

Two 220C reflow

cycles before SBS

All

C4

PD

C5

SBS

AEC Q100-010

C6

LI

JESD22-B105

D1

EM

D2

TDDB

D3

HCI

D4

NBTI

D5

SM

E1

TEST

E2

HBM

An appropriate time period

for each bonder to be used

10 leads
No lead breakage or
from each
finish cracks
of 5

All parametric and

functional tests

All units

AEC Q100-002

TEST = ROOM and

HOT

Var.

Var.

30

90

1
10
3

1
3
1

1
30
3

All units

1
1
1
1
1
1
1
1

All
All
15
15
15
15
5
5
5
3

E3

CDM

AEC Q100-011

E4

LU

AEC Q100-004

TEST = ROOM and

HOT
TEST = ROOM and
HOT
TEST = ROOM,
HOT, and COLD

E5

ED

AEC Q100-009

E6
E7
E9
E10
E11
E12
F1
F2
G1
G2
G3
G4
G5
G6
G7
G8

FG
CHAR
EMC
SC
SER
LF
PAT
SBA
MS
VFV
CA
GFL
DROP
LT
DS
IWV

AEC Q100-007
AEC Q003
SAE J1752/3
AEC Q100-012
JESD89-1, -2, -3
Q005
AEC Q001
AEC Q002
JESD22-B104
JESD22-B103
MIL-STD-883 2001
MIL-STD-883 1014

All units
TEST = ROOM
TEST = ROOM
TEST = ROOM
TEST = ROOM

MIL-STD-883 2024
MIL-STD-883 2019
MIL-STD-883 - 1018

Part to be
Qualified

15
15
15
15
5
5
5
5

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Differences
Generic
Differences
Generic
Differences
from Q100 Family part A from Q100 Family part B from Q100

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Component Technical Committee

Appendix Template 4B: AEC-Q100 Generic Data (continued)

Part Attributes

Part to be Qualified

Generic Family Part A

User Part Number

Supplier Part Number
A1.1 Product
Product Functionality (e.g., OpAmp, Regulator, Microprocessor,
Logic HC/TTL)
Operating Supply Voltage Range(s)
Specified Operating Temperature
Range
Specified Operating Frequency
Range
1
Analog Design Library Cells (e.g.,
active circuit elements, passive
circuit elements)
1
Digital Design Library Cells (e.g.,
circuit blocks, IO modules, ESD
cells)
Memory IP (e.g., cell structure,
building block)
Memory Type(s) & Size(s)
Design Rules for Active Circuits
under Pads
Other Functional Characteristics
(as defined by supplier)
A1.2 Fab Process
Wafer Fab Technology (e.g.,
CMOS, NMOS, Bipolar)
Circuit Element Feature Size (e.g.,
layout design rules, die shrinks,
contacts, gates, isolations)
Substrate (e.g., orientation, doping,
epi, wafer size)
Maximum Number of Masks
(supplier must show justification for
waiving this requirement)
Lithographic Process (e.g., contact
vs. projection, E-beam vs. X-ray,
photoresist polarity)
Doping Process (e.g., diffusion vs.
ion implantation)
Gate Structure, Material & Process
(e.g., polysilicon, metal, salicide,
wet vs. dry etch)
Polysilicon Material, Thickness
Range, & Number of Levels
Oxidation Process & Thickness
Range (e.g., gate & field oxides)
Interlevel Dielectric Material &
Thickness Range
Metallization Material, Thickness
Range, & Maximum Number of
Levels
Passivation Process (e.g.,
passivation oxide opening),
Material, & Thickness Range
Die Backside Preparation Process
& Metallization
Wafer Fabrication Site

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Generic Family Part B

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Automotive Electronics Council

Component Technical Committee

Appendix Template 4B: AEC-Q100 Generic Data (continued)

Part Attributes

Part to be Qualified

Generic Family Part A

Generic Family Part B

A1.3 Assembly Process Plastic or Ceramic

Assembly Site
Package Type (e.g., DIP, SOIC,
QFP, PGA, PBGA)
Range of Paddle/Flag Size
(maximum & minimum dimensions)
Qualified for the Die Size/Aspect
Ratio Under Consideration
Worst Case Package (e.g.,
package warpage due to CTE
mismatch)
Substrate Base Material (e.g.,
PBGA)
Leadframe Base Material
Die Header / Thermal Pad Material
Leadframe Plating Material &
Process (internal & external to the
package)
Die Attach Material
Wire Bond Material & Diameter
Wire Bond Method, Presence of
Downbonds, & Process
Plastic Mold Compound Material,
Organic Substrate Material, or
Ceramic Package Material
Plastic Mold Compound Supplier/ID
Solder Ball Metallization System (if
applicable)
Heatsink Type, Material, &
Dimensions
Die Preparation/Singulation

Note 1:

Design Library cells need to follow guidelines for temperature ranges, voltage ranges, speed,
performance, and power dissipation as defined in Appendix 1.

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Component Technical Committee

Appendix 5: Part Design Criteria to Determine Need for EMC Testing

A5.1

Use the following criteria to determine if a part is a candidate for EMC testing:
a. Digital technology, LSI, products with oscillators or any technology that has the potential of
producing radiated emissions capable of interfering with communication receiver devices.
Examples include microprocessors, high speed digital IC's, FET's incorporating charge pumps,
devices with watchdogs, and switch-mode regulator control and driver IC's.
b. All new, requalified, or existing IC's that have undergone revisions from previous versions that
have the potential of producing radiated emissions capable of interfering with communication
receiver devices.

A5.2

Examples of factors that would be expected to affect radiated emissions:

Clock drive (internal or external) I/O Drive

Manufacturing process or material composition that reduces rise/fall times (e.g., lower E
dielectric, lower p metallization)
Minimum feature size (e.g., die shrink)
Package or pinout configuration
Leadframe material

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Component Technical Committee

Appendix 6: Part Design Criteria to Determine Need for SER Testing

A6.1

Use the following criteria to determine if a part is a candidate for SER Testing:
a. The part use application will have a significant radiation exposure such as an aviation
application or extended service life at higher altitudes.
b. SER testing is needed for devices with large numbers of SRAM or DRAM cells ( 1 Mbit). For
example: Since the SER rates for a 130 nm technology are typically near 1000 FIT/MBIT, a
device with only 1,000 SRAM cells will result in an SER contribution of ~1 FIT.

A6.2

Examples of factors that would be expected to affect SER results:

a. Technology shrink to small Leffective.
b. Package mold/encapsulate material.
c.

Bump material making die to package connections for Flip Chip package applications.

d. Mitigating factors such as implementation of Error Correcting Code (ECC) and Soft Error
Detection (SED).
A6.3

Cases where new SER testing may be required:

a. Change in basic SRAM/DRAM transistor cell structure (e.g., Leff, well depth and dopant
concentration, isolation method).

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Component Technical Committee

Appendix 7: AEC-Q100 AND THE USE OF MISSION PROFILES

A7.1

SCOPE
Successful completion of the test requirements in Table 2 allows the claim to be made that the
part is AEC Q100 qualified.
Additional testing may be agreed between Component
Manufacturers and Tier 1 Component Users depending on more demanding application
environments. To address these more stringent conditions, application based Mission Profiles
may be used for a reliability capability.
A mission profile is the collection of relevant environmental and functional loads that a component
will be exposed to during its use lifetime.

A7.1.1

Purpose
This appendix provides information on an approach that can be used to assess the suitability of a
component for a given application and its mission profile for unique requirements. The benefit of
applying this approach is that, in the end, the reliability margin between the component
(specification) space and the application (condition) space may be shown.

A7.1.2

Section A7.2 demonstrates the relation between AEC-Q100 stress conditions / durations
and a typical example of a set of use life time and loading conditions.
Section A7.3 describes the approach, supported by flow charts, which can be used for a
reliability capability assessment starting from a mission profile description.

References

SAE J1879/J1211/ZVEI Handbook for Robustness Validation of Semiconductor Devices

in Automotive Applications
JEDEC JEP122 Failure Mechanisms and Models for Semiconductor Devices

A7.2

BASE CONSIDERATIONSE

A7.2.1

Use Lifetime and Mission Profile

The use lifetime assumptions drawn here are an example used for demonstration purpose only.
Many typical mission profiles will differ in one or more characteristics from what is shown below.

service lifetime in years

engine on-time in hours
engine off time { idle} in hours
non-operating time in hours
number of engine on-off cycles
service mileage

The mission profile itself is generated by adding information on thermal, electrical, mechanical
and any other forms of loading under use conditions to the above lifetime characteristics.
Examples of these and how they relate to the test conditions in Table 2 are shown in Table A7.1.
A7.2.2

Relation to AEC-Q100 Stress Test Conditions and Durations

The basic calculations in Table A7.1 for each of the major stress tests demonstrate how one can
derive suitable test conditions for lifetime characteristics based on reasonable assumptions for
the loading. Caution should always be taken on use of excessive test conditions beyond those in
Table 2, because they may induce unrealistic fail mechanisms and/ or acceleration.

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Component Technical Committee

A7.3

METHOD TO ASSESS A MISSION PROFILE

This section demonstrates how to perform a more detailed reliability capability assessment in
cases where the application differs significantly from existing and proven situations:

Application has a demanding loading profile

Application has an extended service lifetime requirement
Application has a more stringent failure rate target over lifetime

These considerations may result in extended test durations. In addition, there may be
components manufactured in new technologies and/or containing new materials that are not yet
qualified. In such cases, unknown failure mechanisms may occur with different times-to-failure
which may require different test methods and/or conditions and/or durations.
For these cases, two flow charts are available to facilitate both Tier 1 and Component
Manufacturing in a reliability capability assessment:

Flow Chart 1 in Figure A7.1 describes the process at Component Manufacturer to assess
whether a new component can be qualified by AEC-Q100.
Flow Chart 2 in Figure A7.2 describes (1) the process at Tier 1 to assess whether a
certain electronic component fulfills the requirements of the mission profile of a new
Electronic Control Unit (ECU); and (2) the process at Component Manufacturer to assess
whether an existing component qualified according to AEC-Q100 can be used in a new
application.

For details on how to apply this method, please refer to SAE J1879, SAE J1211, and/or ZVEI
Handbook for Robustness Validation of Semiconductor Devices in Automotive Applications.
In summary, the flow charts result in the following three clear possible conclusions:
[A]
[B]
[C]

AEC-Q100 test conditions do apply.

Mission Profile specific test conditions may apply.
Robustness Validation may be applied with detailed alignment between Tier1 and
Component Manufacturer.

In addition, not shown in the flow charts, the expected end of life failure rate may be an important
criterion. Regarding failure rates, the following points should be considered:

No fails in 231 devices (77 devices from 3 lots) are applied as pass criteria for the major
environmental stress tests. This represents an LTPD (Lot Tolerance Percent Defective)
= 1, meaning a maximum of 1% failures at 90% confidence level.
This sample size is sufficient to identify intrinsic design, construction, and/or material
issues affecting performance.
This sample size is NOT sufficient or intended for process control or PPM evaluation.
Manufacturing variation failures (low ppm issues) are achieved through proper process
controls and/or screens such as described in AEC-Q001 and AEC-Q002.
Three lots are used as a minimal assurance of some process variation between lots. A
monitoring process has to be installed to keep process variations under control.
Sample sizes are limited by part and test facility costs, qualification test duration and
limitations in batch size per test.

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Component Technical Committee

Figure A7.1: Flow Chart 1 Reliability Test Criteria for New Component

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Component Technical Committee

Figure A7.2: Flow Chart 2 Assessment of Existing, Qualified Component

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Component Technical Committee

Table A7.1: Basic Calculations for AEC-Q100 Stress Test Conditions and Durations
Loading

Mission Profile Input

Stress Test

Stress Conditions

Acceleration Model
(all temperatures in K, not in C)

Model Parameters

Calculated Test
Duration

Q100 Test
Duration

Arrhenius
tu = 12,000 hr
(average operating use
time over 15 yr)
Operation

Thermomechanical

Tu = 87C
(average junction
temperature in use
environment)

nu = 54,750 cls
(number of engine
on/off cycles over 15 yr
of use)
Tu =76C
(average thermal cycle
temperature change in
use environment)

High
Temperature
Operating
Life
(HTOL)

Tt = 125C
(junction
temperature in
test
environment)

Temperature
Cycling
(TC)

Tt = 205C
(thermal cycle
temperature
change in test
environment:
-55C to +150C)

Humidity
(Option 1)

Tu = 32C
(average temperature
in use environment:
9% @ 87C - time on
and 91% @ 27C - time off)

Ea 1 1
= exp
k B Tu Tt

Also applicable for High

Temperature Storage Life (HTSL)
and NVM Endurance, Data
Retention Bake, & Operational Life
(EDR)
Coffin Manson

tu = 131,400 hr
(average on/off time
over 15 yr of use)
RHu = 74%
(average relative
humidity in use
environment)

Temperature
Humidity
Bias
(THB)

RHt = 85%
(relative humidity
in test
environment)
Tt = 85C
(ambient
temperature in
test environment)

Tt
=

Tu

Also applicable for Power

Temperature Cycle (PTC)

Hallberg-Peck
RH
A =
RH

t

Ea 1 1
exp
k B Tu Tt

Also applicable for Highly

Accelerated Steam Test (HAST)
and Unbiased Humidity Steam Test
(UHST). See Notes.

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Ea = 0.7 eV
(activation energy; 0.7 eV is a
typical value, actual values
depend on failure mechanism and
range from -0.2 to 1.4 eV)

tt = 1393 hr
(test time)
1000 hr

kB = 8.61733 x 10-5 eV/K

(Boltzmanns Constant)

m=4
(Coffin Manson exponent; 4 is to
be used for cracks in hard metal
alloys, actual values depend on
failure mechanisms and range
from 1 for ductile to 9 for brittle
materials)

p=3
(Peck exponent, 3 is to be used
for bond pad corrosion)
Ea = 0.8 eV
(activation energy; 0.8 eV is to be
used for bond pad corrosion)
kB = 8.61733 x 10-5 eV/K
(Boltzmanns Constant)

t
= u
Af

nt =1034 cls
(number of cycles
in test)

n=n
t

1000 cls

Af

Tt = 960 hr

tu
Af

1000 hr

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September 11, 2014

Automotive Electronics Council

Component Technical Committee

Table A7.1: Basic Calculations for AEC-Q100 Stress Test Conditions and Durations (continued)
Loading

Mission Profile Input

Stress Test

tu = 131,400 hr
(average on/off time
over 15 yr of use)

Humidity
(Option 2)

RHu = 74%
(average relative
humidity in use
environment)
Tu = 32C
(average temperature
in use environment:
9% @ 87C - time on
and 91% @ 27C - time off)

Highly
Accelerated
Steam
Test
(HAST)

Stress
Conditions

RHt = 85%
(relative
humidity in test
environment)
Tt = 130C
(ambient
temperature in
test environment)

Acceleration Model
(all temperatures in K, not in C)

Hallberg-Peck
RH
A =
RH

t

Ea
exp
kB

1 1

Tu Tt

Also applicable for Temperature

Humidity Bias (THB) and Unbiased
Humidity Steam Test (UHST).
See Notes.

Model Parameters

p=3
(Peck exponent, 3 is to be used
for bond pad corrosion)
Ea = 0.8 eV
(activation energy; 0.8 eV is to be
used for bond pad corrosion)

Calculated Test
Duration

Q100 Test
Duration

Tt = 53 hr

tu
Af

96 hr

kB = 8.61733 x 10-5 eV/K

(Boltzmanns Constant)

Notes:

Autoclave (121C/100%RH) is a highly accelerated test using a saturated moisture condition that will tend to uncover failure mechanisms not seen in normal use conditions. For
this reason, autoclave is not a test whose test conditions can be derived through models and assumptions. The current test conditions were selected decades ago and the test
has been used as part of a standard qualification ever since.

Most Pressure Pot testing is performed with an Al Pressure Pot. Air purging is done at 100C boiling water, and with both steam and liquid escaping from the vent. The chamber
walls are not independently heated at all. Control of the chamber wall temperature; air purging procedure, during ramp-up; ramp-down temperature and pressure and overall
temperature and pressure are key. In addition, when the test is ended the heater is turned off and the vent is opened. It takes about 3 minutes to fully vent the pot. A significant
concern is that venting before the pot chamber drops to 100C, can cause a pressure differential from the >100C residual hot device and cause any water trapped in device void
to create a pop-corning type of delamination.

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Revision History

Rev #

Date of change

June 9, 1994

Initial Release.

May 19, 1995

Added copyright statement. Revised sections 2.3, 2.4.1, 2.4.4, 2.4.5, 2.8,
3.2 and 4.2, Tables 2, 3, 4 and Appendix 1, 2. Added Appendix 3.

Sept. 6, 1996

Revised sections 1.1, 1.2.3, 2.3, 3.1, and 3.2.1, Tables 2, 3, and 4, and
Appendix 2.

Oct. 8, 1998

Revised sections 1.1, 1.1.3, 1.2.2, 2.2, 2.3, 2.4.2, 2.4.5, 2.6, 3.1, 3.2.1,
3.2.3, 2.3.4, 4.1, and 4.2, Tables 3 and 4, Appendix 2, and Appendix 3.
Added section 1.1.1, Figures 1, 2, and 3, and Test Methods Q100-008 and
-009. Deleted sections 2.7 and 2.8.

Aug. 25, 2000

Revised sections 1.1 and 2.3, Figures 2, 3, and 4, Tables 2, 3, and 4,

Appendix 1, and Appendix 2. Added section 2.3.2, Test Methods Q100010 and -011, and Figure 1.

Jan. 31, 2001

Revised Figure 4.

July 18, 2003

Complete Revision.

May 14, 2007

Complete Revision. Revised document title to reflect that the stress test
qualification requirements are failure mechanism based. Revised sections
1, 1.1, 1.2.1, 1.2.2, 1.2.3, 2.3.1, 2.4.4, 2.5, 3.2, 3.2.3, 4.2, and 4.3, Figure
2, Tables 2 and 3, Appendix 2, Appendix 4A, and Appendix 4B. Added
sections 2.1.1, 3.1.1, Table 2 and 3 entries (test #D4, D5, E10, and E11),
Appendix 6, and Test Method Q100-012. Deleted Table 2A.

Sept. 11, 2014

Complete Revision. Revised sections 1.2.1, 1.3.1, 1.3.3, 2.2, 2.3.1, 2.3.3,
2.4.1, 2.4.5, 2.5, and 3.2.3, Figure 2, Tables 1 and 2, Appendix 1,
Appendix 4A, Appendix 4B, and Revision History. Added Revision
Summary, sections 1.2.4, 1.3.2, 1.3.4, 1.3.5, and 3.3, Table 2 and 3 entry
(test #E12), Table 2 Legend (Note L), Tables A1.1 and A1.2, Appendix 7,
Figures A7.1 and A7.2, and Table A7.1. Deleted section 3.1.1, Table 2
and 3 entries (test #E2 and E8).

Brief summary listing affected sections

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