RISC

ARCITECTURES

BY: PRATEEK RAJ GAUTAM

SR.NO.:725/09
M.TECH (ECE)
HBTI
RISC:[1] Reduced Instruction Set Computer as really an old
idea. Some aspects attributed to the first RISC-labeled
designs around 1975 include the observations that the
memory-restricted compilers of the time were often unable
to take advantage of features intended to facilitate manual
assembly coding, and that complex addressing modes take
many cycles to perform due to the required additional
memory accesses. It was argued that such functions would
be better performed by sequences of simpler instructions if
this could yield implementations small enough to leave room
for many registers,[2] reducing the number of slow memory
accesses. In these simple designs, most instructions are of
uniform length and similar structure, arithmetic operations
are restricted to CPU registers and only separate load and
store instructions access memory. These properties enable a
better balancing of pipeline stages than before, making RISC
pipelines significantly more efficient and allowing higher
clock frequencies.
Non-RISC design philosophy :
CISC:[2] Complex Instruction Set Computer
In the early days of the computer industry, programming
was done in assembly language or machine code, which
encouraged powerful and easy-to-use instructions. CPU
designers therefore tried to make instructions that would do
as much work as feasible. With the advent of higher level
languages, computer architects also started to create
dedicated instructions to directly implement certain central
mechanisms of such languages. Another general goal was to
provide every possible addressing mode for every
instruction, known as orthogonality, to ease compiler
implementation. Arithmetic operations could therefore often
have results as well as operands directly in memory (in
addition to register or immediate).
The attitude at the time was that hardware design was more
mature than compiler design so this was in itself also a
reason to implement parts of the functionality in hardware
or microcode rather than in a memory constrained compiler
(or its generated code) alone. This design philosophy
became retroactively termed complex instruction set
computing (CISC) after the RISC philosophy came onto the
scene.
CPUs also had relatively few registers, for several
reasons:[2]

1. More registers also implies more time-consuming

saving and restoring of register contents on the
machine stack.
2. A large number of registers requires a large number
of instruction bits as register specifiers
3. CPU registers are more expensive than external
memory locations; large register sets were
cumbersome with limited circuit boards or chip
integration.

An important force encouraging complexity was very limited

main memories (order of kilobytes). It was therefore
advantageous for the density of information held in
computer programs to be high, leading to features such as
highly encoded, variable length instructions, doing data
loading as well as calculation

An equally important reason was that main memories were

quite slow; by using dense information packing, one could
reduce the frequency with which the CPU had to access this
slow resource. Modern computers face similar limiting
factors: main memories are slow compared to the CPU and
the fast cache memories employed to overcome this are
instead limited in size. This may partly explain why highly
encoded instruction sets have proven to be as useful as
RISC designs in modern computers.

ISSUES WITH CISC[5]

  2-operand format.
 where instructions have a source and a
destination.
 Register to register,
 register to memory, &
 memory to register
 Multiple addressing modes for memory.
 Variable length instructions.
 length varies according to addressing mode.
 Instructions which require multiple clock cycles to
execute.
 Small number of general purpose registers.
 So we need instructions which can operate on
memory
 Very large no of instructions.
 Hard to remember.
 Only 20% are used in 80% of program.
 Implementing code is difficult
 (which increase design time)
 Size of package increase
 (which requires more Silicon & increase
cost).

Search for RISC

  Longer programs & use of Compilers.
 The majority of CISC instructions were rarely used.
 Some complex instructions were slower than a group of
simple instructions performing an equivalent task
 Too many instructions for designers to optimize
each one

RISC design philosophy[3]

In the mid 1970s researchers (particularly John Cocke) at
IBM (and similar projects elsewhere) demonstrated that the
majority of combinations of these orthogonal addressing
modes and instructions were not used by most programs
generated by compilers available at the time. It proved
difficult in many cases to write a compiler with more than
limited ability to take advantage of the features provided by
conventional CPUs.

It was also discovered that, on microcoded implementations

of certain architectures, complex operations tended to be
slower than a sequence of simpler operations doing the
same thing. This was in part an effect of the fact that many
designs were rushed, with little time to optimize or tune
every instruction, but only those used most often
one of the most significant characteristics of RISC
processors was that external memory was only accessible by
a load or store instruction. All other instructions were limited
to internal registers. This simplified many aspects of
processor design: allowing instructions to be fixed-length,
simplifying pipelines, and isolating the logic for dealing with
the delay in completing a memory access (cache miss, etc)
to only two instructions. This led to RISC designs being
referred to as load/store architectures
Characteristic features of RISC[1]
 One cycle execution time:
 RISC processors have a CPI (clock per instruction)
of one cycle.
 Uses a load-store architecture
 Pipelining:
 A technique that allows simultaneous execution of
parts or stages of instructions.
 Large number of general purpose registers:
 Reduce interactions with memory
 Hardwired

Load/Store Architecture[1]
 Individual instructions to store/load data and to
perform operations
 All operations are performed on operands in registers
 Main memory is used only to load/store instructions
Programming issues[1]

CX=AX+BX
 CISC:
1. ADD AX,BX
2. MOV BX,CX
*BX is overwritten

*Delay in MOV

 RISC:
1. ADD AX,BX,CX
 [2]
MIPS:
An example of RISC
Microprocessor without Interlocked Pipelining Stage
 Smaller and simpler instruction set
 111 instructions
 One cycle execution time
 Pipelining
 32 registers
 32 bits for each register
MIPS Instruction Set
 25 branch/jump instructions
 21 arithmetic instructions
 15 load instructions
 12 comparison instructions
 10 store instructions
 8 logic instructions
 8 bit manipulation instructions
 8 move instructions
 4 miscellaneous instructions
MISC/RISC Pipeline Stages
 Fetch instruction
 Decode instruction
 Execute instruction
 Access operand
 Write result
Pipelining in Mips[3]

2 instructions in 10 T-states

5 instructions in 9 T-states
RISC Disadvantages
 Size of program is long.
 Burden on the software programmer.
 Now, CISC microprocessors are becoming fast and
cheap so it is not justified to burden programmer.

Why CISC Persists

 Most Intel and AMD chips are CISC x86
 Most PC applications are written for x86
 Intel spent more money on research to improving the
performance of their chips
References:

[1] A.K.Ray & K.M.Bhurcjandi, Advanced Microprocessors

and Peripherals, Second Edition. New Delhi, Tata McGraw
Hill Publishing Company Limited, 2008, 585

[2] Reduced instruction set computing, Wikipedia, [online],

available:
http://en.wikipedia.org/wiki/Reduced_instruction_set_comp
uting, april2010

[3] Lloyd Borrett, RISC versus CISC, Australian Personal

Computer, [online], available:
http://www.borrett.id.au/computing/art-1991-06-02.htm,
april 2010

[4] Richard Murray, RISC vs CISC, [online], available:

http://www.heyrick.co.uk/assembler/riscvcisc.html, april
2010

[5] BARRY B. BREY, The Intel Microprocessors. Singapore:

Pearson Education: Sixth Edition,2006