Design of 4 watt Power Amplifier

Sanjib Kumar Mandal 1, V N singh2

1-2

Defence Electronics Application laboratory, DRDO

Dehradun-248001, Uttarakhand
1

[email protected]
2

[email protected]

Abstract This paper presents the design and

implantation of a linear 4 watt power amplifier at S-band. The
power amplifier has been realized using FR4 substrate with
relative permittivity (r) of 4.3 in microstrip line configuration. A
GaN HEMT transistor is selected for the design and
implementation of power amplifier. Load and source pull
techniques are used to find the optimum impedances at
maximum power added efficiency (PAE) and output power. A
band pass filter at the desired output frequency of 40 MHz
bandwidth is incorporated to achieve the required spurious and
harmonic rejection and a high power T/R switch is also employed
at the output for transreceive selection. The complete amplifier
circuit is simulated and optimized in Advanced Design system
software. A good linearity performance is achieved for final
output power of +36 dBm with harmonic suppression below 45
dBc.

power amplifier include class D, class E, class F. The trade

offs between the biasing and switched mode power amplifier
are linearity and efficiency [4,5]. The amplifier is biased to
provide the necessary power, gain and linearity performance.
The output matching circuit is determined such that the
necessary compression point, saturated power or PAE is
achieved. This is done by simulation and optimization of the
required parameter from the device model.

Keywords Band pass filter, GaN, HEMT, Power amplifier,

PAE, S-Band.

II. DESIGN METHODOLOGY

The deign objective is to achieve maximum flat gain across
the frequency band of interest with the transistor operating at a
prescribed nominal RF output power level. The design
procedure is illustrated in the following subsections for the
following design specification.

I. INTRODUCTION
Power amplifier is the one of key components to affect the
performance of any communication system. Due to the growth
of communication system market power amplifier
requirements have become more important with regard to
system performance.Wide bandgap transistors such as gallium
nitride high electron mobility transistor (GaN HEMT) have
been recently introduced commercially. These devices, which
operate at voltage range of 28 to 50 volts, offer much higher
RF power densities than either GaAs MESFETs or LDMOS
FETs [2, 3]. Apart from offering smaller size, the transistors
have low capacitance per watt, very high transconductance
which offer high gain as well as the capability of being
operated over wide bandwidth.[1]
Moreover GaN based transistor offer high input and
output impedances as results the design of matching network
of the power amplifier becomes easier. Other than this, GaN in
particular is noteworthy due to its high operating frequency
and high thermal conductivity also. Therefore, in this design
5W GaN HEMT part no NPTB0004A transistor model from
NITRONEX is used.
Generally, power amplifier can be classified as
biasing class and switching class. Biasing class includes class
A, class B, class AB and class C where class is defined by the
DC bias condition and the conduction angle. Switch mode

In this paper a class AB amplifier based on NPTB0004A

is designed with an operating frequency of 2680 MHz with 40
MHz bandwidth. Power amplifier device of 5 watt has been
chosen to compensate the loss of bandpass filter and T/R
switch so that final output of the complete module is 4 watt.

TABLE I
POWER AMPLIFIER SPECIFICATION

Sl.
No.
1
2
3
4
5

Parameter

Specification

Frequency range
RF output
Spurious
Harmonics
PA Class

268020 MHz
+36 dBm
45 dBc(min)
45 dBc(min)
AB

A. Transistor Modeling and Characterization

The frequency range is S-band from 2660 MHz
to 2700 MHz; therefore a DC to 6 GHz Nitronex, 5W
transistor is used as the active device. The parasitic of the
transistor need to be carefully modelled to take care of
package of transistor with base chip.
Thus the computeraided design (CAD) based
modelling can be conducted with a combination of bare chip
model & the package model, which are provided by the
manufacturer. Load line simulations are done using advanced
design system (ADS) software. The DC curves are shown in
the following figure.1

TABLE II
OPTIMUM SOURCE & LOAD IMPEDANCE

Sl.
No.
1

Fig. 1 Simulated I-V characteristics of the device.

B. Matching Network
The matching networks are designed for impedance
transformation, typically between the transistor and 50 Ohm
terminations on the input/output of the device. Generally,
input matching side provides for maximum power transfer,
which occurs according to complex conjugate theorem and
gives low input return loss. On the other hand output matching
network is designed according to required output power at
load for desired output frequencies. The amplifier matching
configuration is shown in fig.2 as given below.

Frequency

ZS()

ZL()

2680 MHz

5.0-j10

13-j12

The source & load impedance to be matched with 50

impedance. For this design single stub impedance matching is
used. The matching networks were designed using Matching
networks synthesis utility available in ADS software. Initial
matching network i.e. stub length & width were adjusted
using optimization tool until the specific small signal gain was
achieved for required bandwidth.
C. Bias-Network Design
Bias network design for the amplifier is designed at
center frequency of its operational bandwidth. A quarter
wavelength line (/4) along with radial stub immediately after
it which provides proper isolation, no matter what component
is added after high impedance /4 long bias line. The
following figure shows the circuit design for bias circuit with
resistor and capacitor to ground which results shows perfect
bias network between 2.660 GHz to 2.680 GHz.

Fig .2. Amplifier matching design configuration

A Loadull measurement will help the designer to

determine the optimum load impedance ZL. This technique is
based on varying the load impedance while simultaneously
measuring the output power. The input match is adjusted each
time as well to ensure a well-matched condition at the input of
the amplifier. Load pull simulations can be done in ADS
using HB1Tone_Loadpull design guide with a Largesignal/non-linear model of the transistor. Figure 3 shows the
simulation setup and resulting load-pull contours for output
power.

Fig 4. Distributed Bias Network and its response.

D. Stability Analysis
The stability analysis is prime important in the
designing of the power amplifier. There are various stability
configurations which could be used to stabilize the circuit, the
most popular being using resistive loading of the circuit.
Figure below shows the simulated stability factor (Mu) after
stabilization which shows the circuit is unconditionally stable
at operating frequency. Adding inductor to stabilization circuit
maintain device noise performance.

Fig .3. Load Pull Simulation & Power contours in smith chart

Optimum source & Load impedance at 2700 MHz for 6 watt

saturated power & 17 dB gain is tabulated below.

Fig 5. Simulation results for stability analysis.

III. AMPLIFIER PERFORMANCE EVALUATION

Amplifier performance was evaluated by connecting
all the designed sub-network & optimized the overall circuit.
Figure 7 shows the complete amplifier schematic in ADS
software with biasing circuit.

V. PA IMPLANTATION
The designed PA is fabricated on FR4 substrate ( r =
4.3) PCB board on microstrip line with 1.6 mm substrate
thickness and dielectric loss tangent (tandD) of 0.02. A low
pass filter after driver stage output & a high power (10 watt)
T/R switch FMS2031-001 at final output is incorporated .The
complete PCB assembly will be mounted on a copper fixture
with proper heat sink arrangement. The complete PA module
schematic, its TOI performance & harmonic resposnse are
given in the following figure below. The results meet the
required design specification for the system.

Fig .6. Final Schematic with bias circuit & matching network

Using the schematic of the amplifier PAE and output

power is simulated using Harmonic Balance. Input power is
swept from 0 to 30 dBm, it is observed that the device is
driven into saturation and maximum linear output power is 37
dBm for input power of 20 dBm and a gain 17 dB at 2.68
GHz. The simulation results are shown below.

Fig .7. Plot of Gain Compression & Power Added Efficiency

IV. BAND PASS FILTER

The hairpin resonator filter is selected to implement the
bandpass filter at the output of power amplifier. It is easy to
manufacture because it has open circuited ends that require no
grounding. The design is derived from the edge coupled
resonator filter by folding back the ends of the resonator into a
U shape which reduces length significantly The detail
design procedure [6] is beyond the scope of this paper. The
simulation schematic and optimized results for hairpin filter
are shown below.

Fig .9. Power Amplifier Schematic & IMD results

VI. CONCLUSIONS
In this paper design and simulation of a linear class
AB power amplifier based on a GaN HEMT is presented. For
the design Gallium Nitride device NPTB0004A from Nitronex
is used as the power device. A novel method load/source pull
analysis is utilized to determine the optimum load and source
impedance at fundamental frequency. The design amplifier
has PAE of 55.37 % for final output power 4.0 W and gain of
the order of 17 dB at 28 Volt. This high efficiency power
amplifier can be used for satellite communication &
Integrated Coastal Surveillance System (ICSS) application.
ACKNOWLEDGMENT
The authors express their sincere gratitude and thanks to
Dr. R.S. Pundir, Director DEAL for his kind permission to
publish the paper. Authors are thankful to shri S.O.Gupta,
Group Head, Radio Frequency System Group for useful
technical discussions. We are very grateful to PCB design
group & CAME group for fabricating the hardware of power
amplifier.
REFERENCES
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[6]
Fig .8. ADS Simulation Schematic of hairpin filter & its response

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