EE214 Digital Logic Design

Lab Exercise #4: Basic Logic Minimization Techniques

Revision: February 7, 2003

Overview

This lab presents the concepts and techniques needed to find minimal expressions of logic relationships
using the “pencil-and-paper” techniques of Boolean algebra and Karnaugh Maps. The concept of
inconsequential input combinations to combinational circuits that result in “don’t care” output
conditions is also examined.

Background

SOP and POS circuits

The terms “product” and “sum” have long been borrowed from mathematics to describe AND and OR
logic operations. A product term is defined as an AND relationship between any number of variables
(e.g., A.B.C, as well as X.Y, are both product terms), and a sum term is defined as an OR relationship
between logic variables (so A+B and X+Y+Z are sum terms). Any logic system can be represented in
two logically equivalent ways: as the OR’ing of AND’ed terms, known as the Sum Of Products
(SOP) form; or as the AND’ing of OR’ed terms, known as the Product of Sums (POS) form. The two
forms are interchangeable, and one form can be transformed to the other following a few basic rules.
As an example, consider the XOR relationship YSOP = (not A and B) or (A and not B). This SOP
relationship can be expressed in POS form as YPOS = (A or B) and (not A or not B). In this example,
the POS and SOP forms are equally simple, but this is not always the case. For circuits with more than
two inputs, it may turn out that one form is simpler that the other. If a circuit is to be constructed, it
makes sense to evaluate both forms so that the simplest one can be constructed.

A B Y A A
0 0 0 B B
0 1 Y Y
1
1 0 1
1 1 0
XOR cicuit (SOP form) XOR cicuit (POS form)
XOR truth table
Y=A B+A B Y = (A + B) (A + B)

Contains material C Digilent, Inc. 8 Pages

digilent, inc.
www.digilentinc.com
Lab #4: Basic Logic Minimization Techniques Page 2

Truth tables and logic circuits

A truth table is the most basic and concise way to represent the input/output requirements of a given
logic system. A truth table shows each combination of inputs for which an output should be asserted. A
logic equation (and therefore a logic circuit) can easily be constructed from any truth table by applying
the rules presented below.

For SOP circuits:

• A circuit for a truth table with N input columns can use AND gates with N inputs;
• A truth table with M rows in which the output is a ‘1’ can use M AND gates and an M-input
OR gate;
• Every truth table row with a ‘1’ in the output column produces an AND term in the logic
equation (or, equivalently, an AND gate in the logic circuit);
• Inputs to the AND term are inverted if the input shows a ‘0’ on the row, and inputs are not
inverted if the input shows a ‘1’ on the row;
• All AND terms are connected to an M-input OR gate, and the OR output is the function output.
A B C
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0 Y
1 0 1 1
1 1 0 0
1 1 1 0 Y=A B C + A B C + A B C

And for POS circuits:

• A circuit for a truth table with N input columns can use OR gates with N inputs;
• A truth table with M rows in which the output is a ‘0’ can use M OR gates and an M-input
AND gate;
• Every truth table row with a ‘0’ in the output column produces an OR term in the logic
equation (or, equivalently, an OR gate in the logic circuit);
• Inputs to the OR term are inverted if the input shows a ‘1’ on the row, and inputs are not
inverted if the input shows a ‘0’ on the row;
• All OR terms are connected to an M-input AND gate, and the AND output is the function
output.
Lab #4: Basic Logic Minimization Techniques Page 3
A
A B C Y B
0 0 0 0 C
0 0 1 1
0 1 0 0
Y
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

Y = (A+B+C) (A+B+C) (A+B+C) (A+B+C) (A+B+C)

In the SOP circuit shown above, every product term contains all three input variables. Likewise, in the
POS circuit, every sum term contains all three input variables. Product terms that contain all input
variables are known as minterms, and sum terms that contain all input variables are known as
maxterms. A minterm or maxterm number can be assigned to each row in a truth table if the input 1’s
and 0’s on a given row are interpreted as a binary number. Thus, the SOP equation above contains
minterms 1, 3, and 5, and the POS equation contains maxterms 0, 2, 4, 6, and 7. In an SOP equation, an
input value of ‘1’ creates a non-inverted variable in the minterm (and ‘0’ creates an inverted variable).
This defines a minterm code that associates each minterm with a corresponding truth table row. In a
POS equation, an input value of ‘1’ creates an inverted variable (and ‘0’ creates a non-inverted
variable). This defines a maxterm code that associates every maxterm with a particular truth table
row.

Minimizing logic systems

If a logic circuit must be constructed according to the input/output relationship specified in a truth
table, then it is desirable to find a minimal logic equation, and therefore a minimal circuit, that
expresses the relationship. For example, it would be simpler to construct the SOP circuit shown above
than the POS circuit. But the logic equation and circuit below also produce the same behavior as the
SOP equation and circuit above, and clearly, the circuit below is more economical to produce.

A
C
Y= A C +B C Y
B

A minimal logic equation for a given logic system can be obtained by eliminating all non-essential or
redundant inputs. Any input that can be removed from the equation without changing the input/output
relationship is redundant, so to find minimal equations, all redundant inputs must be identified and
removed. In the truth table above, note the SOP terms generated by rows 1 and 3. The A input is ‘0’ in
both rows, and the C input is ‘1’ in both rows, but the B input is ‘0’ in one row and ‘1’ in the other.
Thus, for these two rows, the output is a ‘1’ whether B is a ‘0’ or ‘1’ and B is therefore redundant.

The goal in “minimizing” logic systems is to find the simplest form by identifying and removing all
redundant inputs. For now, the simplest form will be defined as the one that uses the fewest number of
Lab #4: Basic Logic Minimization Techniques Page 4
logic gates (or, if two forms use the same number of gates, then the one that uses the fewest number of
N
total inputs to all gates will be considered the simplest). For a logic function of N inputs, there are 22
logic functions, and for each of these functions, there exists a minimum SOP form and a minimum
POS form (and there may be more than one minimum SOP and/or POS form). The SOP form may be
more minimal than the POS form, or the POS form may be more minimal, or they may be equivalent
(i.e., they may both require the same number of logic gates and inputs). In general, it is difficult to
identify the minimum form by simply staring at a truth table. Several methods have evolved to assist
with the minimization process, including the application of Boolean algebra, the use of logic graphs,
and the use of searching algorithms. Although any of these methods can be employed using pen and
paper, it is far easier (and more productive) to implement searching algorithms on a computer. Thus,
only Boolean algebra and logic graphs are presented in this lab exercise.

Boolean Algebra

Boolean algebra is perhaps the oldest method used to minimize logic equations. It provides a formal
algebraic system that can be used to manipulate logic equations in an attempt to find more minimal
equations. It is a proper algebraic system, with three set elements {‘0’, ‘1’, and ‘A’} (where ‘A’ is any
variable that can assume the values ‘0’ or ‘1’), two binary operations (and or intersection, or or union),
and one unary operation (inversion or complementation). Operations between sets are closed under the
three operations. The basic laws governing and, or, and inversion operations are easily derived from
the logic truth tables for those operations. The associative, commutative, and distributive laws can be
directly demonstrated using truth tables. Only the distributive law truth table is shown; the simpler
associative and commutative law truth tables can be easily derived.

AND operations OR operations INV operations

Truth table Laws Truth table Laws Truth table Laws
0·0=0 A·0 =0 0+0=0 A+0 =A 0' = 1 A'' = A
1·0=0 A·1 =A 1+0=1 A+1 =1 1' = 0
0·1=0 A·A =A 0+1=1 A+A =A
1·1=1 A · A' = 0 1+1=1 A + A' = 1

Associative Laws Commutative Laws Distributive Laws

(A·B)·C = A·(B·C) = A·B·C A·B = B·A A·(B+C) = (A·B) + (A·C)
(A+B)+C = A+(B+C) = A+B+C A+B = B+A A+(B·C) = (A+B) · (A+C)

Truth tables to verify distributive laws

A B C A+B B+C A+C A·B B·C A·C A·(B+C) (A·B)+(A·C) A+(B·C) (A+B)·(A+C)
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 0 0 0 0 0 0 0
0 1 0 1 1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 0 1 0 0 0 1 1
1 0 0 1 0 1 0 0 0 0 0 1 1
1 0 1 1 1 1 0 0 1 1 1 1 1
1 1 0 1 1 1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1
Lab #4: Basic Logic Minimization Techniques Page 5
AND’ing operations take precedence over OR’ing operations. Parenthesis can be used to eliminate any
possible confusion. Thus, the following two sets of equations show equivalent logic equations.

A·B+C = (A·B) + C A+B·C = A + (B·C)

Demorgan’s Law provides a formal algebraic statement for the property observed in defining the
conjugate gate symbols: the same logic circuit can be interpreted as implementing either an AND or an
OR function, depending how the input and output voltage levels are interpreted. Demorgan’s law,
which is applicable to logic systems with any number of inputs, states

(A·B)’ = A’ + B’ (nand form) and (A+B)’ = A’·B’ (nor form).

The circuits below also serve illustrate these laws.

A Vdd A B C A B C

GND

These are These are

A equivalent
equivalent
A

GND

A These are These are

equivalent equivalent
1

A Associative Laws Commutative Laws

1 A A
B B
Y Y
AND / OR Laws These are These are
C C
equivalent equivalent
A A
Y Y
B B
C C
Distributive Laws

XOR Boolean Algebra

The XOR relationship “F = A xor B” is defined by the equivalent logic expression “F = A·B’ + A’·B”.
The XOR function is somewhat unique among logic operations – it is frequently encountered in logic
designs, and it is possible to design an XOR circuit that uses only 6 transistors (whereas the A’·B +
A·B’ circuit would require 16 transistors). Any expression that contains an XOR relationship can
always be rewritten in the A’·B + A·B’ form, and then the laws of Boolean algebra introduced above
can be used to find a simpler equation. But it is also possible to define laws for XOR equations that can
be used to directly simplify XOR equations.
Lab #4: Basic Logic Minimization Techniques Page 6

The table below defines the basic laws for XOR algebra. The associative, commutative, and
distributive XOR laws can be obtained directly from the AND/OR laws above by simply substituting
XOR for AND and XNOR for OR. As with the AND/OR laws, all XOR laws can be easily verified
through the use of truth tables.

XOR operations XNOR operations

Truth table Laws Truth table Laws
0 xor 0 = 0 A xor 0 = A 0 xnor 0 = 1 A xnor 0 = A’
1 xor 0 = 1 A xor 1 = A’ 1 xnor 0 = 0 A xnor 1 = A
0 xor 1 = 1 A xor A = 0 0 xnor 1 = 0 A xnor A = 1
1 xor 1 = 0 A xor A' = 1 1 xnor 1 = 1 A xnor A' = 0

One useful application of the XOR function is the “controlled inverter” circuit illustrated below. The
truth table, derived directly from the XOR truth table, assumes an XOR function where one input is
tied to a signal named “control”. When control is a ‘1’, the input A is inverted, but when control is a
‘0’, A is simply passed through the logic gate without modification. This controlled inversion function
will be useful in later work.

A B F Control A F
0 0 0 0 0 0
0 1 1 0 1 1 Control Y
A
1 0 1 1 0 1
Controlled Inverter
1 1 0 1 1 0
XOR truth Controlled inverter
table truth table

By definition, the XNOR function results from inverting the XOR function output. But notice in the
XOR truth table above, if either of the A or B inputs were inverted, the XNOR output would result as
well. Restated as a logic equation, if “F = A xor B”, then “F’ = A xnor B”, and “F’ = A’ xor B”.
Notice also that if both inputs A and B were inverted, then the output column would again show the
XOR function output. Restated, if “F = A xor B, then also “F = A’ xor B’”.
A B C F
Shown on the left is the truth table for a 3-input XOR function. Notice that the
output F shows the expected XOR output for inputs B and C in the first four 0 0 0 0
rows, where the A input is a ‘0’. Then in the last four rows where A is a ‘1’, F 0 0 1 1
is the inverse of the expected pattern (it is the XNOR of B and C). This 0 1 0 1
general pattern repeats for any number of XOR inputs, with the general result
0 1 1 0
that the XOR function output is asserted whenever an odd number of inputs
are asserted. Thus, with respect to the number of asserted input signals, an 1 0 0 1
XOR function is an “odd detector”, and an XNOR function is an “even 1 0 1 0
detector”. 1 1 0 0
These observations lead to a version of DeMorgan’s Laws that hold for XOR 1 1 1 1
functions of any number of inputs: XOR truth table
Lab #4: Basic Logic Minimization Techniques Page 7

(A xor B)’ = A’ xor B = A xor B’ = A’ xor B’ = A xnor B

(A xnor B)’ = A’ xnor B = A xnor B’ = A’ xnor B’ = A xor B
and also

(A xor B xor C xor D)’ = A’ xor B xor C xor D = A xnor B xor C xor D = A xor B’ xor C xor D, etc.

Note that a single input inversion can be moved to any other signal in a multi-input XOR circuit
without changing the logical result. Note also that any signal inversion can be replaced with a non-
inverted signal and an XNOR function. These properties will be useful in later work.

The following examples illustrate the use of Boolean Algebra to find simpler logic equations.

Examples to be added – refer to text.

Problem 1. Use the laws of Boolean algebra to minimize the logic equations in the lab submission
form.

Logic Graphs

Truth tables are not very useful for minimizing logic systems, and Boolean algebra has limited utility.
Logic graphs offer the easiest and most useful pen-and-paper methods of minimizing logic systems. A
logic graph and truth table contain identical information, but patterns that indicate redundant inputs can
be readily identified in a logic graph. A logic graph is a two (or even three) dimensional construct that
contains exactly the same information that a truth table does, but arranged in an array structure so that
all logic domains are contiguous, and logic relationships are therefore easy to identify. Information in a
truth table can easily be recast into a logic graph. The figure below shows how a three-input truth table
is mapped to an 8-cell logic graph; the numbers in the logic graph cells are the numbers in the truth
table rows.

A B C Y C=1
0 0 0
0 0 1
0 1 0 000 001 011 010
0 1 1
1 0 0
A=1 100 101 111 110
1 0 1
1 1 0
1 1 1 B=1

Note there is a 1-to-1 correspondence between the cells in the logic graph and the rows in a truth table,
and that the cell numbers have been arranged so that each logic variable domain is represented by a
group of four connected cells (the A domain is a row of four cells, and the B and C domains are
squares of four cells). This particular arrangement of cells in the logic graph isn’t the only one
possible, but it has the useful property of having each domain overlap the others in exactly two cells.
As can be seen in the figure below, the logic domains are contiguous in the logic graph, but they are
Lab #4: Basic Logic Minimization Techniques Page 8
not contiguous in the truth table. It is the contiguous logic domains in the logic graphs that make them
so useful.

Logic graphs are typically shown with variable names A B C Y A B C Y A B C Y

near the graph borders, and 1’s and 0’s near cell rows and 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 1 0
columns to indicate the value of the variables for the rows 0 1 0 1 0 1 0 1 0 1 0 1
and columns. The logic graph below shows a typical 0 1 1 1 0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 0 1 0 0 0
appearance. Note that the variable values on the logic
1 0 1 1 1 0 1 1 1 0 1 1
graph edges can be read from left to right to find the truth 1 1 0 0 1 1 0 0 1 1 0 0
table row that corresponds to a given cell. For example, 1 1 1 1 1 1 1 1 1 1 1 1
the shaded cell below is in the A = 1, B = 1, C= 0 cell,
which corresponds to row 110 in the truth table. A domain B domain C domain

The information in the output column of the truth table

below has been transferred row-for-cell into the cells of
the logic graph, and so the truth table and logic graph
contain identical information. In
the logic graph, 1’s that appear A B C Y B C
adjacent to one another (either 0 0 0 0 00 01 11 10
vertically or horizontally) are A
0 0 1 0
said to be “logically adjacent”,
and these adjacencies represent
0 1 0 1 0 0 0 1 1
opportunities to find and 0 1 1 1
eliminate redundant inputs. Logic 1 0 0 0
graphs used in this manner are 1 0 1 1
1 0 1 1 0
called Karnaugh Maps (or just K- 1 1 0 0
Maps) after their inventor. 1 1 1 1

The figure below shows a four-

input truth table mapped to a 16-cell K-map.

C=1
A B C D Y CD
0 0 0 0 0
0 0 0 1 0 AB 00 01 11 10
0 0 1 0 0 0000 0001 001 1 001 0
0 0 1 1 1 00 0 0 1 0
0 1 0 0 1
0 1 0 1 1 0100 0101 011 1 011 0
0 1 1 0 0 01 1 1 0 0
0 1 1 1 0 B=1
1 0 0 0 0
1 0 0 1 1 1100 1101 111 1 111 0
11 0 0 1 0
1 0 1 0 0
1 0 1 1 1 A=1
1 1 0 0 0 1000 1001 101 1 101 0 10 0 1 1 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
D=1

A four-input Row-to-cell mapping of a 4-variable A 4-input, 16 cell K-map

truth table truth table to a 16-cell logic graph for the truth table shown
Lab #4: Basic Logic Minimization Techniques Page 9
The key to using K-maps to find and eliminate redundant inputs from a logic system is to identify
“groups” of 1’s for SOP equations or groups of 0’s for POS equations. A valid group must be a “power
of 2” size (meaning that only groups of 1, 2, 4, 8, 16, etc. are allowed), and it must be a row, column,
square, or rectangle, but not a diagonal, dogleg, or other irregular shape. Each ‘1’ in a SOP K-map
must participate in at least one group, and each ‘1’ must be in the largest possible group (and likewise
for 0’s in POS maps). Note that this requirement, that all 1’s (or 0’s) are grouped in the largest possible
group, may mean that some 1’s (or 0’s) are part of several groups. In practice, loops are drawn on a K-
map to encircle the 1’s (or 0’s) in a given group. Once all 1’s (or 0’s) in a map have been grouped in
the largest possible loops, the grouping process is complete and a logic equation can be read directly
from the K-map. If the procedure is performed correctly, a minimal logic equation is guaranteed.

SOP logic equations are read from a K-map by writing product terms defined by each loop, and then
OR’ing the product terms together. Likewise, POS logic equations are read from a K-map by writing
sum terms defined by each loop, and then AND’ing all the sum terms together. A loop term is defined
by the logic variables on the periphery of the K-map. SOP loop terms use minterm codes (i.e., the ‘0’
domain of a variable results in that variable being complemented in the product term for the loop), and
POS loop terms use maxterm codes (i.e., the ‘1’ domain of an input variable results in that variable
being complemented in the sum term for the loop). If a loop spans across both the ‘1’ and ‘0’ domain
of a given logic variable, then that variable is redundant and it does not appear in the loop term.
Restated, a logic variable is included in a loop term only if the loop is contained entirely in the ‘1’ or
‘0’ domain of that variable. The edges of maps are continuous with the opposite edges, so loops can
span from one edge to the other without grouping 1’s or 0’s in the middle (the examples below
illustrate this process).

Kmap for FSOP = B'.C + A.C Kmap for FSOP = A'.D' + B.C + A

BC CD
A 00 01 11 10 AB 00 01 11 10 This loop (A'.D') spans
arcoss map edges
0 0 1 0 0 00 1 0 0 1

1 0 1 1 0 01 1 0 1 1
Three of the 1's in the
B.C group appear in
This loop is entirely in the B'.C domain,
11 1 1 1 1 more than one loop.
but it crosses the A / A' boundary (so A This allows the '1' in cell
is not in the loop equation) 10 1 1 1 1 7 to be grouped in the
largest possible group.
This loop is entirely in the A.C domain, but it This loop crosses all
crosses the B / B' boundary (so B is not in the domains except A
loop equation)

K-maps can be used for finding minimal logic expressions for systems of 2, 3, 4, 5, or 6 input variables
(beyond 6 variables and the technique becomes unwieldy). For systems of 2, 3, or 4 variables, the
technique is straightforward, and it is illustrated in several examples below. In general, the looping
process should be started with 1’s (or 0’s) that can only be grouped in one possible loop. As loops are
drawn, ensure that all 1’s (or 0’s) are in at least one loop, and that no redundant loops exist (a
redundant loop contains 1’s or 0’s that are all already grouped in other loops).
Lab #4: Basic Logic Minimization Techniques Page 10

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 1 1 0 0 0 1 1 1 0 0 1 0 0 1

1 0 1 1 0 1 0 1 0 0 1 0 1 0 0

FSOP = A B + A C FSOP = A B + A C + B C FSOP = A C + A B C

FPOS = (A + B)(A + C) FPOS = (A + C)(A + B)(B + C) FPOS = (A + C)(A + C)(B + C

BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10

0 1 0 0 1 0 1 0 1 1 0 1 1 1 1

1 1 1 1 1 1 1 0 0 1 1 0 0 1 1

FSOP = A + C FSOP = C + A B FSOP = A + B

FPOS = (A + C) FPOS = (B + C)(A + C) FPOS = (A + B)

CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10

00 0 1 0 0 00 1 1 1 1 00 1 0 0 0

01 0 1 0 0 01 0 0 0 0 01 0 0 0 1

11 1 1 1 1 11 0 1 1 0 11 1 1 1 1

10 0 1 0 0 10 1 1 1 1 10 0 0 0 0

FSOP = A B + C D FSOP = B + A C FSOP = A B C D + B C D + A B

FPOS = (A + D)(A + C)(B + D)(B + C) FPOS = (A + B)(B + D) FPOS = (A + B + C)(A + D)(A + B + C)(A + B)

CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10

00 0 1 1 1 00 1 1 0 1 00 1 0 0 0

01 1 1 1 1 01 0 1 0 0 01 1 1 1 0

11 1 1 1 1 11 0 1 0 0 11 1 1 0 1

10 0 0 0 0 10 1 1 1 1 10 0 1 0 0

FSOP = A D + A C + B FSOP = C D + A B + B D FSOP = ACD+ ABD + ABD + ACD

FPOS = (A + B)(B + C + D) FPOS = (B + D)(B + C)(A + C + D) FPOS = (A+B+D)(A+C+D)
(A+C+D)(A+B+C)
Lab #4: Basic Logic Minimization Techniques Page 11
For systems of 5 or 6 variables, two different methods can be used. One method uses 4-variable K-
maps nested in 1 or 2 variable “super maps”, and the other method uses “map entered variables”. The
super-map technique for finding minimum equations for 5 or 6 variables closely follows the technique
used for 2, 3, or 4 variables, but 4-variable maps must be nested into 1 or 2-variable super-maps as
shown below. Logic adjacencies between the sub-maps can be discovered by identifying 1’s (or 0’s) in
like-numbered cells in adjacent super-map cells. The grayed cells in the maps show examples of
adjacent cells in the K-maps. SOP equations for the sparsely populated maps contain the product terms
shown – note that the “super map” variables do not appear in product terms when 1’s are located in
like-numbered cells in the sub maps.

F
E E 0 1
CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 1 00 00 1

0 01 1 0 01 1 01

11 11 11

10 10 10

CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 00 00

01 1 01 1 01 1
1 1
11 11 11

10 1 10 10

Y = ABCDE + ABCDE + ABCD Y = ABCDEF + ABCDF + ABCDE

Problem 2. Loop the K-maps in the lab submission form, showing the minimal SOP or POS
equation as required.

Incompletely specified logic functions (don’t cares)

Situations can arise where a circuit has N input signals, but not all 2N combinations of inputs are
possible. Or, if all 2N combinations of inputs are possible, some combinations might be irrelevant. For
example, consider a television remote control unit that can switch between control of a television,
VCR, or DVD. Some remotes might have operational modes where buttons like “fast forward” are
physically switched out of the circuit; other remotes may use modes where such buttons are left in the
circuit, but their functions are irrelevant. In either case, some combinations of input signals are
completely inconsequential to the proper operation of the circuit. It is possible to take advantage of
these situations to further minimize logic circuits.
Lab #4: Basic Logic Minimization Techniques Page 12

Input combinations that cannot possibly effect the proper operation of a logic system can be allowed to
drive circuit outputs high or low – literally, the designer doesn’t care what the circuit response is to
these impossible or irrelevant inputs. This information is encoded by using a special “don’t care”
symbol in truth tables and K-maps to indicate that the signal can be a ‘1’ or a ‘0’ without effecting
circuit operation. Some sources use an “X” to indicate a don’t care, but this can be confused with a
signal named “X”. It is perhaps a better practice to use a symbol that is not normally associated with
signal names – here, we choose the “φ” symbol.

The truth table on the right shows two output

BC
functions (F and G) for the same three inputs. A B C F G A 00 01 11 10
Both outputs have two rows where the output is a
0 0 0 0 1
don’t care. This same information is also shown 0 0 1 1 φ
in the associated K-maps. In the “F” K-map, the 0 0 1 1 φ
designer “don’t care” if the output is a ‘1’ or a ‘0’ 1 0 1 φ 0
0 1 0 φ 1
for minterms 2 and 7, and so cells 2 and 7 in the F
K-map can be looped as either a ‘1’ or a ‘0’. 0 1 1 0 φ
Clearly, looping cell 7 as a ‘1’ and cell 2 as a ‘0’ 1 0 0 1 1 BC
results in a more minimal logic circuit. In this 1 0 1 0 0 A 00 01 11 10
case, both an SOP and POS looping would result
in identical circuits. 1 1 0 0 0 0 1 φ φ 1
1 1 1 φ 0
1 1 0 0 0
In the “G” K-map, the don’t cares in cells 1 and 3
can be looped as either a ‘1’ or a ‘0’. In an SOP G
looping, both don’t cares would be looped as 1’s, giving a logic function
of “G = A’ + B’·C’”. In a POS looping, however, cells 1 and 3 would be looped as 0’s, giving the logic
function “G = C’·(A’ + B’). A little Boolean algebra reveals these two equations are not algebraically
equal. Often, the SOP and POS forms of equations looped from K-maps that contain don’t cares are
not algebraically equal (although they would perform identically in the circuit). The following
examples illustrate the use of don’t cares in K-maps.

BC
A 00 01 11 10
CD
0 0 1 1 1
AB 00 01 11 10
1 0 φ φ 0 00 1 1 φ 1

FSOP = C + A B FPOS = A (B + C) 01 0 0 φ 0

BC 11 0 φ 1 0
A 00 01 11 10
10 1 1 1 φ
0 1 0 φ 1

1 1 φ 1 1 FSOP = B + C D

FPOS = (A + B) (B + D)
FSOP = A + C FPOS = (A + C)
Lab #4: Basic Logic Minimization Techniques Page 13

Problem 3. Loop the K-maps in the lab submission form, showing the minimal SOP or POS
equation as required.

Map entered variables

To be added – refer to text

Problem 4. Loop the K-maps in the lab submission form, showing the minimal SOP or POS
equation as required.

Lab Procedure Part 1: K-map Battleship (35 points)

Five digital inputs can generate 25 or 32 unique input patterns. A five input digital circuit could
therefore be in one of 32 unique “states”, where each state is defined by a particular input pattern. In
this exercise, a circuit is designed to illuminate an output LED whenever the five input switches are set
in one of twelve (out of the possible 32) patterns. Which twelve input patterns cause the LED to
illuminate depends on a given circuit's design. Each person will design a unique circuit, and only they
will know which twelve switch patterns will illuminate the output LED. Once a circuit has been
constructed and tested, a neighboring student will attempt to discover the illuminating switch patterns
by sliding the input switches (one at a time) to a new position. The goal is to design a circuit that forces
the “competition” to take as many moves as possible to find the illuminating switch positions. A
second goal is to devise a method that can be used to find the 12 switch patterns in another’s circuit
with a minimum number of moves. The winner for each lab section is the person who finds the twelve
illuminating positions in another's circuit in a minimum number of moves, and in the event of a tie
forces the visitor to take the greatest number of moves to discover the twelve positions.

The only rule is that your circuit must use exactly three product or sum terms, and each term must have
three input variables. An empty 32-cell K-map (or rather two linked 16-cell K-maps) can be used to
specify the circuit. A '1' should be placed in twelve of the 32 cells, and the remaining 20 cells should
get a '0'. When placing 1's, be sure that each 1 can be looped in a group of four. Once a circuit has been
specified using the K-maps as described, it must be captured using the Xilinx schematic capture tool,
and then thoroughly simulated. After the design has been verified in the simulator, it can be
downloaded to the Digilab board.

Problem 5. Specify a 5-input, one output circuit for this lab using the K-maps in the submission
form. When you load 1’s and 0’s into the K-maps to specify your circuit, try to choose
patterns of cells that will be the hardest to guess (you will probably want to experiment
with several patterns). You may want to print several copies of the K-maps in the
submission form to assist in experimenting with possible circuit designs. Try several
patterns, keeping in mind that you want your opponent to use a maximum number of
moves to find all minterms. When you have decided on a circuit, enter the minterms for
the circuit you wish to construct in the submitted K-map. Loop out minimum cover
from the final K-map, and enter your circuit into the Xilinx schematic capture tool. In
your circuit, name the inputs A,B,C,D, and E, and name the output OUT. Simulate the
circuit with all 32 input patterns, and verify that it behaves correctly in all cases. Print
and submit the circuit schematic and simulator output.
Lab #4: Basic Logic Minimization Techniques Page 14
Problem 6. Download the completed circuit to the Digilab board, and thoroughly test it. If it is
working correctly, the output LED should only be ON when the input switches are set
in one of the twelve patterns corresponding to the minterms (or maxterms) in your
circuit. After your circuit has been verified, invite a neighboring student to attempt to
locate all the minterms in your circuit (i.e., all the 1’s or 0’s in your K-map). The visitor
may request that the five input switches be set to any initial pattern (you may want to
shield the LEDs when setting the initial pattern to avoid giving away information).
Then, the visitor may begin hunting for your 1's by sliding the input switches one at a
time to new positions. Each time a switch is moved to a new position (setting the first
input pattern does not count as a move), the visitor can use their “offense” K-map to
record whether a 0 or 1 was discovered in each visited cell of your K-map. The visitor
keeps changing the input pattern until all the 1’s have been discovered.

After all 1’s have been discovered, change roles. When you are probing your neighbor’s
map to find all the 1's, remember that as you slide one input switch at a time, you are
crossing a logic boundary. To avoid wasting steps, you should cross logic boundaries
according to a sound strategy. This means plotting a course through the K-map that
doesn’t touch the same cell twice. You will, of course, need to adjust your path as you
gain information. Try to establish some good strategic rules to follow before game
time. Use your “offense” K-map to chart your progress through your visitees map.

Both parties should keep track of the number of moves required to find all the 1's in the
others K-maps. If all 1’s and 0’s were entered in all visited K-map cells, then the
number of non-empty cells can simply be counted. Write the number of moves the
visitor required to find all of your 1’s in the submission form, as well as the number of
moves it took for you to find all the 1’s in the map you visited.

Problem 7. When you have finished probing each others maps for minterms, set the input switches
in your circuit to any input pattern where the LED is off, and then record the time it
takes your neighbor to visit each of the 20 “LED OFF” cells in your K-map exactly
once. Your neighbor can refer to their “offense” K-map for this exercise. Plot your
neighbor’s course through your map (you can use your “design” map to track progress),
and for each cell visited more than once, add 4 seconds to their time, and add six
seconds each time the output LED is illuminated. Record their time (plus penalties) in
the submission form, and then change roles. When you have completed your course
through your neighbors map, record your time (plus penalties) as well.

Lab procedure part 2 (40 points)

In part 2, four relatively simple circuits will be implemented, but only after K-map circuit
minimization techniques have been used to simplify them. By performing minimization techniques
prior to constructing a circuit, simpler forms of the circuit can be discovered and implemented without
affecting the required logical behavior of the circuit. Keep in mind that when searching for a minimal
circuit, both SOP and POS forms should be considered.
Lab #4: Basic Logic Minimization Techniques Page 15

Problem 8. A sequence of numbers is shown in the “I” column in the table on I Y

the right (the sequence restarts at “0”). Design a circuit that can 0 1
output the next 4-bit binary number in the sequence when any 1 3
given number in the sequence is input. The table shows the 3 14
14 7
input/output requirements as decimal numbers – note that for any
7 8
given input number, the output is the next number in the sequence.
8 2
These numbers must be implemented in a digital circuit as 4-bit 2 15
binary numbers composed of four distinct logic signals. If the four 15 11
bits of the input binary number are represented by logic signals I3, 11 10
I2, I1, and I0, and the four bits of the output binary number are 10 6
represented as logic signals Y3, Y2, Y1, and Y0, then a truth table 6 12
can be prepared showing the required relationships between the 12 0
four input signals and the four output signals. K-maps can then be 0 1
prepared from the truth table to find minimal circuits. etc.

Start this problem by completing the truth table in the lab submission form. Then, based
on the truth table, complete the four 4-variable K-maps (one K-map for each “Y” output
signal). Use the K-maps to minimize the logic functions Y3, Y2, Y1, and Y0, and
implement the circuit using the Xilinx schematic capture tool and the Digilab board.
Use four slide switches as inputs and 4 LEDs as outputs. Test the circuit, and confirm
that you can read the correct 4-bit binary number from the LEDs. Print and submit the
circuit and the simulation waveforms, and have the lab assistant inspect your work.

Problem 9. Use the Xilinx schematic capture tool to implement minimal SOP and POS circuits for
the following equations. Print and submit the schematics and simulation waveforms
(you don’t need to download these circuit to the Digilab board).

F = AB + BC’ + A’B’C’ G(A,B,C,D) = Σ m(0, 1, 4, 5, 7, 13, 15)

Problem 10. Use the schematic capture tool to implement and simulate a circuit that can detect all
prime numbers less than 15. Assume that the four inputs to your circuit (B3B2B1B0) are
used to form a four-bit binary number in the range 0 to 15. Your circuit should
illuminate an LED whenever the input binary number is a prime number. Begin by
completing the K-map (or, if you wish, start with a truth table), then extract minimum
SOP and POS circuits, and then implement the circuit that requires the fewest number
of transistors. After you have verified the circuit through simulation, download it to the
Digilab board, using four slide switches as inputs, and a single LED as output. Note that
this circuit can co-reside in the Digilab board with the circuit from problem 8 if you use
different slide switches for the inputs and a different LED for the output. Print and
submit the schematic and the simulator output, and have the lab assistant inspect your
circuit.