Computer

System
Organization
Lab

Divjot Singh
262/CO/12

INDEX
S.No
1
2

Experiment
Model a simple AND gate using dataflow modeling. Write the testbench to test the
system. Verify the functionality from the output waveform.
(a) Model a 1-bit Fulladder using dataflow modeling. Use this to build an 8-bit ripple
carry adder using structural modeling. (b) Implement a 4-bit adder using + operator
for std_logic_vector data types. Use this to build a 1-digit BCD adder. (c) Use for
generate statement to implement Part (a). (d) Implement an Array Multiplier to
multiply two 8-bit numbers using the 8-bit fulladdders.
(a) Implement a 2-to-4 Decoder using conditional signal assignment statement with
enable facility. Use it to construct a 4-to-16 decoder. (b) Model a 4-to-1 multiplexor
using Selected Signal Assignment statement. Use it to build 16-to-1 multiplexor. (c)
Implement a 1-bit comparator having 5 inputs (two 1-bit inputs being compared and
three 1-bit comparison result bits of previous stage) and 3 outputs (namely eq, lt, gt).
Connect 8 such units to model an 8-bit comparator using generate statement. The 3
outputs of a stage go to its next stage as inputs.

Implement an 8-bit Arithmetic Logic Unit to perform basic arithmetic (add, sub, inc,
dec) and logical (or, and, xor, not) operations using structural modeling that uses a
component of 1-bit fulladder and multiplexor.

Model a combinational circuit in VHDL that performs either shift left, or shift right, or
rotate left or rotate right by 1-bit operations on its input. Do not use the predefined
gates/shift/rotate operators.

Model an S-R flip-flop using structural modeling using programmer-defined NAND gates
as components.

Model an edge triggered D flip-flop with asynchronous reset facility. Use it to model 8bit Parallel-In- Parallel-Out register. Now add preset facility to the DFF and use it to
model a Ring Counter.

Implement a Serial Adder using a D flip-flop and a fulladder.

Model a T flip-flop. Use it model a Mod-10 Up-Down counter.

10

Implement an n-bit Shift-left register using generic facility of VHDL.

11

Implement the Booths Multiplication Algorithm, Restoring Division Algorithm in VHDL.

12

Implement a Register file of 8-bit wide 16 registers with two read ports and a write
port.

13

Implement a 3-bit Gray Code counter using Finite State Machine modeling method.

14

Model a Moore machine based circuit having single serial input and a single output that
gives an output 1 whenever it detects 0101 bit sequence in its input stream.

15

Implement a 16 byte ROM with some predefined data in its locations.

16

Implement a 1Kx8 RAM with bidirectional data lines.

Sign

Question 1
Code
entity andCKT is
port (
x,y : in bit;
z : out bit
);
end entity;
architecture andCKT_arch of andCKT is
begin
z <= x and y;
end andCKT_arch;

Test Bench
entity andckt_test is
end entity;
architecture andckt_test_arch of andckt_test is
component andCKT is
port (
x,y : in bit;
z : out bit
);
end component;
signal test_x,test_y,test_z : bit;
begin
inst0: andCKT port map(test_x,test_y,test_z);
process begin
test_x <= '0';
test_y <= '0';
wait for 10 ns;
test_x <= '1';
wait for 10 ns;
test_y <= '1';
wait for 10 ns;
test_x <= '0';
wait for 10 ns;
end process;
end andckt_test_arch;

Question 2 (a)
Components
entity fa1bit is
port(
x,y,cin : in bit;
sum,cout : out bit
);
end entity;
architecture fa1bit_arch of fa1bit is
begin
sum <= x xor y xor cin;
cout <= (x and y) or (x and cin) or (y and cin);
end fa1bit_arch;
Code
entity fa8bit_nogen is
port(
xin,yin : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit
);
end entity;
architecture fa8bit_nogen_arch of fa8bit_nogen is
component fa1bit is
port(
x,y,cin : in bit;
sum,cout : out bit
);
end component;
signal carry : bit_vector(8 downto 0);
begin
carry(0) <= '0';
INST0: fa1bit port map(xin(0),yin(0),carry(0),sum_out(0),carry(1));
INST1: fa1bit port map(xin(1),yin(1),carry(1),sum_out(1),carry(2));
INST2: fa1bit port map(xin(2),yin(2),carry(2),sum_out(2),carry(3));
INST3: fa1bit port map(xin(3),yin(3),carry(3),sum_out(3),carry(4));
INST4: fa1bit port map(xin(4),yin(4),carry(4),sum_out(4),carry(5));
INST5: fa1bit port map(xin(5),yin(5),carry(5),sum_out(5),carry(6));
INST6: fa1bit port map(xin(6),yin(6),carry(6),sum_out(6),carry(7));
INST7: fa1bit port map(xin(7),yin(7),carry(7),sum_out(7),carry(8));
c_out <= carry(8);
end fa8bit_nogen_arch;

Test Bench
entity fa8bit_nogen_test is end entity;
architecture fa8bit_nogen_test_arch of fa8bit_nogen_test is
component fa8bit_nogen is
port(
xin,yin : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit
);
end component;
signal test_x,test_y,test_sum:bit_vector(7 downto 0);
signal test_cin,test_cout:bit;
begin
inst0 : fa8bit_nogen port map(test_x,test_y,test_cin,test_sum,test_cout);
process
begin
test_x <= "10101010";
test_y <= "01010101";
wait for 50 ns;
test_x <= "00001111";
test_y <= "00000101";
wait for 50 ns;
end process;
end fa8bit_nogen_test_arch;

Question 2 (b)
Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fa4bit_std_logic is
port(
xin,yin : in std_logic_vector(3 downto 0);
carryin : in std_logic;
sout : out std_logic_vector(3 downto 0);
carryout : out std_logic
);
end entity;
architecture fa4bit_std_logic_arch of fa4bit_std_logic is
signal temp_result : std_logic_vector(4 downto 0);
begin
temp_result <= '0'&xin + yin + carryin;
sout <= temp_result(3 downto 0);
carryout <= temp_result(4);
end fa4bit_std_logic_arch;

Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fa4bit_std_logic_test is end entity;
architecture fa4bit_std_logic_test_arch of fa4bit_std_logic_test is
component fa4bit_std_logic is
port(
xin,yin : in std_logic_vector(3 downto 0);
carryin : in std_logic;
sout : out std_logic_vector(3 downto 0);
carryout : out std_logic
);
end component;
signal test_x,test_y,test_sum : std_logic_vector(3 downto 0);
signal test_cin,test_cout : std_logic;
begin
inst0: fa4bit_std_logic port map(test_x,test_y,test_cin,test_sum,test_cout);
process
begin
test_x <= "0101";
test_y <= "1010";
test_cin <= '0';
wait for 50 ns;
test_y <= "0101";
wait for 50 ns;
end process;
end fa4bit_std_logic_test_arch;

Question 2 (c)
Code
entity fa8bit is
port(
xin,yin : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit
);
end entity;
architecture fa8bit_arch of fa8bit is
component fa1bit is
port(
x,y,cin : in bit;
sum,cout : out bit
);
end component;
signal carry : bit_vector(8 downto 0);

begin
carry(0) <= '0';
SUM_GEN :
for I in 0 to 7 generate
INST: fa1bit port map(xin(I),yin(I),carry(I),sum_out(I),carry(I+1));
end generate SUM_GEN;
c_out <= carry(8);
end fa8bit_arch;
Test Bench
entity fa8bit_test is end entity;
architecture fa8bit_test_arch of fa8bit_test is
component fa8bit is
port(
xin,yin : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit
);
end component;
signal test_x,test_y,test_sum:bit_vector(7 downto 0);
signal test_cin,test_cout:bit;
begin
inst0 : fa8bit port map(test_x,test_y,test_cin,test_sum,test_cout);
process
begin
test_x <= "10101010";
test_y <= "01010101";
wait for 50 ns;
test_x <= "00001111";
test_y <= "00000101";
wait for 50 ns;
end process;
end fa8bit_test_arch;

Question 2 (d)
Code
entity multiplier8x8 is
port (
aIn,bIn : in bit_vector(7 downto 0);
product : out bit_vector(15 downto 0)
);
end entity;
architecture multiplier8x8_arch of multiplier8x8 is
component fa8bit is
port(
xin,yin : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit
);
end component;
signal temp0,temp1,temp2,temp3,temp4,temp5,temp6,temp7,
sum0,sum1,sum2,sum3,sum4,sum5,sum6,sum7,carry,
tsum0,tsum1,tsum2,tsum3,tsum4,tsum5,tsum6,tsum7 : bit_vector(7 downto 0);
begin
-- Getting all the partial products
A0 :
for I in 0 to 7 generate
temp0(7-I) <= (aIn(0)and bIn(7-I));
temp1(7-I) <= (aIn(1)and bIn(7-I));
temp2(7-I) <= (aIn(2)and bIn(7-I));
temp3(7-I) <= (aIn(3)and bIn(7-I));
temp4(7-I) <= (aIn(4)and bIn(7-I));
temp5(7-I) <= (aIn(5)and bIn(7-I));
temp6(7-I) <= (aIn(6)and bIn(7-I));
temp7(7-I) <= (aIn(7)and bIn(7-I));
end generate A0;
-- Initializing inputs of FAs and first carry
sum0 <= temp0;
carry(0) <= '0';
tsum0 <= carry(0)&sum0(7 downto 1);
tsum1 <= carry(1)&sum1(7 downto 1);
tsum2 <= carry(2)&sum2(7 downto 1);
tsum3 <= carry(3)&sum3(7 downto 1);
tsum4 <= carry(4)&sum4(7 downto 1);
tsum5 <= carry(5)&sum5(7 downto 1);
tsum6 <= carry(6)&sum6(7 downto 1);

-- Adding all partial products

INST1 : fa8bit port map(tsum0,temp1,carry(0),sum1,carry(1));
INST2 : fa8bit port map(tsum1,temp2,carry(0),sum2,carry(2));
INST3 : fa8bit port map(tsum2,temp3,carry(0),sum3,carry(3));
INST4 : fa8bit port map(tsum3,temp4,carry(0),sum4,carry(4));
INST5 : fa8bit port map(tsum4,temp5,carry(0),sum5,carry(5));
INST6 : fa8bit port map(tsum5,temp6,carry(0),sum6,carry(6));
INST7 : fa8bit port map(tsum6,temp7,carry(0),sum7,carry(7));
-- Computing the product
product <= carry(7)&sum7(7 downto 0)&
sum6(0)&sum5(0)&sum4(0)&sum3(0)&
sum2(0)&sum1(0)&sum0(0);
end multiplier8x8_arch;
Test Bench
entity multiplier8x8_test is end entity;
architecture multiplier8x8_test_arch of multiplier8x8_test is
component multiplier8x8 is
port (
aIn,bIn : in bit_vector(7 downto 0);
product : out bit_vector(15 downto 0)
);
end component;
signal test_a,test_b: bit_vector(7 downto 0);
signal test_product: bit_vector(15 downto 0);
begin
inst0 : multiplier8x8 port map(test_a,test_b,test_product);
process
begin
test_a <= "00000011"; -- 3
test_b <= "00010001"; -- 17
-- product should be 51 or 0000000000110011
wait for 50 ns;
test_a <= "00010000"; -- 16 (left shift 4)
-- product should be 0000000100010000
wait for 50 ns;
end process;
end multiplier8x8_test_arch;

Question 3 (a)
Components
entity decoder2x4 is
port(
xin : in bit_vector(1 downto 0);
enable : in bit;
output : out bit_vector(3 downto 0)
);
end entity;
architecture decoder2x4_arch of decoder2x4 is
begin
-- conditional assignment
output <= "0000" when enable = '0' else
"0001" when xin = "00" and enable = '1' else
"0010" when xin = "01" and enable = '1' else
"0100" when xin = "10" and enable = '1' else
"1000" when xin = "11" and enable = '1' ;
end decoder2x4_arch;
Code
entity decoder4x16 is
port(
inputs : in bit_vector(3 downto 0);
en : in bit;
outputs : out bit_vector(15 downto 0)
);
end entity;
architecture decoder4x16_arch of decoder4x16 is
component decoder2x4 is
port(
xin : in bit_vector(1 downto 0);
enable : in bit;
output : out bit_vector(3 downto 0)
);
end component;
signal temp : bit_vector(3 downto 0);
begin
inst0 : decoder2x4 port map (inputs(3 downto 2),en,temp);
inst1 : decoder2x4 port map (inputs(1 downto 0),temp(3),outputs(15 downto 12));
inst2 : decoder2x4 port map (inputs(1 downto 0),temp(2),outputs(11 downto 8));
inst3 : decoder2x4 port map (inputs(1 downto 0),temp(1),outputs(7 downto 4));
inst4 : decoder2x4 port map (inputs(1 downto 0),temp(0),outputs(3 downto 0));
end decoder4x16_arch;

Test Bench
entity decoder4x16_test is
end entity;
architecture decoder4x16_test_arch of decoder4x16_test is
component decoder4x16 is
port(
inputs : in bit_vector(3 downto 0);
en : in bit;
outputs : out bit_vector(15 downto 0)
);
end component;
signal test_inputs:bit_vector(3 downto 0);
signal test_enable:bit;
signal test_output: bit_vector(15 downto 0);
begin
inst0 : decoder4x16 port map(test_inputs,test_enable,test_output);
process
begin
test_enable <= '1';
test_inputs <= "0000";
wait for 50 ns;
test_inputs <= "0001";
wait for 50 ns;
test_inputs <= "0010";
wait for 50 ns;
test_inputs <= "0011";
wait for 50 ns;
test_inputs <= "0100";
wait for 50 ns;
test_inputs <= "0101";
wait for 50 ns;
test_inputs <= "0110";
wait for 50 ns;
test_inputs <= "0111";
wait for 50 ns;
test_inputs <= "1000";
wait for 50 ns;
test_inputs <= "1001";
wait for 50 ns;
test_enable <= '0';
test_inputs <= "1010";
wait for 50 ns;
end process;
end decoder4x16_test_arch;

Question 3 (b)
Components
entity mux4x1_selected is
port (
inputs : in bit_vector(3 downto 0);
sel : in bit_vector(1 downto 0);
output : out bit
);
end entity;
architecture mux4x1_selected_arch of mux4x1_selected is
begin
with sel select output <=
inputs(0) when "00",
inputs(1) when "01",
inputs(2) when "10",
inputs(3) when "11";
end mux4x1_selected_arch;
Code
entity mux16x1 is
port(
xin : in bit_vector(15 downto 0);
xsel : in bit_vector(3 downto 0);
xout : out bit
);
end entity;
architecture mux16x1_arch of mux16x1 is
component mux4x1_selected is
port (
inputs : in bit_vector(3 downto 0);
sel : in bit_vector(1 downto 0);
output : out bit
);
end component;
signal temp : bit_vector(3 downto 0);
begin
inst0: mux4x1_selected port map (xin(3 downto 0),xsel(1 downto 0),temp(0));
inst1: mux4x1_selected port map (xin(7 downto 4),xsel(1 downto 0),temp(1));
inst2: mux4x1_selected port map (xin(11 downto 8),xsel(1 downto 0),temp(2));
inst3: mux4x1_selected port map (xin(15 downto 12),xsel(1 downto 0),temp(3));
inst4: mux4x1_selected port map (temp,xsel(3 downto 2),xout);
end mux16x1_arch;

Test Bench
entity mux16x1_test is
end entity;
architecture mux16x1_test_arch of mux16x1_test is
component mux16x1
port(
xin : in bit_vector(15 downto 0);
xsel : in bit_vector(3 downto 0);
xout : out bit
);
end component;
signal test_inputs : bit_vector(15 downto 0);
signal test_sel : bit_vector(3 downto 0);
signal test_output : bit;
begin
inst0 : mux16x1 port map(test_inputs,test_sel,test_output);
process
begin
test_inputs <= "1010101010101010";
test_sel <= "0000";
wait for 50 ns;
test_sel <= "0101";
wait for 50 ns;
test_sel <= "1010";
wait for 50 ns;
test_sel <= "1100";
wait for 50 ns;
test_sel <= "1101";
wait for 50 ns;
end process;
end mux16x1_test_arch;

Question 3 (c)
Components
entity comparator1bit is
port(
x,y,prev_lt,prev_eq,prev_gt : in bit;
lt,eq,gt : out bit
);
end entity;
architecture comparator1bit_arch of comparator1bit is
begin
gt <= prev_gt or (prev_eq and (not y) and x); -- if pervious is greater or prev equal and present is
greater
lt <= prev_lt or (prev_eq and (not x) and y); -- if previous is less or prev equal and present is less
eq <= prev_eq and (y xnor x); -- if equal and present equal
end comparator1bit_arch;
Code
entity comparator8bit is
port (
x_in,y_in: in bit_vector(7 downto 0);
greater,lesser,equal : out bit
);
end entity;
architecture comparator8bit_arch of comparator8bit is
component comparator1bit is
port(
x,y,prev_lt,prev_eq,prev_gt : in bit;
lt,eq,gt : out bit
);
end component;
signal temp_prev_lt,temp_prev_eq,temp_prev_gt : bit_vector(8 downto 0);
begin
temp_prev_lt(0) <= '0';
temp_prev_gt(0) <= '0';
temp_prev_eq(0) <= '1';
GEN:
for I in 0 to 7 generate
COMP: comparator1bit port map(
x_in(7-I),
y_in(7-I),
temp_prev_lt(I),temp_prev_eq(I),temp_prev_gt(I),
temp_prev_lt(I+1),temp_prev_eq(I+1),temp_prev_gt(I+1)
);
end generate GEN;
greater <= temp_prev_gt(8);
lesser <= temp_prev_lt(8);
equal <= temp_prev_eq(8);
end comparator8bit_arch;

Test Bench
entity comparator8bit_test is
end entity;
architecture comparator8bit_test_arch of comparator8bit_test is
component comparator8bit is
port (
x_in,y_in: in bit_vector(7 downto 0);
greater,lesser,equal : out bit
);
end component;
signal test_x,test_y:bit_vector(7 downto 0);
signal test_greater,test_lesser,test_equal : bit;
begin
inst0: comparator8bit port map(test_x,test_y,test_greater,
test_lesser,test_equal);
process
begin
test_x <= "01100000";
test_y <= "10000000";
wait for 50 ns;
test_x <= "11100000";
wait for 50 ns;
test_y <= "11100000";
wait for 50 ns;
end process;
end comparator8bit_test_arch;

Question 4
Code
entity basicALU is
port (
x : in bit_vector(7 downto 0);
y : in bit_vector(7 downto 0);
sel : in bit_vector(2 downto 0);
output : out bit_vector(8 downto 0)
);
end entity;
architecture basicALU_arch of basicALU is
component fa1bit is
port(
x,y,cin : in bit;
sum,cout : out bit
);
end component;
component mux8vector is
port(
inp0,inp1,inp2,inp3,inp4,inp5,inp6,inp7 : in bit_vector(8 downto 0);
mux_sel : in bit_vector(2 downto 0);
mux_out : out bit_vector(8 downto 0)
);
end component;
signal adderCarry,adderOutput,incDecCarry,incDecOutput : bit_vector(8 downto 0);
signal tempInput,one : bit_vector(7 downto 0);
signal adderControl : bit;
signal andO,orO,notO,xorO : bit_vector(8 downto 0);
begin
-- 000 Add
-- 001 Subtract
-- 010 Increment (add with 00000001)
-- 011 Decrememt (subtract 00000001)
-- 100 AND
-- 101 OR
-- 110 XOR
-- 111 NOT (of x)
one <= "00000001";
adderControl <= '0' when sel = "000" or sel = "010" else
'1' when sel = "001" or sel = "011";
adderCarry(0) <= adderControl;
incDecCarry(0) <= adderControl;

ADD:
for I in 0 to 7 generate
tempInput(I) <= (adderControl xor y(I)) when sel = "000" or sel = "001" else
(adderControl xor one(I)) when sel = "010" or sel = "011";
add_sub: fa1bit port map(x(I),tempInput(I),adderCarry(I),adderOutput(I),adderCarry(I+1));
inc_dec: fa1bit port map(x(I),tempInput(I),incDecCarry(I),incDecOutput(I),incDecCarry(I+1));
end generate ADD;
adderOutput(8) <= adderCarry(8) xor adderCarry(7);
incDecOutput(8) <= incDecCarry(8) xor incDecCarry(7);
andO <= '0'& (x and y);
orO <= '0'& (x or y);
xorO <= '0'& (x xor y);
notO <= '0'& (not x);
inst0 : mux8vector port map (adderOutput,adderOutput,
incDecOutput,incDecOutput,andO,
orO,xorO,notO,sel,output);
-- output <= adderOutput when sel = "000" or sel = "001" else
-incDecOutput when sel = "010" or sel ="011" else
-'0'& (x and y) when sel = "100" else
-- '0'& (x or y) when sel = "101" else
-- '0'& (x xor y) when sel = "110" else
-- '0'& (not x) when sel = "111";
end basicALU_arch;
Test Bench
entity basicALU_test is
end entity;
architecture basicALU_test_arch of basicALU_test is
component basicALU is
port (
x : in bit_vector(7 downto 0);
y : in bit_vector(7 downto 0);
sel : in bit_vector(2 downto 0);
output : out bit_vector(8 downto 0)
);
end component;
signal test_x,test_y: bit_vector(7 downto 0);
signal test_sel : bit_vector(2 downto 0);
signal test_output : bit_vector(8 downto 0);
begin

-- 000 Add
-- 001 Subtract
-- 010 Increment (add with 00000001)
-- 011 Decrememt (subtract 00000001)
-- 100 AND
-- 101 OR
-- 110 XOR
-- 111 NOT (of x)
inst0 : basicALU port map(test_x,test_y,test_sel,test_output);
process
begin
test_x <= "11001010";
test_y <= "00110011";
test_sel <= "000";
wait for 50 ns;
test_sel <= "001";
wait for 50 ns;
test_sel <= "010";
wait for 50 ns;
test_sel <= "011";
wait for 50 ns;
test_sel <= "100";
wait for 50 ns;
test_sel <= "101";
wait for 50 ns;
test_sel <= "110";
wait for 50 ns;
test_sel <= "111";
wait for 50 ns;
end process;
end basicALU_test_arch;

Question 5
Code
entity bitOperators is
port (
input : in bit_vector (7 downto 0);
sel : in bit_vector (1 downto 0);
output : out bit_vector(7 downto 0)
);
end entity;
architecture bitOperators_arch of bitOperators is
signal tLeft,tRight : bit_vector(7 downto 0);
begin
-- 00 Left Shift
-- 01 Right Shift
-- 10 Right Rotate
-- 11 Left Rotate
GEN_SHIFT:
for I in 0 to 6 generate
tLeft(I+1) <= input(I);
tRight(I) <= input(I+1);
end generate GEN_SHIFT;
tLeft(0) <= '0';
tRight(7) <= '0';
output <= tLeft when sel = "00" else
tRight when sel = "01" else
input(0)&tRight(6 downto 0) when sel = "10" else
tLeft(7 downto 1)&input(7) when sel = "11";
end bitOperators_arch;

Test Bench
entity bitOperators_test is
end entity;
architecture bitOperators_test_arch of bitOperators_test is
component bitOperators is
port (
input : in bit_vector (7 downto 0);
sel : in bit_vector (1 downto 0);
output : out bit_vector(7 downto 0)
);
end component;
signal test_input,test_output : bit_vector(7 downto 0);
signal test_sel : bit_vector(1 downto 0);
begin
-- 00 Left Shift
-- 01 Right Shift
-- 10 Right Rotate
-- 11 Left Rotate
inst0: bitOperators port map(test_input,test_sel,test_output);
process
begin
test_input <= "00110011";
test_sel <= "00";
wait for 50 ns;
test_sel <= "01";
wait for 50 ns;
test_sel <= "10";
wait for 50 ns;
test_sel <= "11";
wait for 50 ns;
end process;
end bitOperators_test_arch;

Question 6
Components
entity nand1 is
port (
x , y : in bit;
z : out bit
);
end entity;
architecture nand1_arch of nand1 is
begin
z <= x nand y;
end architecture;
entity nand2 is
port (
x , y : in bit;
z : out bit
);
end entity;
architecture nand2_arch of nand2 is
begin
z <= x nand y after 2 ns;
end architecture;
Code
entity SRFlipFlop is
port (
s, r, clk, reset : in bit;
q, notQ : out bit
);
end entity;
architecture SRFlipFlop_arch of SRFlipFlop is
component nand1 is
port (
x , y : in bit;
z : out bit
);
end component;
component nand2 is
port (
x , y : in bit;
z : out bit
);
end component;
signal temp1, temp2, notR, notS : bit;

begin
gate1: nand1 port map (notS, temp2, temp1);
gate2: nand2 port map (notR, temp1, temp2);
process(clk)
begin
if(reset = '1') then
q <= '0';
notQ <= '1';
elsif(clk'event and clk = '1') then -- rising edge
notR <= not r;
notS <= not s;
q <= temp1;
notQ <= temp2;
end if;
end process;
end architecture;
Test Bench
entity SRFlipFlop_test is
end entity;
architecture SRFlipFlop_test_arch of SRFlipFlop_test is
component SRFlipFlop is
port (
s, r, clk, reset : in bit;
q, notQ : out bit
);
end component;
signal testS, testR, testCLK, testReset, testQ, testQnot : bit;
begin
flipFlop: SRFlipFlop port map (testS, testR, testCLK, testReset, testQ, testQnot);
-- Clock Generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;

-- Inputs
process
begin
testS <= '0';
testR <= '0';
wait for 50 ns;
testS <= '0';
testR <= '1';
wait for 50 ns;
testS <= '1';
testR <= '0';
wait for 50 ns;
testReset <= '1';
wait for 50 ns;
testReset <= '0';
wait for 50 ns;
testS <= '1';
testR <= '1';
wait for 150 ns;
end process;
end architecture;

Question 7
Components
entity DFlipFlop is
port (
d, clk, reset, preset : in bit;
q : out bit
);
end entity;
architecture DFlipFlop_arch of DFlipFlop is
begin
process(clk)
begin
if(preset = '1') then
q <= '1';
elsif(reset = '1') then
q <= '0';
elsif(clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
Code Parallel In Parallel Out
entity PIPO8bit is
port (
clk, clear : in bit;
data_in : in bit_vector (7 downto 0);
data_out : out bit_vector (7 downto 0)
);
end entity;
architecture PIPO8bit_arch of PIPO8bit is
component DFlipFlop is
port (
d, clk, reset, preset : in bit;
q : out bit
);
end component;
signal preset : bit;
begin
GEN : for i in 0 to 7 generate
DFF : DFlipFlop port map (data_in(i), clk, clear, preset, data_out(i));
end generate GEN;
end architecture;

Test Bench Parallel In Parallel Out

entity PIPO8bit_test is
end entity;
architecture PIPO8bit_test_arch of PIPO8bit_test is
component PIPO8bit is
port (
clk, clear : in bit;
data_in : in bit_vector (7 downto 0);
data_out : out bit_vector (7 downto 0)
);
end component;
signal testCLK, testCLR : bit;
signal testIn, testOut : bit_vector(7 downto 0);
begin
REG : PIPO8bit port map (testCLK, testCLR, testIn, testOut);
-- Clock Generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
-- Inputs
process
begin
testIn <= "11000011";
wait for 50 ns;
testIn <= "11110000";
wait for 50 ns;
testCLR <= '1';
wait for 50 ns;
testCLR <= '0';
testIn <= "01010101";
wait for 50 ns;
end process;
end architecture;
Code Ring Counter
entity RingCounter is
port (
clk, clear, set : in bit;
data : inout bit_vector (3 downto 0)
);
end entity;

architecture RingCounter_arch of RingCounter is

component DFlipFlop is
port (
d, clk, reset, preset : in bit;
q : out bit
);
end component;
signal temp : bit_vector(0 to 4);
begin
temp(0) <= not data(3);
GEN : for i in 0 to 3 generate
temp(i + 1) <= data(i);
DFF : DFlipFlop port map (temp(i), clk, clear, set, data(i));
end generate GEN;
end architecture;
Test Bench Ring Counter
entity RingCounter_test is
end entity;
architecture RingCounter_test_arch of RingCounter_test is
component RingCounter is
port (
clk, clear, set : in bit;
data : inout bit_vector (3 downto 0)
);
end component;
signal testCLK, testCLR, testSET : bit;
signal testData : bit_vector (3 downto 0);

begin
RC: RingCounter port map(testCLK, testCLR, testSET, testData);
-- Clock Generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;

-- Inputs
process
begin
testSET <= '1';
wait for 50 ns;
testSET <= '0';
wait for 200 ns;
testCLR <= '1';
wait for 50 ns;
testCLR <= '0';
wait for 200 ns;
end process;
end architecture;

Question 8
Code
entity SerialAdder is
port (
a, b, clk, reset : in bit;
s, cout : out bit
);
end entity;
architecture SerialAdder_arch of SerialAdder is
component DFlipFlop is
port (
d, clk, reset, preset : in bit;
q : out bit
);
end component;
component fa1bit is
port(
x,y,cin : in bit;
sum,cout : out bit
);
end component;
signal presentCarry, nextCarry , preset: bit;
begin
FA : fa1bit port map (a, b, nextCarry, s, presentCarry );
DFF : DFlipFlop port map (presentCarry, clk, reset, preset, nextCarry );
cout <= nextCarry;
end architecture;

Test Bench
entity SerialAdder_test is
end entity;
architecture SerialAdder_test_arch of SerialAdder_test is
component SerialAdder is
port (
a, b, clk, reset : in bit;
s, cout : out bit
);
end component;
signal testA, testB, testCLK, testRESET, testS, testCout : bit;
begin
SA : SerialAdder port map (testA, testB, testCLK, testRESET, testS, testCout);
-- Clock generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
-- Inputs
process
begin
testRESET <= '1';
wait for 50 ns;
testRESET <= '0';
wait for 50 ns;
testA <= '1';
testB <= '0';
wait for 100 ns;
testA <= '0';
testB <= '1';
wait for 100 ns;
testA <= '1';
testB <= '1';
wait for 1 00 ns;
end process;
end architecture;

Question 9
Components
entity TFlipFlop is
port (
t, clk, reset : in bit;
q : inout bit
);
end entity;
architecture TFlipFlop_arch of TFlipFlop is
begin
process(clk)
begin
if(clk'event and clk = '1') then
if(reset = '1') then
q <= '0';
elsif(t = '1') then
q <= not q;
end if;
end if;
end process;
end architecture;
Code
entity Mod10 is
port (
up, clk : in bit;
output : inout bit_vector (3 downto 0)
);
end entity;
architecture Mod10_test of Mod10 is
component TFlipFlop is
port (
t, clk, reset : in bit;
q : inout bit
);
end component;
signal high, low, clr: bit;
signal tempCLK : bit_vector(0 to 4);
begin
high <= '1';
clr <= output(3) and output(1) when up = '1'; -- 1X1X
tempCLK(0) <= not clk when up = '1' else clk;
GEN: for i in 0 to 3 generate
tempCLK(i + 1) <= (not output(i)) when up = '1' else output(i);
FF : TFlipFlop port map (high, tempCLK(i), clr, output(i));
end generate GEN;
end architecture;

Test Bench
entity Mod10_test is
end entity;
architecture Mod10_test_test of Mod10_test is
component Mod10 is
port (
up, clk : in bit;
output : inout bit_vector (3 downto 0)
);
end component;
signal testUp, testCLK : bit;
signal testOutput : bit_vector (3 downto 0);
begin
COUNTER : Mod10 port map(testUp, testCLK, testOutput);
testUp <= '1';
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
end architecture;

Question 10
Code
entity nBitLeftShiftRegister is
generic (
bits : integer := 8
);
port (
enable, write, clk, reset : in bit;
data : in bit_vector (bits - 1 downto 0);
output : out bit_vector (bits - 1 downto 0)
);
end entity;
architecture nBitLeftShiftRegister_arch of nBitLeftShiftRegister is
signal tempOut : bit_vector(bits - 1 downto 0);
begin
process(clk)
begin
if (reset = '1') then
tempOut <= (others => '0');
elsif (clk'event and clk = '1') then
if( enable = '1') then
for i in bits - 1 downto 1 loop
tempOut(i) <= tempOut(i - 1);
end loop;
tempOut(0) <= '0';
elsif( enable = '0' and write = '1') then
tempOut <= data;
end if;
end if;
output <= tempOut;
end process;
end architecture;
Test Bench
entity nBitLeftShiftRegister_test is
end entity;
architecture nBitLeftShiftRegister_test_arch of nBitLeftShiftRegister_test is
component nBitLeftShiftRegister is
generic (
bits : integer := 16
);
port (
enable, write, clk, reset : in bit;
data : in bit_vector (bits - 1 downto 0);
output : out bit_vector (bits - 1 downto 0)
);
end component;

signal testEnable, testWrite, testCLK, testReset : bit;

signal testData, testOutput : bit_vector(15 downto 0);
begin
REG : nBitLeftShiftRegister port map (testEnable, testWrite, testCLK, testReset, testData,
testOutput);
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
process
begin
testWrite <= '1';
testEnable <= '0';
testData <= "1010001111110000";
wait for 50 ns;
testWrite <= '0';
testEnable <= '1';
wait for 200 ns;
testEnable <= '0';
testReset <= '1';
wait for 50 ns;
testReset <= '0';
wait for 50 ns;
testWrite <= '1';
testEnable <= '0';
testData <= "1111000011110000";
wait for 50 ns;
testWrite <= '0';
testEnable <= '1';
wait for 200 ns;
end process;
end architecture;

Question 11
Code Booths Multiplication
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BoothMult is
port (
mpcd, mplr : in std_logic_vector (7 downto 0);
result : out std_logic_vector (15 downto 0);
start : in std_logic
);
end entity;
architecture BoothMult_arch of BoothMult is
begin
process(start)
variable br, nbr : std_logic_vector(7 downto 0);
variable acqr : std_logic_vector(15 downto 0);
variable qn1 : std_logic;
begin
if(start'event and start = '1') then
acqr (15 downto 8) := (others => '0');
acqr (7 downto 0) := mpcd;
br := mplr;
nbr := (not br) + '1'; -- 2's complement of br
qn1 := '0';
else
for i in 7 downto 0 loop
-- Special cases (01 and 10)
if(acqr(0) = '0' and qn1 = '1') then
acqr(15 downto 8) := acqr(15 downto 8) + br;
elsif(acqr(0) = '1' and qn1 = '0') then
acqr(15 downto 8) := acqr(15 downto 8) + nbr;
end if;
-- Shifting
qn1 := acqr(0);
acqr(14 downto 0) := acqr(15 downto 1);
end loop;
result <= acqr;
end if;
end process;
end architecture;

Test Bench Booths Multiplication

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BoothMult_test is
end entity;
architecture BoothMult_test_arch of BoothMult_test is
component BoothMult is
port (
mpcd, mplr : in std_logic_vector (7 downto 0);
result : out std_logic_vector (15 downto 0);
start : in std_logic
);
end component;
signal testA, testB : std_logic_vector (7 downto 0);
signal testResult : std_logic_vector (15 downto 0);
signal testStart : std_logic;
begin
MULT : BoothMult port map(testA, testB, testResult, testStart);
process
begin
----- 64,32,16,8,4,2,1
testA <= "01001100"; -- 76
testB <= "01101001"; -- 105
-- Output should be : 7980 , ie 0001111100101100
testStart <= '0';
wait for 50 ns;
testStart <= '1';
wait for 100 ns;
end process;
end architecture;
Code Restoring Division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RestoringDivision is
port (
x, y : in std_logic_vector (7 downto 0);
result : out std_logic_vector (7 downto 0);
start : in std_logic
);
end entity;

architecture RestoringDivision_arch of RestoringDivision is

begin
process(start)
variable A, B : std_logic_vector (7 downto 0);
variable Q : std_logic_vector (7 downto 0);
begin
if(start'event and start = '1') then -- Initialization
A := x;
B := y;
Q := (others => '0');
else
for i in 0 to 7 loop
Q(7 downto 1) := Q(6 downto 0);
Q(0) := A(7);
A(7 downto 1) := A(6 downto 0);
Q := (Q + ((not B) + '1'));
if(Q(7) = '1') then -- If Q - B < 0
A(0) := '0';
Q := Q + B;
else
A(0) := '1';
end if;
end loop;
result <= A;
end if;
end process;
end architecture;
Test Bench Restoring Division
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RestoringDivision_test is
end entity;
architecture RestoringDivision_test_arch of RestoringDivision_test is
component RestoringDivision is
port (
x, y : in std_logic_vector (7 downto 0);
result : out std_logic_vector (7 downto 0);
start : in std_logic
);
end component;
signal testX, testY, testResult : std_logic_vector (7 downto 0);
signal testStart : std_logic;
begin
RD : RestoringDivision port map (testX, testY, testResult, testStart);

process
begin
------ 64,32,16,8,4,2,1
testX <= "01101100"; -- 108
testY <= "00001100"; -- 12
-- Output should be : 9 , ie 00000000000001001
testStart <= '0';
wait for 50 ns;
testStart <= '1';
wait for 100 ns;
end process;
end architecture;

Question 12
Code
entity RegisterFile is
port (
clk, rw, reset : in bit;
data : in bit_vector(7 downto 0);
addrA, addrB : in integer range 0 to 15;
portA, portB : out bit_vector (7 downto 0)
);
end entity;

-- rw = '1' - Write data in addrA

-- rw = '0' - Read addrA and addrB in portA and portB
-- 16 Registers in total
-- Each 8 bit wide

architecture RegisterFile_test of RegisterFile is

type reg_array is array(0 to 15) of bit_vector(7 downto 0);
signal memory : reg_array;
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
memory <= (others => "00000000");
elsif (rw = '1') then -- Write
memory(addrA) <= data;
end if;
portA <= memory(addrA);
portB <= memory(addrB);
end if;
end process;
end architecture;
Test Bench
entity RegisterFile_test is
end entity;
architecture RegisterFile_test_test of RegisterFile_test is
component RegisterFile is
port (
clk, rw, reset : in bit;
data : in bit_vector(7 downto 0);
addrA, addrB : in integer range 0 to 15;
portA, portB : out bit_vector (7 downto 0)
);
end component;
signal testCLK, testRW, testRESET : bit;
signal testData, testPortA, testPortB : bit_vector(7 downto 0);
signal testAddrA, testAddrB : integer range 0 to 15;
begin
RF : RegisterFile port map(testCLK, testRW, testRESET,
testData, testAddrA, testAddrB, testPortA, testPortB);

-- Clock generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
-- Inputs
process
begin
testRW <= '1';
testData <= "01010101";
testAddrA <= 2;
testAddrB <= 3;
wait for 50 ns;
testData <= "11110000";
testAddrA <= 5;
testAddrB <= 2;
wait for 50 ns;
testData <= "00111100";
testAddrA <= 8;
testAddrB <= 5;
wait for 50 ns;
testRW <= '0';
testAddrA <= 2;
testAddrB <= 8;
wait for 50 ns;
testRESET <= '1';
wait for 50 ns;
testRESET <= '0';
wait for 50 ns;
end process;
end architecture;

Question 13
Code
entity GrayCodeCounter is
port (
clk , reset : in bit;
output : out bit_vector(2 downto 0)
);
end entity;
architecture GrayCodeCounter_arch of GrayCodeCounter is
type state is (S0,S1,S2,S3,S4,S5,S6,S7);
-- user defined enumerative data type
signal presentState,nextState : state;
-- using state data type defined above
begin
process(clk, reset)
begin
if(reset = '1') then
presentState <= S7;
elsif(clk'event and clk = '1') then
presentState <= nextState;
end if;
end process;
process(presentState)
begin
case presentState is
when S0 =>
nextState <= S1;
output <= "001";
when S1 =>
nextState <= S2;
output <= "011";
when S2 =>
nextState <= S3;
output <= "010";
when S3 =>
nextState <= S4;
output <= "110";
when S4 =>
nextState <= S5;
output <= "111";
when S5 =>
nextState <= S6;
output <= "110";
when S6 =>
nextState <= S7;
output <= "100";
when S7 =>
nextState <= S0;
output <= "000";
end case;
end process;
end architecture;

Test Bench
entity GrayCodeCounter_test is
end entity;
architecture GrayCodeCounter_test_arch of GrayCodeCounter_test is
component GrayCodeCounter is
port (
clk , reset : in bit;
output : out bit_vector(2 downto 0)
);
end component;
signal testCLK, testRESET : bit;
signal testOutput : bit_vector(2 downto 0);
begin
GCC : GrayCodeCounter port map(testCLK, testRESET, testOutput);
-- Clock generation
process
begin
for i in 0 to 20 loop
testCLK <= '0';
wait for 20 ns;
testCLK <= '1';
wait for 20 ns;
end loop;
end process;
-- Inputs
process
begin
wait for 250 ns;
testRESET <= '1';
wait for 50 ns;
testRESET <= '0';
wait for 150 ns;
end process;
end architecture;

Question 14
Code
entity fsm_0101 is
port(
x,reset,clk : in bit;
z : out bit
);
end entity;
architecture fsm_0101_arch of fsm_0101 is
type state is (S0,S1,S2,S3); -- user defined enumerative data type
signal ps,ns : state; -- using state data type defined above
begin
process(clk,reset)
begin
if(reset = '1') then
ps <= S0;
elsif(clk'event and clk = '1') then
ps <= ns;
end if;
end process;
process(x,ps)
begin
case ps is
when S0 =>
if(x = '0') then
ns <= S1;
z <= '0';
else
ns <= S0;
z <= '0';
end if;
when S1 =>
if(x = '1') then
ns <= S2;
z <= '0';
else
ns <= S1;
z <= '0';
end if;
when S2 =>
if(x = '0') then
ns <= S3;
z <= '0';
else
ns <= S0;
z <= '0';
end if;

when S3 =>
if(x = '1') then
ns <= S2;
z <= '1';
else
ns <= S1;
z <= '0';
end if;
end case;
end process;
end architecture;
Test Bench
entity fsm_0101_test is
end entity;
architecture fsm_0101_test_arch of fsm_0101_test is
component fsm_0101 is
port(
x,reset,clk : in bit;
z : out bit
);
end component;
signal test_x ,test_z,test_reset,test_clk: bit;
begin
inst: fsm_0101 port map(test_x,test_reset,test_clk,test_z);
process
begin
for i in 0 to 20 loop
test_clk <= '1'; wait for 25 ns;
test_clk <= '0'; wait for 25 ns;
end loop;
end process;
process
begin
test_reset <= '1'; wait for 50 ns;
test_x <= '0'; test_reset <= '0'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '0'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '0'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '0'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
test_x <= '1'; wait for 50 ns;
end process;
end architecture;

Question 15
Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom_16byte is
generic (
bits : integer := 8;
words : integer := 16
);
port (
addr : in integer range 0 to words - 1;
dataout : out std_logic_vector(bits-1 downto 0)
);
end entity;
architecture rom_16byte_arch of rom_16byte is
type rom_array is array(0 to words - 1) of std_logic_vector(bits - 1 downto 0);
constant memory : rom_array := ("10101010","00001111","00110011",
"11001111","11111111","00000000","11100111","00111100",
"11100010","01011111","11001100","10101010","00001111",
"00110011","11001111","11101010");
begin
dataout <= memory(addr);
end architecture;
Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom_16byte_test is
end entity;
architecture rom_16byte_test_arch of rom_16byte_test is
component rom_16byte is
generic (
bits : integer := 8;
words : integer := 16
);
port (
addr : in integer range 0 to words - 1;
dataout : out std_logic_vector(bits-1 downto 0)
);
end component;
signal test_out : std_logic_vector(7 downto 0);
signal test_addr : integer range 0 to 15;
begin

inst : rom_16byte port map(test_addr,test_out);

process
begin
test_addr <= 4;
wait for 20 ns;
test_addr <= 6;
wait for 20 ns;
test_addr <= 1;
wait for 20 ns;
end process;
end architecture;

Question 16
Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_8K is
generic (
bits : integer := 8;
words : integer := 1024
);
port (
addr : in integer range 0 to words - 1;
data : inout std_logic_vector( bits -1 downto 0);
clk, write_enable : in std_logic
);
end entity;
architecture ram_8K_arch of ram_8K is
type ram_array is array (0 to words - 1) of std_logic_vector(bits - 1 downto 0);
signal memory : ram_array;
begin
memory <= (others => "00000000");
process(clk, write_enable)
begin
if(write_enable = '0') then
data <= memory(addr);
else
data <= (others => 'Z');
if(clk'event and clk = '1') then
memory(addr) <= data;
end if;
end if;
end process;
end architecture;

Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_8K_test is
end entity;
architecture ram_8K_test_arch of ram_8K_test is
component ram_8K is
generic (
bits : integer := 8;
words : integer := 1024
);
port (
addr : in integer range 0 to words - 1;
data : inout std_logic_vector(bits -1 downto 0);
clk, write_enable : in std_logic
);
end component;
signal test_clk, test_we : std_logic;
signal test_data : std_logic_vector(7 downto 0);
signal test_addr : integer range 0 to 1023;
begin
test_we <= '0';
test_clk <= '0';
test_data <= (others => '0');
inst : ram_8K port map (test_addr, test_data, test_clk, test_we);
-- Clock
process
begin
for i in 0 to 20 loop
test_clk <= '1';
wait for 20 ns;
test_clk <= '0';
wait for 20 ns;
end loop;
end process;

-- Inputs
process
begin
test_we <= '1';
test_addr <= 0;
wait for 50 ns;
test_we <= '1';
test_addr <= 0;
test_data <= "10101010";
wait for 50 ns;
test_we <= '1';
test_addr <= 6;
test_data <= "11111010";
wait for 50 ns;
test_we <= '0';
test_addr <= 2;
wait for 50 ns;
test_addr <= 6;
wait for 50 ns;
end process;
end architecture;