www.alljntuworld.

in

JNTU World

LECTURE NOTES
ON

ld

IC APPLICATIONS

JN

TU

or

III B. Tech I semester (JNTUH-R13)

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Syllabus:
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
HYDERABAD
L
4

-/-/-

ld

III Year B.Tech. EEE -I Sem

T/ /P/D C

IC APPLICATIONS

PART1: LINEARINTEGRATED CIRCUITS

or

UNIT I: INTEGRATED CIRCUITS

Classification, Chip Size and Circuit Complexity, Classification of Integrated Circuits , Comparison
of various Logic Families, Standard TTL NAND Gate- Analysis & Characteristics. TTL Open Collector
Outputs, Tristate TTL, MOS & CMOS open drain and tri-state outputs, CMOS Transmission gate, IC
interfacing TTL driving CMOS & CMOS driving TTL.

UNIT II: OP-AMP and APPLICATIONS

Basic Applications of Op-Amp, Ideal and Practical Optical Op-Amp,internal circuits, Op-amp characteristics,
DC and AC Characteristics, 741 Op-Amp and its Features, Modes of operation-inverting, non-inverting,
differential.

TU

Basic applications of OP-AMP, Instrumentation Amplifier, AC Amplifier, V to I and I to V Converters.

Sample & Hold Circuits, Multipliers and dividers, Differentiators and Integrators, Comparators. Introduction
to Voltage Regulators.
UNIT III: ACTIVE FILTERS &OSCILLATORS
Introduction, First order LPF,HPF filters, Band Pass Filters,Band Reject and All Pass Filters.
Oscillators Types, Principle of Operation RC, Wien Bridge and Quadrature type, Waveform Generators
Triangular, Saw Tooth, Square Wave and VCO.

JN

UNIT IV: TIMERS & PHASE LOCKED LOOPS

Introduction to 555 Timer, Functional Diagram, Monostable and astable operations and Applications.
Schmitt Trigger, PLL-Introduction. Block Schematic, Principles and Description of Individual Blocks of 565.
VCO.
UNIT V: D-A and A-D CONVERTERS
Introcuction, Basic DAC Techniques Weighted Resistor Type, R-2R Ladder Type, Inverted R-2R Type. IC
1408 DAC.Different types of ADCS parallel Comparator Type, Counter Type. Successive Approximation
Register Type and Dual Slope Type ADC, DAC and ADC Specifications.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

TEXT BOOKS:
1. Linear Integrated Circuits D. Roy Chowdhury. New Age International (P) Ltd, 3rd Ed., 2008.
2. Op-Amps & Linear Ics Ramakanth A. Gayakwad, PHI.

REFERENCES:

JN

TU

or

ld

1. operational amplifiers and linear integrated circuits by RF Coughlin & Fredrick F, Driscoll, PHI
2. Operational Amplifiers and Liner Integrated Circuits: Theory & Applications, Denton J.Daibey,TMH.
3. Design with OP-Amp & Analog ICs,Serglo Franco,McGraw Hill.
4. Digital Fundamentals Floyd and Jain. Pearson Education. 8th Edition 2005.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

UNIT-I
INTEGRATED CIRCUITS
1.1 CLASSIFICATION OF ICS:
Integrated Circuitis a miniature, low cost electronic circuit consisting of active and
passive components that are irreparably joined together on a single crystal chip of silicon.

ld

CLASSIFICATION:
1.1.1 Based on mode of operation
a. Digital ICs
b. Linear ICs

or

Digital ICs: Digital ICs are complete functioning logic networks that are
equivalents of basic transistor logic circuits.
Ex:- gates ,counters, multiplexers, demultiplexers, shift registers.

Linear ICs: Linear ICs are equivalents of discrete transistor networks, such as amplifiers,
filters, frequency multipliers, and modulators that often require additional external
components for satisfactory operation
1.1.2. Based on fabrication
a. Monolithic ICs
b. Hybrid ICs

TU

a. Monolithic ICs : In monolithic ICs all components (active and passive) are formed
simultaneously by a diffusion process. Then a metallization process is used in
interconnecting these components to form the desired circuit.
b. Hybrid ICs: .In hybrid ICs, passive components (such as resistors and capacitors) and the
interconnections between them are formed on an insulating substrate. The substrate is used
as a chassis for the integrated components. Active components such as transistors and diodes
as wellas monolithic integrated circuits, are then connected to form a complete circuit.

JN

1.1.3. Based on number of components integrated on ICs

a. SSI <10 components
b. MSI <100 components
c. LSI >100 components
d. VLSI >1000 components

1.2. CHIP SIZE AND CIRCUIT COMPLEXITY:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Invention of transistor
Development of silicon transistor
Silicon planar technology
First IC,Small Scale Integration(SSI),3 to 30 gates/chip
Medium Scale Integration (MSI),30 to 300 gates/chip
Large Scale Integration(LSI),300 to 3000 gates/chip
Very Large Scale Integration(VLSI) more than 3000 gates/chip

1948
1955-1959
1959
1960
1965-1970
1970-1975
1975

or

ld

An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, or microchip) is an
electronic circuit. Integrated circuits are used in virtually all electronic equipment today and have
revolutionized the world of electronics. Computers, cell phones, and other digital appliances are now
inextricable parts of the structure of modern societies, made possible by the low cost of production of
integrated circuits. There are two main advantages of ICs over discrete circuits: cost and performance. Cost
is low because the chips, with all their components, are printed as a unit by photolithography rather than
being constructed one transistor at a time. Furthermore, much less material is used to construct a packaged
IC die than to construct a discrete circuit.
Performance is high because the components switch quickly and consume little power (compared to their
discrete counterparts) as a result of the small size and close proximity of the components.
6.2 CLASSIFICATION OF INTEGRATED CIRCUITS

Small Scale Integration or (SSI) - Contain up to 10 transistors or a few gates within a single package
such as AND, OR, NOT gates.
Medium Scale Integration or (MSI) - between 10 and 100 transistors or tens of gates within a single
package and perform digital operations such as adders, decoders, counters, flip-flops and
multiplexers.
Large Scale Integration or (LSI) - between 100 and 1,000 transistors or hundreds of gates and
perform specific digital operations such as I/O chips, memory, arithmetic and logic units.
Very-Large Scale Integration or (VLSI) - between 1,000 and 10,000 transistors or thousands of gates
and perform computational operations such as processors, large memory arrays and programmable
logic devices.
Super-Large Scale Integration or (SLSI) - between 10,000 and 100,000 transistors within a single
package and perform computational operations such as microprocessor chips, micro-controllers,
basic PICs and calculators.
Ultra-Large Scale Integration or (ULSI) - more than 1 million transistors - the big boys that are used
in computers CPUs, GPUs, video processors, micro-controllers, FPGAs and complex PICs.

TU

Classification of ICs based on complexity:

JN

While the "ultra large scale" ULSI classification is less well used, another level of integration which
represents the complexity of the Integrated Circuit is known as the System-on-Chip or (SOC) for short.
Here the individual components such as the microprocessor, memory, peripherals, I/O logic etc, are all
produced on a single piece of silicon and which represents a whole electronic system within one single chip,
literally putting the word "integrated" into integrated circuit. These chips are generally used in mobile
phones, digital cameras, micro-controllers, PICs and robotic applications, and which can contain up to 100
million individual silicon-CMOS transistor gates within one single package.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Classification of integrated circuits based on the signal processed:

DIGITAL INTEGRATED CIRCUITS

ANALOG INTEGRATED CIRCUITS

ld

Digital integrated circuits, primarily used to build computer systems, also occur in cellular phones,
stereos and televisions. Digital integrated circuits include microprocessors, microcontrollers and logic
circuits. They perform mathematical calculations, direct the flow of data and make decisions based on
Boolean logic principles.The Boolean system used centers on on two numbers: 0 and 1.

or

Analog integrated circuits most commonly make up a part of power supplies, instruments and
communications. In these applications, analog integrated circuits amplify, filter and modify electrical signals.
In cellular phones, they amplify and filter the incoming signal from the phone's antenna. The sound encoded
into that signal has a low amplitude level; after the circuit filters the sound signal from the incoming signal,
the circuit amplifies the sound signal and sends it to the speaker in your cell phone, allowing you to hear the
voice on the other end.
MIXED-SIGNAL INTEGRATED CIRCUITS

Mixed-signal circuits occur in cellular phones, instrumentation, motor and industrial control
applications. These circuits convert digital signals to analog signals, which in turn set the speed of motors,
the brightness of lights and the temperature of heaters, for example. They also convert digital signals to
sound waveforms, allowing for the design of digital musical instruments such as electronic organs and
computer keyboards capable of playing music.

TU

Mixed-signal integrated circuits also convert analog signals to digital signals. They will convert
analog voltage levels to digital number representations of the voltage level of the signals. Digital integrated
circuits then perform mathematical calculations on these numbers.

MEMORY-INTEGRATED CIRCUITS

Though primarily used in computer systems, memory-integrated circuits also occur in cellular
phones, stereos and televisions. A computer system may include 20 to 40 memory chips, while other types
of electronic systems may contain just a few.

JN

Memory circuits store information, or data, as two numbers: 0 and 1. Digital integrated circuits will
often retrieve these numbers from memory and perform calculations with them, then save the calculation
result a memory chip's data storage locations. The more data it accesses---pictures, sound and text---the more
memory an electronic system will require.

6.3 INTRODUCTION TO DIGITAL LOGIC GATES

A Digital Logic Gate is an electronic device that makes logical decisions based on the different
combinations of digital signals present on its inputs. A digital logic gate may have more than one input but

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

only has one digital output. Standard commercially available digital logic gates are available in two basic
families or forms:

Transistor-Transistor Logic(TTL) such as the 7400 series, and

Complementary Metal-Oxide-Silicon (CMOS) which is the 4000 series of chips.

ld

This notation of TTL or CMOS refers to the logic technology used to manufacture the integrated
circuit, (IC).TTL IC's use NPN (or PNP) type Bipolar Junction Transistors while CMOS IC's use Field Effect
Transistors or FET's for both their input and output circuitry.

Digital Logic States

In digital logic design only two voltage levels or states are allowed and these states are
generally referred to as Logic "1" and Logic "0", High and Low.

or

Most digital logic gates and logic systems use "Positive logic", in which a logic level "0" or
"LOW" is represented by a zero voltage, 0v or ground and a logic level "1" or "HIGH" is
represented by a higher voltage such as +5 volts, There also exists a complementary "Negative
Logic" system in which the values and the rules of a logic "0" and a logic "1" are reversed but in this
tutorial section about digital logic gates we shall only refer to the positive logic convention as it is
the most commonly used.

JN

TU

6.3 STANDARD TTL-NAND GATE ANALYSIS AND CHARACTERISTICS

Fig 6.1: Two input TTL NAND gate

A two input TTL NAND gate is shown in fig 6.1. In standard TTL (transistor-transistor
logic) IC's there is a pre-defined voltage range for the input and output voltage levels which define
exactly what is a logic "1" level and what is a logic "0" level and these are shown below.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. It is called transistortransistor logic because both the logic gating
function (e.g., AND) and the amplifying function are performed by transistors (contrast with RTL
and DTL).
TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally
equivalent to multiple transistors where the bases and collectors are tied together. The output is
buffered by a common emitter amplifier.

or

ld

Input logical ones. When all the inputs are held at high voltage, the baseemitter junctions of the
multiple-emitter transistor are backward-biased. In contrast with DTL, small (about 10 A)
"collector" currents are drawn by the inputs since the transistor is in a reverse-active mode (with
swapped collector and emitter). The base resistor in combination with the supply voltage acts as a
substantially constant current source.It passes current through the basecollector junction of the
multiple-emitter transistor and the baseemitter junction of the output transistor thus turning it on;
the output voltage becomes low (logical zero).

Input logical zero. If one input voltage becomes zero, the corresponding baseemitter junction of
the multiple-emitter transistor connects in parallel to the two connected in series junctions (the base
collector junction of the multiple-emitter transistor and the baseemitter junction of the second
transistor). The input baseemitter junction steers all the base current of the output transistor to the
input source (the ground). The base of the output transistor is deprived of current causing it to go
into cut-off and the output voltage becomes high (logical one). During the transition the input
transistor is briefly in its active region; so it draws a large current away from the base of the output
transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that
speeds up the transition over a diode input structure.
Disadvantage of TTL:

TU

The main disadvantage of TTL with a simple output stage is the relatively high output
resistance at output logical "1" that is completely determined by the output collector resistor. It
limits the number of inputs that can be connected (the fanout). Some advantage of the simple output
stage is the high voltage level (up to VCC) of the output logical "1" when the output is not loaded.

6.4 TTL OPEN COLLECTOR OUTPUTS

JN

An open collector is a common type of output found on many integrated circuits (IC). Instead of
outputting a signal of a specific voltage or current, the output signal is applied to the base of an internal NPN
transistor whose collector is externalized (open) on a pin of the IC. The emitter of the transistor is connected
internally to the ground pin. If the output device is a MOSFET the output is called open drain and it
functions in a similar way.
An open collector inverter circuit is shown in the fig 6.2. In the single-input (inverter) circuit, shown
in fig 6.3 grounding the input resulted in an output that assumed the "high" (1) state. In the case of the opencollector output configuration, this "high" state was simply "floating." Allowing the input to float (or be
connected to Vcc) resulted in the output becoming grounded, which is the "low" or 0 state. Thus, a 1 in
resulted in a 0 out, and vice versa.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

Since this circuit bears so much resemblance to the simple inverter circuit, the only difference being
a second input terminal connected in the same way to the base of transistor Q2, we can say that each of the
inputs will have the same effect on the output. Namely, if either of the inputs is grounded, transistor Q2 will
be forced into a condition of cutoff, thus turning Q3 off and floating the output (output goes "high"). The
following series of illustrations shows this for three input states (00, 01, and 10):

Fig:6.2 open collector inverter circuit

JN

TU

When Q3 is OFF, the output is pulled up to Vcc through the external resistor. When Q3 is ON, the output is
connected to near-ground through the saturated transistor

Fig: 6.3 with external pull-up resistor

6.5TRISTATE TTL GATES:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

In digital electronics three-state, tri-state, or 3-statelogic allows an output port to assume a

high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the
circuit. This allows multiple circuits to share the same output line or lines (such as a bus).

TU

or

ld

Three-state outputs are implemented in many registers, bus drivers, and flip-flops in the 7400
and 4000 series as well as in other types, but also internally in many integrated circuits. Other
typical uses are internal and external buses in microprocessors, memories, and peripherals. Many
devices are controlled by an active-low input called OE (Output Enable) which dictates whether the
outputs should be held in a high-impedance state or drive their respective loads (to either 0- or 1level).

Fig. 6.4: Tristate TTL Gate

JN

Fig 6.4 shows the basic circuit for a TTL tristate inverter. When the enable input is LOW, Q2
is OFF, and the output circuit operates as a normal totem-pole configuration, in which the ouput state
depends on the input state. When the enable input is HIGH, Q2 is ON. There is thus a LOW on the second
emitter of Q1, causing Q3 and Q5 to turn OFF, and diode D1 is forward biased, causing Q4 also to turn OFF.
When both totem-pole transistors are OFF, they are effectively open, and the output is completely
disconnected from the internal circuitry

6.6 BASIC CMOS DIGITAL LOGIC GATE

One of the main disadvantages of the TTL logic series is that the gates are based on bipolar
transistor logic technology and as transistors are current operated devices, they consume large
amounts of power from a fixed +5 volt power supply. Also, TTL bipolar transistor gates have a
limited operating speed when switching from an "OFF" state to an "ON" state and vice-versa called
the "gate" or "propagation delay". To overcome these limitations complementary MOS called
"CMOS" logic gates using "Field Effect Transistors" or FET's were developed.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

As these gates use both P-channel and N-channel MOSFET's as their input device, at quiescent
conditions with no switching, the power consumption of CMOS gates is almost zero, (1 to 2uA)
making them ideal for use in low-power battery circuits and with switching speeds upwards of
100MHz for use in high frequency timing and computer circuits.

Fig6.5: 2-input NAND gate

TU

This CMOS gate (fig 6.5) example contains 3 N-channel MOSFET's, one for each input
FET1 and FET2 and one for the output FET3. When both the inputs A and B are at logic level "0",
FET1 and FET2 are both switched "OFF" giving output logic "1" from the source of FET3. When one
or both of the inputs are at logic level "1" current flows through the corresponding FET giving an
output state at Q equivalent to logic "0", thus producing a NAND gate function.

JN

For example, CMOS NAND gate:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Fig 6.6: CMOS NAND gate

In fig 6.6 the transistors Q1 and Q3are series-connected complementary pair from the inverter circuit.
Both are controlled by the same input signal (input A), the upper transistor turning off and the lower
transistor turning on when the input is "high" (1), and vice versa. The transistors Q2 and Q4 are similarly
controlled by the same input signal (input B), and how they will also exhibit the same on/off behaviour for

TU

or

ld

the same input logic levels. The upper transistors of both pairs (Q1 and Q2) have their source and drain
terminals paralleled, while the lower transistors (Q3 and Q4) are series-connected. What this means is that
the output will go "high" (1) if either top transistor saturates, and will go "low" (0) only if both lower
transistors saturate. The following sequence of illustrations shows the behaviour of this NAND gate for all
four possibilities of input logic levels (00, 01, 10, and 11):

Fig 6.7 CMOS AND gate

JN

A CMOS NOR gate circuit (fig 6.8) uses four MOSFETs just like the NAND gate, except that its
transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 6.8: CMOS NOR Gate

connected to Vdd and two series-connected sinking (lower) transistors connected to ground, the NOR gate
uses two series-connected sourcing transistors and two parallel-connected sinking transistors like this: As
with the NAND gate, transistors Q1 and Q3 work as a complementary pair, as do transistors Q2 and Q4. Each
pair is controlled by a single input signal. If either input A or input B are "high" (1), at least one of the lower
transistors (Q3 or Q4) will be saturated, thus making the output "low" (0). Only in the event of both inputs
being "low" (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the
Conditions necessary for the output to go "high" (1). This behavior, of course, defines the NOR logic function.

JN

TU

The OR function may be built up from the basic NOR gate with the addition of an inverter stage on
the output (fig 6.9):

Fig 6.9: CMOS OR Gate

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

Fig: 6.10 CMOS open drain

ld

6.7 MOS & CMOS OPEN DRAIN

www.alljntuworld.in

The term open drain means that the drain terminal of the output transistor is unconnected and must be
connected externally to VDD through a load.

An open-drain output circuit is a single n-channel MOSFET as shown in fig 6.10. It is used to produce a
HIGH output state.
6.8CMOS TRISTATE OUTPUTS

JN

TU

The tristate output combines the advantages of the totem-pole and open-collector circuits.

Fig 6.11: CMOS Tristate outputs

From the fig 6.11 when the enable input is LOW, the device is enabled for normal logic operation . when the
enable is HIGH both Q1 and Q2 are OFF, and the circuit is in the high Z-state.
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

6.9COMPARISION OF VARIOUS LOGIC FAMILIES

Bipolar(TTL)

CMOS
5V

LS

ALS

HC

AC

tp(ns)

3.3

10

Max.clock
Freq(MHz)

145

33

45

50

160

2.2

1.4

20

LVC

0.55

24

ALVC

3.7

4.3

170

90

100

150

2.75

1.6

0.8

0.8

12

24

24

JN

TU

Output
drive(mA)

2.75

power
dissipation
per gate
TTL(mW)
CMOS(W)

LV

or

speed

AHC

ld

3.3V

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

BIPOLAR(TTL)

CMOS

BIPOLAR(ECL)

AHC

10H

E-LITE

tp(ns)

3.3

3.7

0.22

Max.clock
Freq(MHz)

145

170

330

2800

8.9mW

2.5W

Where tp is the propagation delay in ns

25mW

73mW

or

s power dissipation
per gate

ld

speed

6.10 IC INTERFACING-CMOS DRIVING TTL AND CMOS DRIVING TTL

Interfacing ICs under 5Volts power supply

JN

TU

1) Interfacing a CMOS to a TTL under 5Volts power supply

Fig. 6.12.a

Fig. 6.12.b

Fig 6.12a and 6.12b showing interfacing CMOS to TTL

The high state of the CMOS output is enough to drive directly a TTL input into high state without problems.
The low state, could cause malfunctions in some cases. Is it possible to sink a TTL input current into low
state without exceeding the maximum value of the TTL low state input voltage? Typical CMOS gates are

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

specified to sink about 0.4 mA in the low state while maintaining an output voltage of 0.4 volts or less,
sufficient to drive two LS TTL inputs or one Schottky input (Fig. 6.12.a), but insufficient to drive standard
TTL. In this case, a 4041 buffer (or another buffer) should be used to eliminate this problem (Fig. 6.12.b).

or

ld

2) Interfacing a TTL to a CMOS under 5Volts power supply

Fig. 6.13: interfacing TTL to CMOS

Interfacing ICs with different power supply voltages:

JN

TU

1) Interfacing a CMOS to a TTL with different power supply voltages

Fig. 6.14: Interfacing a CMOS to a TTL with different power supply voltages

TTL with different voltages (fig 6.14) is as easy as with same voltages. The reason is because the CMOS
can be supplied also with 5V like the TTL. So, a 4041 buffer can be powered with 5V to do the interface. In
the following drawing, the 4041 could be omitted if the 4011 was supplied with 5V.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

2) Interfacing a TTL to a CMOS with different power supply voltages

Fig. 6.15.a

Fig. 6.15.b

or

Fig 6.15 (a and b): Interfacing a TTL to a CMOS with different power supply voltages

In this case, a use of NPN transistor a essential to implement the interface (Fig. 6.15.a). The base of the
transistor is controlled by the output of the TTL chip. When it is in low state, the collector voltage is nearly
the CMOS voltage. When the TTL output is driven into high state, the transistor is driven into saturation
causing the CMOS input to become nearly 0. This interface is also causing an inversion of the signal so be
sure that you have this in mind during designing.

JN

TU

Another technique is the use of an open collector TTL buffer like 7406 (Fig.6.5.b). This technique is useful if
you have multiple outputs to interface. The 7406 VDD pins are connected to the TTL's power line (5V).

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

UNIT-II
OP-AMP APPLICATIONS
2.11.3 THE OPERATIONAL AMPLIFIER:

ld

An operational amplifier is a direct-coupled high-gain amplifier usually consisting of one or more

differential amplifiers and usually followed by a level translator and an output stage. An operational
amplifier is available as a single integrated circuit package.

or

The operational amplifier is a versatile device that can be used to amplify dc as well as ac input
signals and was originally designed for computing such mathematical functions as addition,subtraction,
multiplication, and integration. Thus the name operational amplifier stems from its original use for these
mathematical operations and is abbreviated to op-amp. With the addition of suitable external feedback
components, the modern day op-amp can be used for a variety of applications, such as ac and dc signal
amplification, active filters, oscillators, comparators,regulators, and others.
1.3.1 The ideal op-amp:

An ideal op-amp would exhibit the following electrical characteristics:

TU

1. Infinite voltage gain

2. Infinite input resistance so that almost any signal source can drive it and there is no loading
on the preceding stage.
3. Zero output resistance Ro so that output can drive an infinite number of other devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to Hz can be amplified without
attenuation.
6. Infinite common mode rejection ratio so that the output common-mode noise voltage is zero.
7. Infinite slew rate so that output voltage changes occur simultaneously with input voltage
changes.
8.

JN

1.3.2 Equivalent circuit of an opamp:

Fig. 1.1 shows an equivalent circuit of an op-amp. V1 and V2are the two input voltage voltages. Ri is
the input impedance of OPAMP. Ad Vdis an equivalent Thevenins voltage source and RO is the Thevenins
equivalent impedance looking back into the terminal of an op-amp.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Fig. 1.1 Equivalent circuit of OP-AMP

This equivalent circuit is useful in analysing the basic operating principles of op-amp and in
observing the effects of standard feedback arrangements.
VO = Ad (V1-V2) = AdVd.

TU

1.3.3.Ideal Voltage Transfer Curve:

or

This equation indicates that the output voltage Vo is directly proportional to the algebraic
difference between the two input voltages. In other words the opamp amplifies the difference between the
two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage
depends on the polarity of the difference voltage Vd.

Fig. 1.2 Ideal voltage transfer curve

JN

The graphic representation of the output equation is shown infig.1.2 in which the output voltage Vo
is plotted against differential input voltage Vd, keeping gain Ad constant.
The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages
are specified for given values of supply voltages. This means that the output voltage is directly proportional
to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage
remains constant.
Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be
zero. If the curve is drawn to scale, the curve would be almost vertical because of very large values of Ad.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

1.4 INTERNAL CIRCUIT

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MHz to
which feedback is added to control its overall response characteristic i.e. gain and bandwidth. The op-amp
exhibits the gain down to zero frequency.

TU

or

ld

The internal block diagram of an opamp is shown in the fig 1.3. The input stage is the dual input
balanced output differential amplifier. This stage generally provides most of the voltage gain of the
amplifier and also establishes the input resistance of the op-amp. The intermediate stage is usually another
differential amplifier, which is driven by the output of the first stage. On most amplifiers, the intermediate
stage is dual input, unbalanced output. Because of direct coupling, the dc voltage at the output of the
intermediate stage is well above ground potential. Therefore, the level translator (shifting) circuit is used
after the intermediate stage downwards to zero volts with respect to ground. The final stage is usually a
push pull complementary symmetry amplifier output stage. The output stage increases the voltage swing
and raises the ground supplying capabilities of the op-amp. A well designed output stage also provides low
output resistance.

Fig.1.3 Block Diagram of OP-AMP

JN

1.4.1. Differential amplifier

Fig. 1.4 Differential Amplifier

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to
amplify the difference between two input signals. The two transistors Q1 and Q2 have identical
characteristics. The resistances of the circuits are equal, i.e. RE1 = R E2, RC1 = R C2 and the magnitude of +VCC
is equal to the magnitude of -VEE. These voltages are measured with respect to ground.

ld

To make a differential amplifier, the two circuits are connected as shown in fig. 1.4. The two +VCC and -VEE
supply terminals are made common because they are same. The two emitters are also connected and the
parallel combination of RE1 and RE2 is replaced by a resistance RE. The two input signals v1& v2 are applied at
the base of Q1 and at the base of Q2. The output voltage is taken between two collectors. The collector
resistances are equal and therefore denoted by RC = RC1 = RC2.
Ideally, the output voltage is zero when the two inputs are equal. When v1 is greater then v2 the output
voltage with the polarity shown appears. When v1 is less than v2, the output voltage has the opposite
polarity.

TU

or

The differential amplifiers are of different configurations.

JN

Fig1.5. Dual input, balanced output differential amplifier.Fig.1.6. Dual input, unbalanced output differential amplifier.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Fig.1.7.Single input, balanced output differential amplifierFig.1.8.Single input, unbalanced output differential amplifier

The four differential amplifier configurations are following:

1.
2.
3.
4.

Dual input, balanced output differential amplifier.

Dual input, unbalanced output differential amplifier.
Single input balanced output differential amplifier.
Single input unbalanced output differential amplifier.

or

ld

These configurations are shown in fig(1.5,1.6,1.7, 1.8), and are defined by number of input signals used and
the way an output voltage is measured. If use two input signals, the configuration is said to be dual input,
otherwise it is a single input configuration. On the other hand, if the output voltage is measured between
two collectors, it is referred to as a balanced output because both the collectors are at the same dc
potential w.r.t. ground. If the output is measured at one of the collectors w.r.t. ground, the configuration is
called an unbalanced output.

A multistage amplifier with a desired gain can be obtained using direct connection between successive
stages of differential amplifiers. The advantage of direct coupling is that it removes the lower cut off
frequency imposed by the coupling capacitors, and they are therefore, capable of amplifying dc as well as
ac input signals.

1) Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig.1.10V1 and V2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials.

JN

TU

D.C. Analysis:To obtain the operating point (ICQ and VCEQ) for differential amplifier dc equivalent circuit is
drawn by reducing the input voltages V1 and V2 to zero as shown in fig1.9

Fig.1.9Differential Amplifier
The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both emitter biased
sections of the different amplifier are symmetrical in all respects, therefore, the operating point for only

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

one section need to be determined. The same values of ICQ and VCEQ can be used for second transistor Q2.

or

ld

Applying KVL to the base emitter loop of the transistor Q1.

The value of RE sets up the emitter current in transistors Q1 and Q2 for a given value of VEE. The emitter
current in Q1 and Q2 are independent of collector resistance RC.

JN

TU

The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is negligible.
Knowing the value of IC the voltage at the collector VCis given by

Fig.1.10 Differential Amplifier

VC =VCC- IC RC

and VCE = VC- VE

= VCC - IC RC + VBE
VCE = VCC + VBE - ICRC

(E-2)

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

From the two equations VCEQ and ICQ can be determined. This dc analysis is applicable for all types of
differential amplifier.
A.C. Analysis :
The circuit is shown in fig.1.10 V1 and V2 are the two inputs, applied to the bases of Q1 and Q2 transistors.
The output voltage is measured between the two collectors C1 and C2, which are at same dc potentials.

or

ld

In previous lecture dc analysis has been done to obtain the operating point of the two transistors.To
find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac equivalent circuit is
drawn using r-parameters as shown infig1.11. The dc voltages are reduced to zero and the ac equivalent of
CE configuration is used.

TU

Fig.1.11Differential Amplifier A/C Analysis

Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and designated
by r'e . This voltage across each collector resistance is shown 180 out of phase with respect to the input
voltages v1 and v2. This is same as in CE configuration. The polarity of the output voltage is shown in Figure.
The collector C2 is assumed to be more positive with respect to collector C1 even though both are negative
with respect to ground.

JN

Applying KVL in two loops 1 & 2.

Substituting current relations,

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

TU

The output voltage VO is given by

or

Solving these two equations, ie1 and ie2 can be calculated.

ld

Again, assuming RS1 / and RS2 / are very small in comparison with RE and re' and therefore neglecting these
terms,

JN

Substituting ie1, & ie2 in the above expression

Thus a differential amplifier amplifies the difference between two input signals. Defining the
difference of input signals as Vd =V1-V2 the voltage gain of the dual input balanced output differential
amplifier can be given by

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

(E-2)

JNTU World

Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be measured at
either input terminal with the other terminal grounded. This means that the input resistance Ri1 seen from
the input signal source V1 is determined with the signal source V2 set at zero. Similarly, the input signal V1

or

ld

set at zero to determine the input resistance Ri2 seen from the input signal source V2. Resistance RS1 and RS2
are ignored because they are very small.

Substituting ie1,

TU

Similarly

The factor of 2 arises because the re' of each transistor is in series.To get very high input impedance
with differential amplifier is to use Darlington transistors. Another ways is to use FET.

Output Resistance:

JN

Output resistance is defined as the equivalent resistance that would be measured at output
terminal with respect to ground. Therefore, the output resistance RO1 measured between collector C1 and
ground is equal to that of the collector resistance RC. Similarly the output resistance RO2 measured at C2
with respect to ground is equal to that of the collector resistor RC.
RO1 = RO2 = RC

(E-5)

The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier
is a small signal amplifier. It is generally used as a voltage amplifier and not as current or power amplifier.

2) Dual Input, Unbalanced Output Differential Amplifier:

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

or

Fig. 1.12Differential Amplifier

In this case, two input signals are given however the output is measured at only one of the twocollector w.r.t. ground as shown infig1.12. The output is referred to as an unbalanced output because the
collector at which the output voltage is measured is at some finite dc potential with respect to ground.

TU

In other words, there is some dc voltage at the output terminal without any input signal applied. DC
analysis is exactly same as that of first case.

AC Analysis:

JN

The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the
output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is normally
followed by a level translator circuit.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

1.4.2. Level Translator:

Because of the direct coupling the dc level at the emitter rises from
stages to stage. This increase in dc level tends to shift the operating
point of the succeeding stages and therefore limits the output
voltage swing and may even distort the output signal.

ld

To shift the output dc level to zero, level translator circuits are used.
An emitter follower with voltage divider is the simplest form of level
translator as shown in fig 1.13

or

Thus a dc voltage at the base of Q produces 0V dc at the output. It is

decided by R1 and R2. Instead of voltage divider emitter follower
either with diode current bias or current mirror bias as shown in fig
1.14may be used to get better results.

Fig.1.13 Level Translator

TU

In this case, level shifter, which is common collector amplifier, shifts

the level by 0.7V. If this shift is not sufficient, the output may be
taken at the junction of two resistors in the emitter leg.

JN

Fig1.14 Common collector Amplifier

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

Fig.1.15 shows a complete opamp circuit having input different amplifiers with balanced output,
intermediate stage with unbalanced output, level shifter and an output amplifier.

Fig.1.15 Circuit Diagram of OP-AMP

TU

1.5 OP-AMP CHARACTERISTICS

1. 5.1 DC CHARACTERISTICS:

a)Input offset voltage:

JN

Input offset voltage Vio is the differential input voltage that exists between two input terminals of an
op-amp without any external inputs applied. In other words, it is the amount of the input voltage that
should be applied between two input terminals in order to force the output voltage to zero. Let us denote
the output offset voltage due to input offset voltage Vio as Voo. The output offset voltage Voo is caused by
mismatching between two input terminals. Even though all the components are integrated on the same
chip, it is not possible to have two transistors in the input differential amplifier stage with exactly the same
characteristics. This means that the collector currents in these two transistors are not equal, which causes a
differential output voltage from the first stage. The output of first stage is amplified by following stages and
possibly aggravated by more mismatching in them.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

Fig 1.17 Output offset voltage in opamp

TU

or

Fig 1.16input offset voltage in opamp

Fig 1.18.Op-Amp with offset voltage compensating network

JN

The op-amp with offset-voltage compensating network is shown in Figure1.18. The

Compensating network consists of potentiometer Ra and resistors Rb and Re.
To establish a relationship between Vio, supply voltages, and the compensating components,
firstThevenize the circuit, looking back into Ra from point T. The maximum Thevenins equivalentresistance
Rmax, occurs when the wiper is at the center of the Potentiometer, as shown in Figure.

Rmax =(R a /2)||(R a /2)

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Supply voltages VCCand -VEEare equal in magnitude therefore; let us denote their magnitude byvoltage V.
Thus Vmax= V

or

where V2 has been expressed as a function of maximum Thevenins voltage Vmax

and maximum Thevenins resistance, But the maximum value of V2 can be equal to Vio since V1
V2 = Vio. Thus Equation becomes

Assume Rb >Rmax >Rc, where Rmax = Ra/4. Using this assumption Rmax+Rb+Rc=Rb

JN

TU

Therefore

Let us now examine the effect of Vio in amplifiers with feedback. The non-inverting and inverting
amplifiers with feedback are shown in Figure.1.19To determine the effect of Vio, in each case, we have to
reduce the input voltage vin to zero.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

or

Fig 1.19 Closed loop non inverting or inverting Amp

JN

TU

With vin reduced to zero, the circuits of both non-inverting and inverting amplifiers are the sameas the
circuit in Figure. The internal resistance Rin of the input signal voltage is negligibly small.In the figure, the
non-inverting input terminal is connected to ground; therefore, assume voltageV1 at input terminal to be
zero. The voltageV2 at the inverting input terminal can be determinedby applying the voltage-divider rule:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

b)

JNTU World

Input offset voltage

A small voltage applied to the input terminals to make the output voltage as zero when
the two input terminals are grounded is called input offset voltage

c)Input bias current

ld

Input bias current IB as the average value of the base currents entering into terminal of an op-

JN

TU

or

amp

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

TU

Obtaining the expression for the output offset voltage caused by the inputbias current IB in the
inverting and non-inverting amplifiers and then devise some scheme toeliminate or minimize it.

Fig 1.20 Op-Amp

JN

In the figure, the input bias currents 81 and 1 are flowing into the non-inverting and invertinginput
leads, respectively. The non-inverting terminal is connected to ground; therefore, thevoltage V1 = 0 V. The
controlled voltage source A Vio =0 V since Vio= 0 V is assumed. Withoutput resistance Ro is negligibly small,
the right end of RF is essentially at ground potential; thatis, resistors R1, and RF are in parallel and the bias
current I, flows through them. Therefore, thevoltage at the inverting terminal is

d)Thermal Drift:

Bias current, offset current and offset voltage change with temperature. A circuit carefully nulled at
25oc may not remain so when the temperature rises to 35oc. This is called drift

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

1.5.2 AC CHARACTERISTICS:
a) Slew rate
b) Frequency Response
Need for frequency compensation in practical op-amps:
Frequency compensation is needed when large bandwidth and lower closed loop gain is desired.
Compensating networks are used to control the phase shift and hence to improve the stability
Frequency compensation methods :

ld

a)Dominant- pole compensation

b)Pole- zero compensation

or

a)Slew Rate

The slew rate is defined as the maximum rate of change of output voltage caused by a step input voltage.
An ideal slew rate is infinite which means that op-amps output voltage should change instantaneously in
response to input step voltage.

TU

The symbolic diagram of an OPAMP is shown in fig1.21

Fig.1.21 Op-Amp Symbol

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

1.5.3.Parameters of OPAMP:

JN

The various important parameters of OPAMP are follows:

1.Input Offset Voltage:

Fig. 1.22input 0ffset voltage

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

If no external input signal is applied to the op-amp at the inverting and non-inverting terminals the output
must be zero. That is, if Vi=0, Vo=0. But as a result of the given biasing supply voltages, +Vcc and Vcc, a
finite bias current is drawn by the op-amps, and as a result of asymmetry on the differential amplifier
configuration, the output will not be zero. This is known as offset. Since Vo must be zero when Vi=0 an input
voltage must be applied such that the output offset is cancelled and Vo is made zero. This is known as input
offset voltage. Input offset voltage (Vio) is defined as the voltage that must be applied between the two
input terminals of an OPAMP to null or zero the output voltage. Fig 1.22, shows that two dc voltages are
applied to input terminals to make the output zero.
Vio = Vdc1- Vdc2

ld

Vdc1 and Vdc2 are dc voltages and RS represents the source resistance. Vio is the difference of Vdc1 and Vdc2. It
may be positive or negative. For a 741C OPAMP the maximum value of Vio is 6mV. It means a voltage 6 mV
is required to one of the input to reduce the output offset voltage to zero. The smaller the input offset
voltage the better the differential amplifier, because its transistors are more closely matched

or

2.Input offset Current:

Iio = | IB1- IB2 |

Though for an ideal op-amp the input impedance is infinite, it is not so practically. So the IC draws current
from the source, however smaller it may be. This is called input offset current Iio. The input offset current Iio
is the difference between the currents into inverting and non-inverting terminals of a balanced amplifier as
shown in fig 1.22.

The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the
difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further.For a precision OPAMP
741C, Iio is 6 nA
3.Input Bias Current:

TU

The input bias current IB is the average of the current entering the input terminals of a balanced amplifier
i.e.
IB = (IB1 + IB2 ) / 2

JN

For ideal op-amp IB=0. For 741C IB(max) = 700 nA and for precision 741C IB = 7 nA

4. Differential Input Resistance: (Ri)

Ri is the equivalent resistance that can be measured at either the inverting or non-inverting input terminal
with the other terminal grounded. For the 741C the input resistance is relatively high 2 M. For some
OPAMP it may be up to 1000 G ohm.
5. Input Capacitance: (Ci)

Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal with
the other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C.
6. Offset Voltage Adjustment Range:
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be
done by connecting 10 K ohm pot between 1 and 5 as shown infig1.23

Fig. 1.23 Op-Amp Offset network

ld

By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts.
Thus the offset voltage adjustment range is the range through which the input offset voltage can be
adjusted by varying 10 K pot. For the 741C the offset voltage adjustment range is 15 mV.

7. Input Voltage Range :

8. Common Mode Rejection Ratio (CMRR).

or

Input voltage range is the range of a common mode input signal for which a differential amplifier
remains linear. It is used to determine the degree of matching between the inverting and non-inverting input
terminals. For the 741C, the range of the input common mode voltage is 13V maximum. This means that
the common mode voltage applied at both input terminals can be as high as +13V or as low as -13V.

CMRR = Ad / ACM.

CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM

For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two
input terminals and the smaller is the output common mode voltage

TU

9. Supply voltage Rejection Ratio: (SVRR)

SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply
voltages. This is expressed inV / V or in decibels, SVRR can be defined as
SVRR =Vio / V

JN

Where V is the change in the input supply voltage and Vio is the corresponding change in the offset
voltage.
For the 741C, SVRR = 150 V / V.
For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3=
10K. For same OPAMPS, SVRR is separately specified as positive SVRR and negative SVRR.
10.Large Signal Voltage Gain:
Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier
is defined as

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Because output signal amplitude is much large than the input signal the voltage gain is commonly called large
signal voltage gain. For 741C is voltage gain is 200,000 typically.
11. Output voltage Swing: The ac output compliance PP is the maximum unclipped peak to peak output
voltage that an OPAMP can produce. Since the quiescent output is ideally zero, the ac output voltage can
swing positive or negative. This also indicates the values of positive and negative saturation voltages of the
OP-AMP. The output voltage never exceeds these limits for a given supply voltages +VCC and -VEE. For a
741C it is 13 V.
12. Output Resistance: (RO)

ld

RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the
ground. It is 75 ohm for the 741C OPAMP.
13. Output Short circuit Current :

or

In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output
impedance is 75 ohm but cannot supply large currents. Since OPAMP is low power device and so its output
current is limited. The 741C can supply a maximum short circuit output current of only 25mA.
14. Supply Current :

15. Power Consumption:

IS is the current drawn by the OP-AMP from the supply. For the 741C OPAMP the supply current is 2.8 m A.

Power consumption (PC) is the amount of quiescent power (Vin= 0V) that must be consumed by the OPAMP
in order to operate properly. The amount of power consumed by the 741C is 85 m W.

TU

16. Gain Bandwidth Product:

JN

The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to
1. From open loop gain vs frequency graph At 1 MHz shown in.fig.1.24,it can be found 1 MHz for the 741C
OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000 and cut off frequency is 10Hz.

Fig.1.24 Band width of OP-AMP

17. Slew Rate:
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal
conditions and is expressed in volts / secs.

or

Fig. 1.25 Charging Capacitor

To understand this, consider a charging current of a capacitor shown in fig.1.25

TU

If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited.Slew rate
indicates how rapidly the output of an OP-AMP can change in response to changes in the input frequency
with input amplitude constant. The slew rate changes with change in voltage gain and is normally specified at
unity gain.
If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is
low 0.5 V / S. which limits its use in higher frequency applications.
18. Input Offset Voltage and Current Drift:

JN

It is also called average temperature coefficient of input offset voltage or input offset current. The input
offset voltage drift is the ratio of the change in input offset voltage to change in temperature and expressed
in V / C. Input offset voltage drift = ( Vio /T).
Similarly, input offset current drift is the ratio of the change in input offset current to the change in
temperature. Input offset current drift = ( Iio / T).
For 741C,

Vio / T = 0.5 V / C.
Iio/ T = 12 pA / C.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

1.6 PIN DIAGRAM OF 741-OP AMP

or

1.7FEATURES OF 741 OP-AMP:

1. No External frequency compensation is required

2. Short circuit Protection

3. Off Set Null Capability

4. Large Common mode and differential Voltage ranges

5. Low Power Dissipation
6. No-Latch up Problem

TU

7.741 is available in three packages :- 8-pin metal can, 10-pin flat pack and 8 or 14-pin DI.

1.8.MODES OF OPERATION OF OP-AMP

There are 2 modes in which an op-amp operates:

JN

1. open loop mode

2. closed loop mode

1.8.1 Open loop OPAMP mode:

In the case of amplifiers the term open loop indicates that no connection exists between input and
output terminals of any type. That is, the output signal is not fedback in any form as part of the input signal.
In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop
OPAMP configurations.
1. The Differential Amplifier:
Fig. 1.26, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to
the positive and negative input terminals.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Fig. 1.26 Differential Amplifier

Since the OPAMP amplifies the difference the between the two input signals, this configuration is
called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source resistance
Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across these
resistances can be assumed to be zero.
Therefore

ld

v1 = vin1 and v2 = vin2.

vo = Ad (vin1- vin2 )
where, Ad is the open loop gain.

or

2. The Inverting Amplifier:

If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is
called inverting amplifier.This configuration is shown infig.1.27.
v1= 0, v2 = vin.

TU

vo = -Ad vi

Fig.1.27 Inverting Amplifier

JN

The negative sign indicates that the output voltage is out of phase with respect to input 180 or is
of opposite polarity. Thus the input signal is amplified and inverted also.
3 .The non-inverting amplifier:
In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is
ground as shown in fig.1.28
v1 = +vin ,

v2 = 0

vo = +Ad vin

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

This means that the input voltage is amplified by Ad and there is no phase reversal at the output.

Fig.1.28 Non Inverting Amplifier

In all there configurations any input signal slightly greater than zero drive the output to saturation
level. This is because of very high gain. Thus when operated in open-loop, the output of the OPAMP is either
negative or positive saturation or switches between positive and negative saturation levels. Therefore open
loop op-amp is not used in linear applications.
1.8.2. Closed Loop mode:

TU

The Open Loop Gain of an ideal operational amplifier can be very high, as much as 1,000,000
(120dB) or more. However, this very high gain is of no real use to us as it makes the amplifier both
unstable and hard to control as the smallest of input signals, just a few micro-volts, (V) would be
enough to cause the output voltage to saturate and swing towards one or the other of the voltage
supply rails losing complete control of the output.

JN

As the open loop DC gain of an operational amplifier is extremely high we can therefore afford to lose
some of this high gain by connecting a suitable resistor across the amplifier from the output terminal
back to the inverting input terminal to both reduce and control the overall gain of the amplifier. This
then produces and effect known commonly as Negative Feedback, and thus produces a very stable
Operational Amplifier based system.
Negative Feedback is the process of "feeding back" a fraction of the output signal back to the input,
but to make the feedback negative, we must feed it back to the negative or "inverting input" terminal
of the op-amp using an external Feedback Resistor called R. This feedback connection between the
output and the inverting input terminal forces the differential input voltage towards zero.

This effect produces a closed loop circuit to the amplifier resulting in the gain of the amplifier now
being called its Closed-loop Gain. Then a closed-loop inverting amplifier uses negative feedback to
accurately control the overall gain of the amplifier, but at a cost in the reduction of the amplifiers
bandwidth.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

This negative feedback results in the inverting input terminal having a different signal on it than the
actual input voltage as it will be the sum of the input voltage plus the negative feedback voltage
giving it the label or term of a Summing Point. We must therefore separate the real input signal from
the inverting input by using an Input Resistor, Rin.
As we are not using the positive non-inverting input this is connected to a common ground or zero

or

1.2.8.1 Inverting Amplifier Configuration

ld

voltage terminal as shown below, but the effect of this closed loop feedback circuit results in the
voltage potential at the inverting input being equal to that at the non-inverting input producing a
Virtual Earth summing point because it will be at the same potential as the grounded reference input.
In other words, the op-amp becomes a "differential amplifier".

Fig 1.29 inverting amplifier with feedback.

TU

In this Inverting Amplifier circuit the operational amplifier is connected with feedback to produce a
closed loop operation. For ideal op-amps there are two very important rules to remember about
inverting amplifiers, these are: "no current flows into the input terminal" and that "V1 equals V2", (in
real world op-amps both of these rules are broken).

JN

This is because the junction of the input and feedback signal ( X ) is at the same potential as the
positive ( + ) input which is at zero volts or ground then, the junction is a "Virtual Earth". Because
of this virtual earth node the input resistance of the amplifier is equal to the value of the input resistor,
Rin and the closed loop gain of the inverting amplifier can be set by the ratio of the two external
resistors.
We said above that there are two very important rules to remember about Inverting Amplifiers or
any operational amplifier for that matter and these are.

1. No Current Flows into the Input Terminals

2. The Differential Input Voltage is Zero as V1 = V2 = 0 (Virtual Earth)

Then by using these two rules we can derive the equation for calculating the closed-loop gain of an
inverting amplifier, using first principles.
Current ( i ) flows through the resistor network as shown.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

JN

Then, the Closed-Loop Voltage Gain of an Inverting Amplifier is given as.

and this can be transposed to give Vout as:

The negative sign in the equation indicates an inversion of the output signal with respect to the input
as it is 180o out of phase. This is due to the feedback being negative in value.

1.8.2.2 The Non-inverting Amplifier

The second basic configuration of an operational amplifier circuit is that of a Non-inverting

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Amplifier. In this configuration, the input voltage signal, ( Vin ) is applied directly to the noninverting ( + ) input terminal which means that the output gain of the amplifier becomes "Positive" in
value in contrast to the "Inverting Amplifier" circuit we saw in the last tutorial whose output gain is
negative in value. The result of this is that the output signal is "in-phase" with the input signal.

or

Non-inverting Amplifier Configuration

ld

Feedback control of the non-inverting amplifier is achieved by applying a small part of the output
voltage signal back to the inverting ( - ) input terminal via a R - R2 voltage divider network, again
producing negative feedback. This closed-loop configuration produces a non-inverting amplifier
circuit with very good stability, a very high input impedance, Rin approaching infinity, as no current
flows into the positive input terminal, (ideal conditions) and a low output impedance, Rout as shown
below.

TU

Fig 1.30 Non-inverting amplifier with feedback.

As said in theInverting Amplifierthat "no current flows into the input" of the amplifier and that "V1
equals V2". This was because the junction of the input and feedback signal ( V1 ) are at the same
potential. In other words the junction is a "virtual earth" summing point. Because of this virtual earth
node the resistors, R and R2 form a simple potential divider network across the non-inverting
amplifier with the voltage gain of the circuit being determined by the ratios of R2 and R as shown
below.

JN

Equivalent Potential Divider Network

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

Fig 1.31 potential divider in non-inverting op-amp

JN

TU

or

From the fig 1.31 using the formula to calculate the output voltage of a potential divider network, we
can calculate the closed-loop voltage gain ( A V ) of the Non-inverting Amplifier as follows:

Then the closed loop voltage gain of a Non-inverting Amplifier is given as:

We can see from the equation above, that the overall closed-loop gain of a non-inverting amplifier
will always be greater but never less than one (unity), it is positive in nature and is determined by the
ratio of the values of R and R2. If the value of the feedback resistor R is zero, the gain of the
amplifier will be exactly equal to one (unity). If resistor R2 is zero the gain will approach infinity, but

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

in practice it will be limited to the operational amplifiers open-loop differential gain, ( Ao ).

Voltage Follower (Unity Gain Buffer)

ld

If we made the feedback resistor, R equal to zero, (R = 0), and resistor R2 equal to infinity,
(R2 = ) as shown in fig 1.32, then the circuit would have a fixed gain of "1" as all the output voltage
would be present on the inverting input terminal (negative feedback). This would then produce a
special type of the non-inverting amplifier circuit called a Voltage Follower or also called a "unity
gain buffer".

or

As the input signal is connected directly to the non-inverting input of the amplifier the output signal is
not inverted resulting in the output voltage being equal to the input voltage, Vout = Vin. This then
makes the voltage follower circuit ideal as a Unity Gain Buffer circuit because of its isolation
properties as impedance or circuit isolation is more important than amplification while maintaining
the signal voltage. The input impedance of the voltage follower circuit is very high, typically above
1M as it is equal to that of the operational amplifiers input resistance times its gain ( Rin x Ao ).
Also its output impedance is very low since an ideal op-amp condition is assumed.

Fig 1.32 voltage follower

JN

TU

In this non-inverting circuit configuration, the input impedance Rin has increased to infinity and the
feedback impedance R reduced to zero. The output is connected directly back to the negative
inverting input so the feedback is 100% and Vin is exactly equal to Vout giving it a fixed gain of 1 or
unity. As the input voltage Vin is applied to the non-inverting input the gain of the amplifier is given
as:

Therefore,

One final thought, the output voltage gain of the voltage follower circuit with closed loop gain is
Unity, the voltage gain of an ideal operational amplifier with open loop gain (no feedback) is Infinite.
Then by carefully selecting the feedback components we can control the amount of gain produced by

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

an operational amplifier anywhere from one to infinity.

INSTRUMENTATION AMPLIFIER:

TU

or

ld

In many industrial and consumer applications the measurement and control of physical
conditions are very important.For example measurements of temperature and humidity inside a
dairy or meat plant permit the operator to make necessary adjustments to maintain product
quality.Similarly,precise temperature control of plastic furnace is needed to produce a
particular type of plastic.

Fig.2.1 Instrumentation Amplifier

JN

The transducer is a device that converts one form of energy into another. For example a
strain gage when subjected to pressure or force undergoes a change in its resistance (electrical
energy).An instrumentation system is used to measure the output signal produced by a
transducer and often to control the physical signal producing it.

Above fig shows a simplified form of such a system.The input stage is composed of a preamplifier and some sort of transducer,depending on the physical quantity to be measured..The
output stage may use devices such as meters,oscilloscopes,charts,or magnetic records.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

In Figure 2.1 the connecting lines between the blocks represent

transmis- sion lines, used especially when the transducer is at a remote
test site monitoring hazardous conditions such as high temperatures or
liquid levels of flammable chemicals. These transmission lines permit
signal transfer from unit to unit. The length of the transmission lines
depends primarily on the physical quantities tobe monitored and on
system requirements.

or

The signal source of the instrumentation amplifier is the output of

the trans- ducer. Although some transducers produce outputs with
sufficient strength to per- m.; their use directly, many do not. To amplify
the low-level output signal of the transducer so that it can drive the
indicator or display is the major function of the instrumentation amplifier.
In short, the instrumentation amplifier is intended for precise, low-level
signal amplification where low noise, low thermal and time
drifts, high input resistance, and accurate closed-loop gain are
required. Besides, low power consumption, high common-mode
rejection ratio, and high slew rate are desirable for superior
performance.

TU

There are many instrumentation operational amplifiers, such as

the /LA 725, ICL7605, and LH0036, that make a circuit extremely stable
and accurate. These
ICs are, however, relatively expensive; they are very precise specialpurpose cir- cuits in which most of the electrical parameters, such as
offsets, drifts, and power consumption, are minimized, whereas input
resistance, CMRR, and supply range are optimized. Some
instrumentation amplifiers are even available in modular form to suit
special installation requirements.

JN

Obviously, the requirements for instrumentation op-amps are

more rigid than those for general-purpose applications. However, where
the requirements are not too strict, the general-purpose op-amp can be
employed in the differential mode.
We will call such amplifiers differential instrumentation amplifiers.
Since most instrumentation systems use a transducer in a bridge
circuit, we will consider a simplified differential instrumentation
system arrangement using a transducer bridge circuit.

2.1.1.Instrumentation Amplifier Using Transducer Bridge

Figure 2.2 shows a simplified differential instrumentation amplifier using a transducer

bridge. A resistive transducer whose resistance changes as a function of some physical
energy is connected in one arm of the Bridge with a small circle around it and is denoted by
(RT R), where RTis the resistance of the transducer and R the change in resistance RT.
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Va=Vb

TU

or

and the desired application.

ld

Generally, resistors RA, RBand Rc are selected so that they are equal in
value to the transducer resistance RT at some reference condition. The
reference condition is the specific value of the physical quantity under
measurement
at
which
the bridge is balanced. This value is normally
established by the designer and depends on the transducer's characteristics,
the type of physical quantity to be measured,

JN

The bridge is balanced initially at a desired reference condition. However, as

the physical quantity to be measured changes, the resistance of the transducer also
changes, which causes the bridge to unbalance. The output voltage of the bridge can be
expressed as a function of the change in resistance of the transducer, as described next.

The negative (-) sign in this equation indicates that Va <Vb because of the
in- crease in the value of R. The output voltage Vab of the bridge is then applied to
the differential instrumentation amplifier composed of three op-amps (see Figure 22). The voltage followers preceding the basic differential amplifier help to
eliminate loading of the bridge circuit. The gain of the basic differential
amplifier is (-RF/ R,); there- fore, the output Va of the circuit is

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

TU

or

ld

The equation indicates that Va is directly proportional to the change in

resistance flR of the transducer. Since the change in resistance is caused by a
change in physical energy, a meter connected at the output can be calibrated
in terms of the units of that physical energy.

JN

Fig.2.2Circuit Diagram of Instrumentation Amplifier

Before proceeding with specific bridge applications, let us briefly

consider the important characteristics of some, resistive types of transducers.
In these re- sistive types of transducers the resistance of the transducer
changes
as
a
function of
some
physical
quantity.
Thermistors,
photoconductive cells, and strain gages are some of the most commonly
used resistive transducers; hence they will be fur- ther discussed here.

Thermistors are essentially semiconductors that behave as resistors, usually with a negative
temperature coefficient of resistance. That is, as the temperature of a thermistor
increases, its resistance decreases. The temperature coefficient of resistance is expressed
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

in ohms per unit change in degrees Celsius. Thermistors with a high temperature
JNTU World
coefficient of resistance are more sensitive to temperature change and are therefore well
suited to temperature measurement and control. Thermistors are available in a wide
variety of shapes and sizes. However, thermistor beads sealed in the
tips
of
glass
rods
are
most
commonly
used
because they are
relatively easy to mount.

JN

TU

or

ld

2.2 AC AMPLIFIER

Fig 2.2.1(a) AC Inverting Amplifier (b)AC Non Inverting Amplifier

2.3 .V to I Converter:

Fig.2.3, shows a voltage to current converter in which load resistor RL is floating (not connected to
ground). The input voltage is applied to the non-inverting input terminal and the feedback voltage
across R drives the inverting input terminal. This circuit is also called a current series negative
feedback, amplifier because the feedback voltage across R depends on the output current iL and is in
series with the input difference voltage Vd.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Writing the voltage equation for the input loop.

vin = vd + vf
But vd since A is very large,therefore,

vin = vf
vin = R iin
iin = v in / R.

ld

and since input current is zero.

iL = iin = vin ./ R

2.3.1Grounded LoadV to I Converter:

or

The value of load resistance does not appear

in this equation. Therefore, the output current
is independent of the value of load resistance.
Thus the input voltage is converted into
current, the source must be capable of
supplying this load current.

Fig.2.3 Circuit Diagram of V to I Converter

If the load has to be grounded, then the above circuit cannot be used. The modified circuit is shown in
fig.2.4.

TU

Since the collector and emitter currents are equal to a close

approximation and the input impedance of OPAMP is very
high,the load current also flows through the feedback resistor R.
On account of this, there is still current feedback, which means
that the load current is stabilized.

Since vd= 0
v2 = v1 = vin
iout = (vCC- vin ) / R

JN

Thus the load current becomes nearly equal to iout. There is a

limit to the output current that the circuit can supply. The base
current in the transistor equals
iout / dc. Since the op-amp has
to supply this base current iout /dc must be less than Iout (max) of
the op-amp, typically 10 to 15mA.
There is also a limit on the output voltage, as the load resistance
increases, the load voltage increases and then the transistor
goes into saturation. Since the emitter is at Vin w. r. t. ground, the
maximum load voltage is slightly less than Vin.

Fig.2.4Circuit Diagram of V to I
ConverterGrounded load

In this circuit, because of negative feedback VBEis automatically adjusted. For instance, if the load resistance decreases
the load current tries to increase. This means that more voltage is feedback to the inverting input, which decreases VBE
just enough to almost completely nullify the attempted increase in load current. From the output current expression it is
clear that as Vin increases the load current decreases.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

Another circuit in which load current increases as Vin increases is shown in fig.2.5.

or

The current through the first transistor is

i = vin / R

This current produces a collector voltage of vC =

vCC- i R = vCC-vin

vCC - (vCC - vin ) = vin

Since this voltage drives the non-inverting input of

the second op-amp. The inverting voltage is vCC- vin
to a close approximation. This implies that the
voltage across the final R is

TU

and the output current .

iout = vin / R

Fig.2.5Circuit Diagram of V to I Converter

JN

As before, this output current must satisfy the

condition,that Iout/ dc must be less than the
Iout(max) of the OPAMP. Furthermore, the load
voltage cannot exceed vCC- vin because of
transistor saturation, therefore Iout R must be less
than vCC- vin.This current source produces
unidirectional load current. fig.2.6, shows a
Howland current source, that can produce a bidirectional load current.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig.2.6Circuit Diagram of V to I Converter

2.4 I to V Converter:

The maximum load current is VCC/ R. In this circuit v in

may be positive or negative.

Current to voltage converter:

JN

TU

The circuit shown in fig.2.7, is a current to voltage converter.

Fig.2.7Circuit Diagram of I to V Converter

Due to virtual ground the current through R is zero and the input current flows through Rf. Therefore,
vout =-Rf * iin
The lower limit on current measure with this circuit is set by the bias current of the inverting input.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

2.5 SAMPLE AND HOLD CIRCUITS:

ld

The sample and hold circuit ,as its name implies samples an i/p signal and holds on to it last sampled
value until the i/p is sampled again.Below fig shows a sample and hold circuit using an op-amp with an EMOSFET.In this circuit the E-MOSFET works as a switch that is controlled by the sample and control voltage
Vs,and the capacitor C serves as a storage element.

or

The analog signal Vin to be sampled is applied to the drain, and sample and hold control voltage Vs
is applied to the gate of the E-MOSFET.During the positive portion of the Vs, the EMOSFET conducts and
acts as a closed switch.This allows i/p voltage to charge capacitor C.In other words input voltage appears
across C and in turn at the o/p as shown in above fig.2.9.On the other hand,when Vs is zero,the EMOSFET is
off and acts as open switch.The only discharge path for C is, through the op-amp.However the i/p resistance
of the op-amp voltage follower is also very high; hence the voltage across C is retained.

JN

TU

The time periods Ts of the sample-and-hold control voltage Vs during which the voltage across the
capacitor is equal to the i/p voltage are called sample periods.The time periods TH of Vs during which the
voltage across the capacitor is constant are called hold periods.The o/p of the op-amp is usually
processed/observed during hold periods.To obtain the close approximation of the i/p waveform,the
frequency of the sample-and-hold control voltage must be significantly higher than that of the i/p

Fig.2.8 sample and hold circuit

Fig2.9 I/P and O/P wave forms

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

2.6 DIFFERENTIATOR

or

ld

A circuit in which the output voltage waveform is the differentiation of input voltage is called
differentiator as shown infig.2.10.

Fig.2.10 Circuit Diagram of Differentiator

TU

The expression for the output voltage can be obtained from the Kirchoff's current equation written at node
v2.

Thus

JN

the output vo is equal to the RC times the

negative instantaneous rate of change of the
input voltage vin with time. A cosine wave input

Fig.2.11 Circuit Diagram of Differentiator

produces sine output. fig.2.10 also shows the
output waveform for different input voltages.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

JN

TU

or

As the frequency changes, the gain changes. Also

at higher frequencies the circuit is highly
susceptible at high frequency noise and noise gets
amplified. Both the high frequency noise and
problem can be corrected by adding, few
components. as shown in fig.2.11.

ld

The input signal will be differentiated properly if

the time period T of the input signal is larger than
or equal to Rf C.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

2.7 Integrator:

or

ld

A circuit in which the output voltage waveform is the integral of the input voltage waveform is
called integrator. Fig.2.12, shows an integrator circuit using OPAMP.

Fig.2.12 Circuit Diagram of Integrator

Here, the feedback element is a capacitor. The current drawn by OPAMP is zero and also the V2 is
virtually grounded.

TU

Therefore, i1 = if and v2 = v1 = 0

JN

Integrating both sides with respect to time from 0 to t, we get

The output voltage is directly proportional to the negative integral of the input voltage and
inversely proportional to the time constant RC.
If the input is a sine wave the output will be cosine wave. If the input is a square wave, the
output will be a triangular wave. For accurate integration, the time period of the input signal T must
Downloaded From JNTU World (http://www.alljntuworld.in)

be longer than
www.alljntuworld.in

JNTU World

or equal to RC.

JN

TU

or

ld

Fig.2.13, shows the output of integrator for square and sinusoidal inputs.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

2.8 COMPARATOR:
Voltage comparator circuit.

or

Fig.2.13 Input and Out put wave forms

JN

TU

Voltage comparator is a circuit which compares two voltages and switches the output to either high or low
state depending upon which voltage is higher. A voltage comparator based on opamp is shown here. Fig2.14
shows a voltage comparator in inverting mode and Fig shows a voltage comparator in non inverting mode.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Fig2.14Circuit Diagram of Comparator

2.8.1.Non inverting comparator.

or

2.8.2.Inverting comparator.

ld

In non inverting comparator the reference voltage is applied to the inverting input and the voltage to
be compared is applied to the non inverting input. Whenever the voltage to be compared (Vin) goes
above the reference voltage , the output of the opamp swings to positive saturation (V+) and vice
versa. Actually what happens is that, the difference between Vin and Vref, (Vin Vref) will be a
positive value and is amplified to infinity by the opamp. Since there is no feedback resistor Rf, the
opamp is in open loop mode and so the voltage gain (Av) will be close to infinity. So the output
voltage swings to the maximum possible value ie; V+. Remember the equation Av = 1 + (Rf/R1).
When the Vin goes below Vref, the reverse occurs.

In the case of an inverting comparator, the reference voltage is applied to the non inverting input and
voltage to be compared is applied to the inverting input. Whenever the input voltage (Vin) goes
above the Vref, the output of the opamp swings to negative saturation. Here the difference between
two voltages (Vin-Vref) is inverted and amplified to infinity by the opamp. Remember the equation
Av = -Rf/R1. The equation for voltage gain in the inverting mode is Av = -Rf/R1.Since there is no
feedback resistor, the gain will be close to infinity and the output voltage will be as negative as
possible ie; V-.
2.8.3.Practical voltage comparator circuit.

JN

TU

A practical non inverting comparator based on uA741 opamp is shown below. Here the reference
voltage is set using the voltage divider network comprising of R1 and R2. The equation is Vref =
(V+/ (R1 + R2)) x R2. Substituting the values given in the circuit diagram into this equation gives
Vref = 6V. Whenever Vin goes above 6V, the output swings to ~+12V DC and vice versa. The
circuit is powered from a +/- 12V DC dual supply.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig2.15 Circuit diagram of Practical voltage comparator.

JN

TU

2.8.4.Op-amp voltage comparator

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Figure 2.16 OP-AMP voltage comparator input and out put wave forms(a,b,c)

2.9 SCHMITT TRIGGER:

JN

TU

Below fig shows an inverting comparator with +ve feed back. This ckt converts an irregular shaped
wave forms to a square wave form or pulse.The ckt is known as schitt trigger or squaring circuit.The
i/p voltage being triggers the o/p Vo every time it exceeds certain voltage levels called the upper
threshold voltage Vut and lower threshold voltage Vlt as shown in fig2.17 (b).In fig2.17(a) these
thresold voltages are obtained by using the voltage divider R1,R2,whrere the voltage across R1 is
F/B to +ve i/p.The voltage across R1 is a variable refference,thershold voltage that dependens on the
value and polarity of the out put voltageVo.when Vo=+Vsat,the voltage across R1 is called the uper
thershold voltage,Vut.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

TU

The input voltage Vin must be slightly more positive then Vut in order to cause the out put Vo to
switch from +Vsat to Vsat.as long as Vin less then Vut,Vo is at +Vsat.using the voltage divider
rule,
On the other hand,when Vo=-Vsat, the voltage across R1 is referred to as the lower threshold
voltage,Vlt.Vin must be slightly more negative than Vlt.in order to cause Vo to switch from-Vsat to
+Vsat.in other words,for Vin values greater than Vlt,Vo is at Vsat.Vlt is given by the following
equation;

JN

Thus if the threshold voltages Vut and Vlt are made large than the input noise voltages, the positive
fed back will eliminate the false output transitions.Also the +ve feedback because of its regenerative
action will make Vo switch faster between +Vsat and Vsat.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

(b)

or

ld

www.alljntuworld.in

Fig2.16.(a).inverting comparator as a schmitt trigger (b).input and output wave forms.(c).Vo versus
Vin plot of the hysteresis voltage

TU

2.10 MULTIVIBRATORS:

MONOSTABLE MULTIVIBRATOR:

JN

The monostable multivibrator circuit using op-amp is shown in below figure2.17(a).The diode D1 is
clamping diode connected across C.the diode clamps the capacitor voltage to 0.7volts when the
ouput is at +Vsat.A narrow ve triggering pulse Vt is applied to the non-inverting input terminal
through diode D2.
To understand the operation of the circuit,let us asssume that the ouput Vo is at +Vsat that is
in its stable state.The diode D1 conducts and the voltage across the capacitor C that is Vc gets
clamped to 0.7V.The voltage at the non-inverting input terminal is controlled by potentiometric
divider of R1R2 to Vo that is +Vsat in the stable state.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Figure2.17 Monostable Multivibrator and input-out put waveforms(a,b,c,d)

Now if Vt ,a ve trigger of amplitude Vt is applied to the non-inverting terminal,so that the

effective voltage at this terminal is less than 0.7V than the output of th e op-amp changes its state
from +Vsat to Vsat.The diode is now reverse biased and the capacitor starts charging
exponentionally to Vsat through the resistance R.The time constant of this charging is = RC.

TU

2.11. INTRODUCTION TO VOLTAGE REGULATORS:

An unregulated power supply consists of a transformer (step down), a rectifier and a filter. These
power supplies are not good for some applications where constant voltage is required irrespective of
external disturbances. The main disturbances are:

JN

1. As the load current varies, the output voltage also varies because of its poor regulation.
2. The dc output voltage varies directly with ac input supply. The input voltage may vary over a wide
range thus dc voltage also changes.
3. The dc output voltage varies with the temperature if semiconductor devices are used.

An electronic voltage regulator is essentially a controller used along with unregulated power supply
to stabilize the output dc voltage against three major disturbances
a. Load current (IL)
b. Supply voltage (Vi)
c. Temperature (T)

Fig.2.18, shows the basic block diagram of voltage regulator. where

Vi = unregulated dc voltage.
Vo = regulated dc voltage.
Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Fig.2.18 Block Diagram of voltage regulator

Since the output dc voltage VLo depends on the input unregulated dc voltage Vi, load current IL and
the temperature t, then the change Vo in output voltage of a power supply can be expressed as
follows

TU

Take partial derivative of VO, we get,

or

VO = VO(Vi, IL, T)

SV gives variation in output voltage only due to unregulated dc voltage. RO gives the output voltage
variation only due to load current. ST gives the variation in output voltage only due to temperature.

JN

The smaller the value of the three coefficients, the better the regulations of power supply. The input
voltage variation is either due to input supply fluctuations or presence of ripples due to inadequate
filtering. A voltage regulator is a device designed to maintain the output voltage of power supply
nearly constant. It can be regarded as a closed loop system because it monitors the output voltage
and generates the control signal to increase or decrease the supply voltage as necessary to
compensate for any change in the output voltage. Thus the purpose of voltage regulator is to
eliminate any output voltage variation that might occur because of changes in load, changes in
supply voltage or changes in temperature.
Zener Voltage Regulator:
The regulated power supply may use zener diode as the voltage controlling device as shown in
fig.2.19. The output voltage is determined by the reverse breakdown voltage of the zener diode. This
is nearly constant for a wide range of currents. The load voltage can be maintained constant by
controlling the current through zener.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Fig.2.19Circuit diagram of Zener voltage regulator

Emitter Follower Regulator:

or

The zener diode regulator has limitations of range. The load current range for which regulation is
maintained, is the difference between maximum allowable zener current and minimum current
required for the zener to operate in breakdown region. For example, if zener diode requires a
minimum current of 10 mA and is limited to a maximum of 1A (to prevent excessive dissipation),
the range is 1 - 0.01 = 0.99A. If the load current variation exceeds 0.99A, regulation may be lost.

TU

To obtain better voltage regulation in shunt regulator, the zener diode can be connected to the base
circuit of a power transistor as shown in fig.2.20. This amplifies the zener current range. It is also
known as emitter follower regulation.

Fig.2.20Circuit diagram of Emitter follower voltage regulator

JN

This configuration reduces the current flow in the diode. The power transistor used in this
configuration is known as pass transistor. The purpose of CL is to ensure that the variations in one
of the regulated power supply loads will not be fed to other loads. That is, the capacitor effectively
shorts out high-frequency variations.
Because of the current amplifying property of the transistor, the current in the zenor dioide is small.
Hence there is little voltage drop across the diode resistance, and the zener approximates an ideal
constant voltage source.
Operation of the circuit:

The current through resistor R is the sum of zener current IZ and the transistor base current IB( = IL
/ ).
IL = IZ + IB

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

The output voltage across RL resistance is given by

VO = VZ - VBE
Where VBE 0.7 V
Therefore, VO= constant.

or

ld

The emitter current is same as load current. The current IR is assumed to be constant for a given
supply voltage. Therefore, if IL increases, it needs more base currents, to increase base current Iz
decreases. The difference in this regulator with zener regulator is that in later case the zener current
decreases (increase) by same amount by which the load current increases (decreases). Thus the
current range is less, while in the shunt regulators, if IL increases by IL then IB should increase by
IL / or IZ should decrease by IL / . Therefore the current range control is more for the same
rating zener.

TU

The simplified circuit of the shunt regulator is shown in fig.2.21

JN

Fig.2.21 Circuit diagram of Zener Shunt regulator

In a power supply the power regulation is basically, because of its high internal impedance. In the
circuit discussed, the unregulated supply has resistance RS of the order of 100 ohm. The use of
emitter follower is to reduce the output resistance and it becomes approximately.

RO = ( Rz + hie ) / (1 + hfe)
Where RZ represents the dynamic zener resistance. The voltage stabilization ratio SV is
approximately
SV = Vo / VI = Rz / (Rz + R)
SV can be improved by increasing R. This increases VCE and power dissipated in the transistor.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Other disadvantages of the circuit are.

Series regulator with Current Pre-regulator

ld

No provision for varying the output voltage since it is almost equal to the zener voltage.
Change in VBEand Vz due to temperature variations appear at the output since the transistor is
connected in series with load, it is called series regulator and transistor is allow series pass transistor.

TU

or

The circuit of fig.2.22 is an improved version of series voltage regulator discussed in previous lecture.
Besides Q1 being replaced with a current regulator circuit. The function of D2, R6, R7, and Q3 is to
establish and maintain a constant I1.

Fig.2.22 Circuit diagram of Series voltage regulator

The circuit works this way :- I1 is the collector current of Q3, and hence it is also approximately equal
to IE3. The voltage at the base of Q3 relative to V1 is held at a constant level by D2; current through R6 is
selected to keep D2 in breakdown and to yield the proper temperature coefficient. Should I1 rise, IE3 will
also rise, increasing the voltage across R1. This reduces VEB3, which in turn reduces IE3 and I1. Thus I1 is
regulated and remains fairly constant even if there are changes in the unregulated input.

JN

One disadvantage of this circuit is that a larger input voltage is required to supply the various voltage
drops between Vi and Vo. In this case Vi must supply Vo plus the two VEB drops of Q11 and Q12 (which
takes us to point A), plus the collector-base bias for Q3 (which takes us to the base Q3), plus the Zener
voltage for D2.

Power Supply Using IC Regulator (Three-Terminal Regulator)

Monolithic integrated circuits have greatly simplified the design of a wide variety of power supplies.
Using a single IC regulator and a few external components, we can obtain excellent regulation (on the
order of 0.01%) with good stability and reliability and with overload protection.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

IC regulators are produced by a number of manufacturers. The IC regulator improves upon the
performance of the Zener diode regulator. It does this by incorporating an operational amplifier. In this
section, we present basic design considerations for IC regulators. These techniques are useful in the
design of power supplies for a variety of low power applications. We consider the internal theory of
operation of these and other three-terminal voltage regulators in the current section. These products
vary in the amount of output current. The most common range of output current is 0.75 A to 1.5 A
(depending on whether a heat sink is used).

Fig.2.23 Circuit diagram of Series voltage regulator

The functional block diagram of fig.2.23 illustrates the method of voltage regulation using this series
regulator. The name series regulator is based on the use of a pass transistor (a power transistor) which
develops a variable voltage which is in "series" with the output voltage. The voltage across the pass
transistor is varied in such a manner as to keep the output voltage constant.

TU

A reference voltage, VREF, which is often developed by a Zener diode, is compared with the voltage
divided output, vout. The resulting error voltage is given by

JN

The error voltage v e is amplified through a discrete amplifier or an operational amplifier and used to
change the voltage drop across the pass transistor. This is a feedback system which generates a
variable voltage across the pass transistor in order to force the error voltage to zero. When the error
voltage is zero, we obtain the desired equation by solving equation (Equ-1) for vout .

Thermal shutdown and current-limit circuitry exists between the error amplifier and the pass transistor.
This circuitry protects the regulator in case the temperature becomes too high or an inadvertent short
circuit exists at the output of the regulator.

The maximum power dissipated in this type of series regulator is the power dissipated in the internal
pass transistor, which is approximately (VS max - Vout) IL max. Hence, as the load current
increases, the power dissipated in the internal pass transistor increases. If ILoad exceeds 0.75 A, the

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

IC package should be secured to a heat sink. When this is done, ILoad can increase to about 1.5 A.
We now focus our attention on the 78XX series of regulators. The last two digits of the IC par
number denote the output voltage of the device. Thus, for example, a 7808 IC package produces a
8V regulated output. These packages, although internally complex, are inexpensive and easy to use.

or

ld

There are a number of different voltages that can be obtained from the 78XX series 1C; they are 5,
6, 8, 8.5, 10, 12, 15, 18, and 24 V. In order to design a regulator around one of these ICs, we need
only select a transformer, diodes, and filter. The physical configuration is shown in fig.2.24(a). The
ground lead and the metal tab are connected together. This permits direct attachment to a heat sink
for cooling purposes. A typical circuit application is shown in fig.2.24(c).

(b)

(a)

TU

(c)

Fig.2.24Three terminal IC voltage regulator(a,b,c)

JN

The specification sheet for this IC indicates that there must be a common ground between the input
and output, and the minimum voltage at the IC input must be above the regulated output. In order to
assure this last condition, it is necessary to filter the output from the rectifier. The CF in fig.2.24(b)
performs this filtering when combined with the input resistance to the IC. We use an n:1 step down
transformer, with the secondary winding center-tapped, to drive a full-wave rectifier.
The minimum and maximum input voltages for the 78XX family of regulators are shown in Table2.1.

Type

Min

Max

7805

25

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

25

7808

10.5

25

7885

10.5

25

7810

12.5

28

7812

14.5

30

7815

17.5

7818

21

7824

27

30
33
38

or

Table -2.1

ld

7806

We use Table -2.1 to select the turns ratio, n, for a 78XX regulator. As a design guide, we will take
the average of Vmax and Vmin of the particular IC regulator to calculate n. For example, using a
7805 regulator, we obtain

TU

The center tap provides division by 2 so the peak voltage out of the rectifier is 115 2 / 2n = 16.
Therefore, n = 5. This is a conservative method of selecting the transformer ratio. The filter
capacitor, CF, is chosen to maintain the voltage input range to the regulator as specified in Table
2.1.

JN

The output capacitor, CLoad, aids in isolating the effect of the transients that may appear on the
regulated supply line. CLoad should be a high quality tantalum capacitor with a capacitance of 1.0
F. It should be connected close to the 78XX regulator using short leads in order to improve the
stability performance.This family of regulators can also be used for battery powered systems.
Fig.2.24(c) shows a battery powered application. The value of CF is chosen in the same manner as
for the standard filter. The 79XX series regulator is identical to the 78XX series except that it
provides negative regulated voltages instead of positive.

2.12 FEATURES OF IC 723:

1.Input and out put short circuit protection provided.

2.Positive or negative supply operation

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

3.Good line and load regulation

4.Low temperature drift and high ripple rejection
5.Out put voltage can be varied from 2V to 37V

JN

TU

or

ld

6.Small in size and hence economical

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

UNIT-III
ACTIVE FILTERS and OSCILLATORS
3.1. LOW PASS FILTER:

ld

Anelectricfilterisoftenafrequency-selectivecircuitthatpassesaspecifiedbandoffrequencies
andblocksorattenuatessignalsoffrequenciesoutsidethisband.Filtersmaybeclassifiedina numberof ways:
1. Analog ordigital

3. Audio (AF) or radio frequency (RF)

or

2. Passiveoractive

Analogfiltersaredesignedtoprocessanalogsignals,whiledigitalfiltersprocessanalogsignals
usingdigitaltechniques.Dependingonthetypeofelementsusedintheirconstruction,filters maybe classifiedas
passive or active. Elementsusedinpassivefiltersareresistors,capacitors,andinductors.Activefilters,onthe
otherhand,employ transistorsorop-ampsinadditiontotheresistorsandcapacitors.Thetypeof element used
dictates theoperatingfrequencyrangeof the filter.

TU

Forexample,RCfiltersarecommonlyusedforaudioorlow-frequencyoperation,whereasLC
orcrystalfiltersareemployedatRF orhighfrequencies.EspeciallybecauseoftheirhighQ value (figureof merit),
the crystal providemorestable operation at higher frequencies.

Anactive filteroffers the following advantages overa passivefilter:

JN

1.Gainandfrequencyadjustmentflexibility.Sincetheop-ampiscapableofproviding again,
theinputsignalisnotattenuatedasitisinapassivefilter.Inaddition,theactivefilteriseasierto tune or adjust.
2.Noloadingprob1em.Because of the high inputresistanceand low outputresistance oftheop- amp, the
active filterdoes not cause loading ofthesourceor load.
3.Cost.Typically,activefiltersaremoreeconomicalthanpassivefilters.Thisisbecauseofthe varietyof cheaper opamps and the absenceof inductors.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Themostcommonlyused filters arethese:

1. Low-pass filter
2. High-pass filter
3. Band-pass filter
4. Band-reject filter

JN

TU

or

ld

5. All-pass filter

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 3.1 frequency response of major active filters (a)Low pass (b)High pass (c)Band pass

TU

(d)Band reject (e) All pass

Fig.3 . 1 showsthefrequencyresponsecharacteristicsofthefivetypesoffilters.Theideal responseisshownby

dashedcurves,whilethesolidlinesindicatethepracticalfilterresponse.A low-passfilterhasaconstantgain
from0HztoahighcutofffrequencyfH.Therefore,the bandwidth is also fH.

JN

AtfH thegainisdownby3dB;afterthat (f>fH)itdecreaseswiththeincreaseininput frequency. The

frequencies between 0 HzandfH areknownas thepassbandfrequencies,whereas
therangeoffrequencies,thosebeyondfH thatareattenuatedincludesthestopbandfrequencies.

Fig.3.1(a)showsthefrequencyresponseofthelow-passfilter.Asindicatedbythedashedline,
anidealfilterhasa zerolossinitspassbandandinfinitelossinitsstopband.Unfortunately,ideal filter response is
not practical because linear networks cannot produce the discontinuities.
However,itispossibletoobtainapractical responsethatapproximatestheidealresponseby usingspecial design
techniques, as well as precision component values andhigh-speed op-amps.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Butterworth,Chebyshev,andCauerfiltersaresomeofthemostcommonlyusedpracticalfilters
thatapproximatetheidealresponse.ThekeycharacteristicoftheButterworthfilteristhatithas a flat passbandas
wellasstopband. Forthis reason, itis sometimes calledaflat-flatfilter.

ld

TheChebyshevfilterhasaripplepassbandandflatstopband,i.e.theCauerfilterhasaripple passbandanda
ripplestopband.Generally,theCauerfiltergivesthebeststopbandresponse
amongthethree.Becauseoftheirsimplicityofdesign,thelow-passandhigh-passButterworth filters
arediscussed here.

or

Figure3 -1(b)showsahigh-passfilterwithastopband0<f<fL andapassbandf>fL.fL isthe low cutoff

frequency, andfis the operating frequency. Aband-pass filterhas apassband between twocutoff
frequencies fH and fL,wherefH>fLand two stop-bands: 0<f<fLand f>fH.Thebandwidthofthebandpassfilter,therefore,isequaltofH -fL.Theband-rejectfilter performs exactly oppositetothebandpass;thatis,ithas aband-stop betweentwo cutoff frequenciesfH andfL andtwopassbands:0<f<fL
andf>fH.Theband-rejectisalsocalleda band-stoporband-eliminationfilter.The frequencyresponsesofbandpassandband-reject filtersareshowninFigure3-1(c)and(d),respectively.Inthesefigures,fC iscalledthecenter
frequencysinceit is approximatelyat thecenter ofthe passband orstopband.

TU

Fig.3.1(e)showsthephaseshiftbetweeninputandoutputvoltagesofanall-passfilter.Thisfilter
passesallfrequenciesequallywell;thatis,outputandinputvoltagesequalinamplitudeforall
frequencies,withthephaseshiftbetweenthetwoafunctionoffrequency.Thehighestfrequency
uptowhichtheinput andoutput amplitudesremainequal isdependentontheunitygain bandwidthoftheopamp.(Atthisfrequency, however, thephaseshiftbetweentheinputand outputismaximum.

JN

Therateatwhichthegainofthefilterchangesinthestopbandisdeterminedbytheorderofthe
filter.Forexample,forthefirstorderlow-passfilterthegain-rolls-offattherateof20dB/decade
inthestopband,thatis,forf>fH;ontheotherhand,forthesecond-orderlow-passfiltertherolloffrateis40dB/decadeandsoon.By contrast,forthefirst-orderhigh-passfilterthegain increases at the rate of
20 dB/decade in the stopband, that is, until f=fL;the increase is 40dB/decade for thesecond-order high-pass
filter;

3.1.1 FIRST-ORDER LOW-PASSBUTTER WORTH FILTER

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

JN

TU

or

ld

Fig. 3-2 shows a first-order low-passButterworthfilterthat uses an RCnetwork for filtering. Notethat the opamp is used in thenon-invertingconfiguration; henceitdoes not load down the RCnetwork. ResistorsR1 and
RF determinethegain of the filter.Accordingto thevoltage-divider rule, the voltageat thenoninvertingterminal (acrosscapacitor C)is

Fig.3.2.First order Low Pass Butter Worth Filter (a)circuit (b)Response

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Where Vo/Vin = gain of the filter as a function of frequency

= passaband gain of the filter
f = input frequency of the filter
= upper cut-off frequency of the filter.

ld

fH=

Where is the phase angle in degrees.

or

Thegain magnitude andphase angleequations ofthe low-pass filter can beobtained by convertingEquation
3.1into its equivalent polar form, as follows:

The operation of the low pass filter can be verified from the gain magnitude equation:

1. At very low frequencies that is , f<fH,

2. At f=fH,

AF

TU

3. At f>fH ,

= 0.707 AF

FilterDesign

JN

Alow-pass filtercan bedesignedbyimplementingthe foI1owingsteps:

1. Chooseavalue ofhigh cutoff frequencyfH.

2. Select a value of C less than or equal to 1 F. Mylar or tantalum capacitors are

recommendedforbetterperformance.
3. Calculate thevalue of Rusing R

4.Finally, select values ofR1 and RFdependent on thedesired passband gain AFusing

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Frequency Scaling

or

ld

Onceafilterdesigned;theremaysometimes beaneed to changeits cutofffrequency. The

procedureusedto convert an originalcutofffrequencyfHtoa new cutofffrequencyfHiscalled
frequencyscaling.Frequencyscalingis accomplished as follows. To change ahigh cutoff frequency, multiple
RorC. but notboth, bytheratio of theoriginalcutoff frequencyto thenew cutofffrequency.

3.1.2 SECOND-ORDER LOW-PASSBUTTER WORTH FILTER

A stop-band response having a 40-dB/decade roll-off is obtained with the second order lowpassfilter. A first-order low-pass filter can be converted into a second order type simply by

JN

TU

using anadditional RC network, as shown in Fig.3.3.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 3.3 Second order Low Pass Butter Worth Filter (a)Circuit(b)Frequency Response

TU

Second-order filters are important because higher-order filters can be designed using them. Thegain of the
second-order filter is set by R1 and RF, while the high cutoff frequency fH isdetermined by R2, C2, R3, and C3,
as follows

JN

Furthermore, for asecond-order low-passButterworth response, thevoltagegain magnitude equation is

Where Vo/Vin = gain of the filter as a function of frequency

= passaband gain of the filter

f = input frequency of the filter

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

= upper cut-off frequency of the filter

3.2 HIGH PASS FILTER

TU

or

ld

3.2.1 .FIRST-ORDER HIGH-PASSBUITERWORTH FILTER

Fig3.4 (a)First order High Pass Butter Worth Filter (b)Frequency Response

JN

High-pass filters areoften formed simplybyinterchangingfrequency-determiningresistors and

capacitors in low-pass filters. That is, a first-orderhigh-passfilteris formedfrom a first-order low-pass
typebyinterchanging componentsRand C.

Similarly,asecond-orderhigh-passfilteris obtained from a second-order low-pass filter if R and

Careinterchanged,and so on. Figure3.4 shows afirst-order high-pass Butterworth filter with a low cutoff
frequencyof fL.

Thisis the frequencyatwhich the magnitudeof thegain is0.707 times itspassband value.Obviously,

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

allfrequencies higher thanfLarepassband frequencies,with thehighest requency determined bythe closedloop bandwidth of the op-amp.

Notethat the high-pass filter of Figure3.4(a) and thelow-pass filter of Figure3.4(a) arethe same
circuits, except thatthe frequency-determiningcomponents(R and C) areinterchanged.

Hencethemagnitudeof thevoltagegain is

or

ld

Forthe first-order high-pass filter ofFigure3.4(a), the outputvoltageis

Where

= passaband gain of the filter

TU

f = input frequency of the filter

fL =

= Lower cut-off frequency of the filter

JN

Sincehigh-pass filters are formed from low-pass filters simplybyinterchangingRs andCs, the design
and frequencyscalingprocedures of thelow-pass filters are also applicable to the high- pass filters.

3.2.2 SECOND-ORDER HIGH-PASSBUTTERWORTH FILTER:

Asin the caseof the first-orderfilter, asecond-order high-pass filtercan be formed from a second-order lowpass filter simplybyinterchangingthe frequency-determiningresistorsand capacitors. Figure3.5(a)shows the
second-order high-passfilter.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig3.5(a)Second order High Pass Butter Worth Filter (b)Frequency Response

Thevoltagegain magnitude equation ofthe second-order high-pass filter isas follows:

TU

WhereAF=1.586=passband gain forthe second-orderButterworth response

f=frequencyofthe inputsignal (Hz)

fL=low cutofffrequency(Hz)

JN

Sincesecond-order low-pass and high-pass filtersarethe same circuits except that thepositions of
resistors and capacitorsareinterchanged, thedesign and frequencyscalingprocedures forthe high-passfilter
arethe same as those forthe low-pass filter.

3.3BAND-PASSFILTERS

Aband-pass filter has a passband between two cutoff frequenciesfHand fL suchthat fH>fL.
Anyinputfrequencyoutsidethis passband is attenuated.Basically, therearetwo types of band-pass filters:
(1) Wide band pass, and

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

(2) Narrow band pass.

ld

Unfortunately, thereis no set dividinglinebetween the two. However, wewilldefinea filteras

wideband pass if itsfigureof meritorqualityfactorQ<10.On theother hand, if wewillcallthe
filteranarrowband-passfilter. Thus Q is ameasureof selectivity, meaning the higher thevalue Q, the
moreselectiveis the filteror thenarrower itsbandwidth (BW). Therelationship between Q, the3dBbandwidth, and the centerfrequency fcis given by

Forthe wideband-pass filter the center frequencyfc can bedefinedas wherefH =highcutofffrequency(Hz)

or

fL=low cutofffrequencyof thewideband-pass filter (Hz)

Inanarrowband-pass filter, the output voltage peaksatthecenterfrequency.

3.3.1 Wide-bandpass filter

Awideband-passfiltercanbeformedbysimplycascadinghigh-passandlow-passsectionsand is
generallythe choice for simplicityofdesign andperformance.To obtain 20dB/decade band-pass, first-order
high pass and first order low-pass sectionsare cascaded;fora40-dB/decadeband-passfilter,
second-orderhigh- passandsecond- order low-pass sections are connected in series.

JN

TU

Figure3 . 6 showsthe20-dB/decadewideband-passfilter,whichiscomposedoffirst-order highpassandfirst-orderlow-passfilters.Torealizeaband-passresponse,however,fH mustbe larger than fL.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

Fig 3.6(a)20dB/decade Wide Band Pass Filter (b)Frequency Response

JN

Sincethe band-passgain is 4, thegain of thehigh-pass as wellas low-passsections could be set equal

to 2. That is, input and feedbackresistors must be equalin value, say10 keach. The complete band-pass
filteris shown in Fig 3.6(a).(b)Thevoltagegain magnitudeof theband-pass filter is equal to the product of
thevoltagegain magnitudes of thehigh-pass and low-pass filters.

whereAFT =total passband gain

f= frequencyofthe input signal (Hz)

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

fL=low cutofffrequency(Hz)
fH=highcutofffrequency(Hz)

ld

3.3.2.NarrowBand-PassFilter

Thenarrow band-pass filterusingmultiple feedback is shown in Figure8-13. As shown in this figure,

the filteruses onlyoneop-amp. Comparedto all the filters discussed so far, this filteris unique in the
followingrespects:

TU

2.Theop-amp is used inthe invertingmode.

or

1.It has twofeedback paths, hencethe namemultiple-feedback filter.

JN

Fig 3.7 Multiple Feedback Narrow Band Pass Filter

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

or

Fig 3.8.(b). Frequency Response

Generally, the narrow band-pass filter is designedforspecificvalues ofcenter frequencyfcand Q

orfcand bandwidth. The circuitcomponentsaredeterminedfrom the followingrelationships. To
simplifythedesign calculations, chooseC1 =C2 =C.

TU

WhereAFisthegainat fc, given by

Thegain AF,however, must satisfythe condition

JN

Another advantageof themultiple feedbackfilterof Figure8-13 is that its centerfrequencyfc can

bechanged toanewfrequencyfcwithoutchangingthegain or bandwidth. This is accomplished
simplybychanging R2 to R2 sothat

3.4 BAND-REJECT FILTERS

Theband-rejectfilter is also called aband-stoporband-eliminationfilter.In this filter, frequencies
areattenuated in thestopband while they arepassed outsidethis band, as shown in

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Figure3.1(d).
Aswith band-pass filters,the band-reject filterscan also be classifiedas (1)wideband-reject or
(2)narrowband-reject. The narrow band-reject filteris commonlycalled thenotch filter. Because of its
higherQ (>10), thebandwidth of thenarrow band-reject filteris much smaller than that of thewidebandreject filter.

or

ld

3.4.1WideBand-RejectFilter

JN

TU

Fig3.9(a).Wide Band Reject Filter

Fig 3.9(b)Frequency Response

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Figure3.9(a) shows a wide band-reject filterusingalow-pass filter,ahigh-pass filter,

andasummingamplifier. To realizeaband-rejectresponse, thelowcutofffrequencyfLofthe high- pass filter
must be largerthan thehighcutofffrequencyfHofthe low-pass filter.In addition, the passbandgain of both
thehigh-passand low-pass sections must be equal. Thefrequency response ofthewideband-reject filteris
shown in Fig3.9(b).

ld

3.4.2 NarrowBand-RejectFilter

TU

or

Thenarrow band-reject filter, often called thenotch filter, is commonlyused forthe rejection of
asinglefrequencysuch as the 60-Hzpower linefrequencyhum. Themostcommonlyusednotch filteris thetwinT network shown in Fig3.10(a). This is a passive filtercomposed of two T- shaped networks.OneTnetwork is
madeup oftwo resistors and acapacitor, while theother usestwo capacitors andaresistor. The notch-out
frequencyis thefrequencyat which maximum attenuation occurs; it is given by

Fig.3.10(a)Twin-T notch Filter

JN

The active notch filter using opamp is shown in fig 3.10b.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Fig.3.10(b) Active notch filter and its frequency response

ld

3.5 ALL-PASSFILTER

or

Asthenamesuggests,anall-passfilterpassesallfrequencycomponentsoftheinputsignal without
attenuation, whileprovidingpredictablephaseshiftsfordifferent

JN

TU

Fig3.11(a)All Pass Filter

Fig3.11(b)Phase Shift Between Input And Output

frequenciesofthe inputsignal.Whensignalsaretransmittedovertransmissionlines,suchastelephonewires,they
undergochangeinphase.Tocompensateforthesephasechanges,all-passfiltersarerequired. Theallpassfiltersarealsocalleddelayequalizersorphasecorrectors.Figure3.11(a)showsan all-passfilterwhereinRF

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

=R1. TheoutputvoltageVoofthefiltercanbeobtainedbyusingthe superposition theorem:

or

Wherefis the frequencyofthe input signal inhertz.

ld

But -j =1/j and XC =1/2fC. Therefore, substitutingfor XC and simplifying, weget

EquationindicatesthattheamplitudeofVo/Vinisunity;thatis,|Vo|=|Vin|throughouttheuseful
frequencyrange,andthephaseshiftbetweenVoandVinisafunctionofinputfrequencyf.The phase angle
isgiven by

TU

Whereisindegrees,inhertz,Rinohms,andCinfarads.Equationisusedtofindthephase
angleiff,R,andCareknown.Figure3 .12 (b)showsaphaseshiftof90betweentheinput
VinandoutputVo.Thatis,VolagsVinby90.ForfixedvaluesofRandC,thephaseangle changesfrom 0to
180asthe frequencyf is variedfrom 0to.InFigure3.12(a),if thepositions
ofRandCareinterchanged,thephaseshiftbetweeninputandoutputbecomespositive.Thatis, outputVo leads
inputVin.

3.6 OSCILLATOR TYPES AND PRINCIPLE OF OPERATION

JN

Theuse of op-amps as oscillators capableofgeneratingavarietyof output waveforms. Basically,

thefunctionof an oscillatoristogenerate alternatingcurrentorvoltagewaveforms.More
precisely,anoscillatorisacircuitthatgeneratesarepetitivewaveformoffixedamplitudeand
frequencywithoutanyexternalinputsignal.Oscillatorsareusedinradio,television,computers,
andcommunications.Althoughtherearedifferenttypesofoscillators,theyallworkonthesame basic principle.

OscillatorPrinciple

Anoscillatoris a typeoffeedback amplifierin which part ofthe output is fed back to theinput via a
feedbackcircuit.Ifthe signal fed back is ofproper magnitudeand phase, the circuit produces

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

alternatingcurrents or voltages. To visualizethe requirements ofan oscillator, consider the block diagram
ofFigure3.12.

JN

TU

or

ld

However, herethe input voltageis zero(Vin=0).Also, the feedback is positive because most
oscillators usepositive feedback.Finally, the closed-loop gain ofthe amplifier is denoted byAv ratherthan AF.

Fig3.12.Oscillator Block Diagram

Usingtheserelationships, the followingequation is obtained:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

However, Vin =0 andVo0 implies thatAv=1

or

ld

Expressed in polarform,

Equation gives the tworequirements foroscillation:

(1)Themagnitudeof theloop gainAvBmust be at least1,and

(2)Thetotal phaseshift oftheloop gain AvBmustbe equal to 0or360.

TU

Ifthe amplifier uses a phaseshift of180, the feedback circuitmustprovide an additional phase shift
of 180 so that the total phaseshift aroundtheloopis 360.Thewaveforms shown in
Figure3.13aresinusoidaland areused to illustrate the circuitsaction.

JN

Thetypeofwaveform generated byan oscillator depends on thecomponents in the circuitand hencemaybe

sinusoidal, square, or triangular;In addition, the frequencyof oscillation is determined bythe components
in the feedback circuit.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

3.6.1 RC-PHASE SHIFT OSCILLATOR

or

ld

Figure3.13showsaphaseshiftoscillator,whichconsistsofanop-ampastheamplifyingstage
andthreeRCcascadednetworksasthefeedbackcircuit.Thefeedbackcircuitprovidesfeedback
voltagefromtheoutputbacktotheinputoftheamplifier.Theop-ampisusedintheinverting mode;therefore,any
signalthatappearsattheinvertingterminalisshiftedby180attheoutput.

TU

Fig 3.13 RC phase shift Oscillator

JN

Anadditional180phaseshiftrequiredforoscillationisprovidedby thecascadedRCnetworks.
Thusthetotalphaseshiftaroundtheloopis360(or0).Atsomespecificfrequencywhenthe phase shift of the
cascaded RC networks is exactly 180and the gain of the amplifier is sufficiently large, the circuit will
oscillate at that frequency. This frequency is called the frequencyof oscillationfo and is given by

Atthis frequency, thegainAvmustbe at least29.That is,

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

3.6.2 WIEN BRIDGE OSCILLATOR

ld

Because of its simplicityand stability, oneof themostcommonlyused audio-frequency oscillators is the Wien
bridge.Figure3.14 shows the Wien bridgeoscillatorin which theWien bridgecircuitis connected between
theamplifierinput terminals and the outputterminal. The bridgehas a series RCnetworkin one arm
andaparallelRCnetworkin theadjoiningarm.In the remainingtwoarmsofthebridge, resistorsR1 and RF,are
connected.

JN

TU

or

Thephaseangle criterionforoscillation is that the total phaseshift around the

circuitmustbe00.Thiscondition occurs onlywhen the bridgeis balanced, that is, atresonance. The
frequencyof oscillation f0 is exactlythe resonant frequencyof thebalanced Wien bridgeand is given by

Fig3.14Wien Bridge Oscillator

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Assumingthat the resistors are equal in value,andcapacitors areequal in value in the reactive legof
theWien bridge. At this frequencythegain required for sustained oscillation is given by

JN

TU

or

3.6.3 QUADRATURE OSCILLATOR

Fig.3.15Quadrature Phase Shift Oscillator

Asitsnameimplies,thequadratureoscillatorgeneratestwosignals(sineandcosine)thatarein
quadrature,thatis,outofphaseby900.Althoughtheactuallocationofthesineandcosineis
arbitrary,inthequadratureoscillatorofFigure3 . 15 theoutputofA1islabeledasineandthe outputofA2isacosine.
Thisoscillatorrequiresadualop-ampandthreeRCcombinations.The firstop-ampA1isoperating
inthenon-invertingmodeandappearsasanon-inverting integrator. Thesecondop-ampA2isworking

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

asapureintegrator.Furthermore,A2isfollowed byavoltage
dividerconsistingofR3andC3.Thedividernetworkformsafeedbackcircuit,whereasA1and A2 form the
amplifierstage.

or

ld

Thetotalphaseshiftof360aroundthelooprequiredforoscillationisobtainedinthefollowing
way.Theop-amp A2isapureintegratorandinverter.Henceitcontributes-270or(900)of
phaseshift.Theremaining-90(or 2700)ofphaseshiftneededareobtainedatthevoltage dividerR3C3andtheopampA1.Thetotalphaseshiftof3600,however,isobtainedatonly one frequencyf0,called thefrequencyof
oscillation.This frequencyisgiven by

WhereR1C1 =R2C2=R3C3=RC. At this frequency,

Thisis the second condition foroscillation. Thus,to design aquadratureoscillator foradesired

frequencyf0,chooseavalue ofC;then, from Equation, calculate thevalue of R. To simplifydesign calculations,
chooseC1 =C2 =C3and R1 =R2 =R3.Inaddition,R1 maybeapotentiometerin order toeliminate anypossible
distortion in theoutputwaveforms.

TU

3.7 WAVEFORM GENERATORS.

Incontrasttosinewaveoscillators,squarewaveoutputsaregeneratedwhentheop-ampis
forcedtooperateinthesaturatedregion.Thatis,theoutputoftheop-ampisforcedtoswing repetitively
betweenpositivesaturation+Vsat(+VCC)andnegativesaturationVsat(+VEE), resultingin thesquarewaveoutput.

JN

3.7.1 SQUARE WAVE GENERATOR.

OnesuchcircuitisshowninFig3 . 16 (a).Thissquarewavegeneratorisalsocalledafreerunningorastablemultivibrator.Theoutputoftheop-ampinthiscircuitwillbeinpositiveor
negativesaturation,depending onwhetherthedifferentialvoltagevid isnegativeorpositive, respectively.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig.3.16 (a).Square Wave Generator (b) Wave Forms of Output Voltage V0 and Capacitor C

TU

Assumethat thevoltageacross capacitorCis zerovolts at the instantthe dcsupplyoltages +VCC and-VEE

areapplied.Thismeansthatthevoltageattheinvertingterminaliszero initially.Atthe
sameinstant,however,thevoltageV1 atthenon-invertingterminalisavery smallfinitevaluethat is
afunctionoftheoutputoffsetvoltageVOOTandthevaluesofR1andR2
resistors.ThusthedifferentialinputvoltageVid isequaltothevoltageV1 atthenon-inverting terminal. Although
verysmall, voltageV1 willstart to drivethe op-amp into saturation.

JN

Forexample,supposethattheoutputoffsetvoltageVOOTispositiveandthat,therefore,voltage V1
isalsopositive.SinceinitiallythecapacitorCactsasashortcircuit,thegainoftheop-ampis
verylarge(A);henceV1drivestheoutputoftheop-amptoitspositivesaturation+Vsat.With
theoutputvoltageoftheop-ampat+Vsat,thecapacitorCstartschargingtoward+Vsat through
resistorR.However,assoonasthevoltageV2acrosscapacitorCisslightlymorepositivethan
V1,theoutputoftheop-ampisforcedtoswitchtoanegativesaturation,-Vsat.Withtheopampsoutputvoltageatnegativesaturation,-Vsat,thevoltagev1acrossR1is alsonegative, since

ThusthenetdifferentialvoltageVid=V1-V2isnegative,whichholdstheoutputoftheop-amp
innegativesaturation.TheoutputremainsinnegativesaturationuntilthecapacitorCdischarges and then
recharges to a negativevoltageslightlyhigherthan-V1.Now, assoon as the capacitors
voltageV2becomesmorenegativethanV1,thenetdifferentialvoltageVidbecomespositive
andhencedrivestheoutputoftheop-ampbacktoitspositivesaturation+Vsat.Thiscompletes onecycle. With
outputat+Vsat, voltage V1at thenon-invertinginputis

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

ld

Thetime period T oftheoutputwaveform isgiven by

or

Above equation indicatesthatthefrequencyoftheoutputf0 isnotonlyafunctionoftheRCtime

constantbutalsooftherelationshipbetweenR1andR2.Forexample,if R2=1.16R1,Equation becomes

3.7.2TRIANGULARWAVEGENERATOR

TU

Recallthattheoutputwaveformoftheintegratoristriangularifitsinputisasquarewave.This
meansthatatriangularwavegeneratorcanbeformedbysimplyconnectinganintegratortothe
squarewavegenerator.TheresultantcircuitisshowninFigure3 . 17 (a).Thiscircuitrequiresa dual op-amp, two
capacitors, and at least five resistors.

Thefrequenciesofthesquarewaveandtriangularwavearethesame.ForfixedR1,R2,andC
values,thefrequencyofthesquarewaveaswellasthetriangularwavedependsontheresistance R.

JN

AsRisincreasedordecreased,thefrequencyofthetriangularwavewilldecreaseorincrease,
respectively.Althoughthe amplitudeofthe square waveis constant(Vsat);the amplitudeofthe triangular
wave decreases with an increase in its frequency, and vice versa. The input of integrator A2 is a square
wave, while its output is a triangularwave.

However,fortheoutputofA2tobeatriangularwaverequiresthat5R3C2>T/2,whereTisthe period ofthe

squarewaveinput.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

Fig.3.17 (a)Triangular Wave Generator (b)Its Output Wave Form

JN

R3C2shouldbeequaltoT.Toobtainastabletriangularwave,itmayalsobenecessary toshunt
thecapacitorC2withresistanceR4=10R3andconnectanoffsetvoltage-compensatingnetwork at thenoninvertingterminalofA2.

Anothertriangularwavegenerator,whichrequiresfewercomponents,isshowninFig3 . 1 8
(a).ThegeneratorconsistsofacomparatorA1,andanintegratorA2.ThecomparatorA1comparesthevoltageatpoi
ntPcontinuouslywiththeinvertinginputthatisat0V.Whenthe
voltageatPgoesslightlybeloworabove0V.theoutputofA1isatthenegativeorpositive saturation level,
respectively.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

Fig 3.18 Triangular Wave Generator(a)Circuit(b)Input and Output Waveform

JN

Toillustratethecircuitsoperation,letussettheoutputofA,atpositivesaturation+V(
+Vc). This+VisaninputoftheintegratorA2.TheoutputofA2,therefore,willbeanegative-going
ramp.Thusoneendofthevoltage-dividerR2R3isthepositivesaturationvoltage+VofA,
andtheotheristhenegative-goingrampofA2.Whenthenegative-goingrampattainsacertain value VRamp,
point P is slightly below 0 V; hence the output of A1 will switch from positive saturation to negative
saturation.This means that the
outputofA2willnowstopgoingnegativelyandwillbegintogopositively.TheoutputofA2
willcontinuetoincreaseuntilitreaches+Atthistimethe point Pisslightlyabove0V;
therefore,theoutputofA,isswitchedbacktothepositivesaturationlevel+V.Thesequence then repeats. The out
put waveform is as shown in Figure3.18(b).

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Thefrequenciesofthesquarewaveandthetriangularwavearethesame.Theamplitudeofthe
squarewaveisa functionofthedcsupplyvoltages.However,adesiredamplitudecanbe obtained by using
appropriate zeners at the output of
A1.

or

ld

Theamplitudeandthefrequencyofthetriangularwavecanbedeterminedasfollows:From
Figure3.18(b),whentheoutputofthecomparatorA1is+V,,theoutputoftheintegratorA2 steadily
decreasesuntilitreachesVrn,.AtthistimetheoutputofA1switchesfrom+Vto
V.Justbeforethisswitchingoccurs,thevoltageatpointP(+input)is0V.Thismeansthatthe VRamp
mustbedeveloped across R2, and +Vsatmustbedeveloped acrossR3. That is,

Similarly,+Vj,,theoutputvoltageofA2atwhichtheoutputofA1switchesfromVto+V,,is given by

TU

The peak-to-peak (pp) output amplitude of the triangular waveis

Above equation indicates that the amplitudeof thetriangular wave decreases with an increase in R3.

JN

Thetime it takes fortheoutputwaveform to swingfrom to + (orfrom +Vmp to VRamp) isequal

to half thetime period T/2.This time can becalculatedfrom the integrator output equation.

Thefrequencyof oscillation then is

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

ld

www.alljntuworld.in

3.7.3 SAWTOOTH WAVEGENERATOR

or

Thedifferencebetween thetriangularandsawtoothwaveformsisthatthe risetimeofthe

triangularwaveisalwaysequaltoitsfalltime.Thatis,thesameamountoftimeisrequiredfor
thetriangularwavetoswingfrom-Vrampto+Vrampasfrom+Vrampto-Vramp.Ontheother
hand,thesawtoothwaveformhasunequalriseandfalltimes.Thatis,itmay risepositivelymany times fasterthan
it falls negatively, or viceversa.

Thetriangularwavegenerator ofFigure3.19(a) can be converted intoasawtooth wavegenerator

byinjectingavariabledcvoltageintothenon-invertingterminaloftheintegratorA2.Thiscan be accomplished by
using the potentiometer and connecting it to the +VCC and-VEE as shown in Figure 3.19(a).

JN

TU

Depending ontheR4setting,a certaindclevelisinsertedintheoutputofA2.Now,supposethat

theoutputofA1isasquarewaveandthepotentiometerR4isadjustedforacertaindclevel.
ThismeansthattheoutputofA2 willbeatriangularwave,ridingonsomedclevelthatisa
functionoftheR4setting.Thedutycycleofthesquarewavewillbedeterminedbythepolarity
andamplitudeofthisdclevel.Aduty cyclelessthan50%willthencausetheoutputofA2tobe asawtooth.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

TU

Fig 3.19 Sawtooth Wave generator (a)Circuit(b)Output Waveform

JN

WiththewiperatthecenterofR4,theoutputofA2isatriangularwave.
ForanyotherpositionofR4wiper,theoutputisasawtoothwaveform.SpecificallyastheR4 wiperismovedtoward
V,the risetimeofthesawtoothwavebecomeslongerthanthefall
time.Ontheotherhand,asthewiperismovedtoward+Vcc,thefall
timebecomeslongerthantherisetime.Also,thefrequencyofthesawtoothwavedecreasesas R4is adjusted
toward + V or VEE. However, the amplitude of the sawtooth wave is independent of theR4setting.

3.7.4 VOLTAGE CONTROLLED OSCILLATOR:

In all the preceding oscillators the frequency is determined by the RC time constant.However there
are applications,such as frequency modulation,tone generators and frequency keying,where the frequency
needs to be controlled by means of an input voltage called controlled voltage.This function is achieved in
the voltage controlled oscillator (VCO) also called a voltage to frequency converter.
A typical example is the signetics NERSE 566 VCO,which provides simultaneous square wave and

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

UNIT-IV

ld

triangular wave outputs as a function of input voltage.Figure(b) is a block diagram of 566,the frequency of
oscillation is determined by an external resistor R1 and capacitor C1 and the voltage Vc applied to the
control terminal 5.The triangular wave is generated by alternately charging the external capacitor C1 by
one current source and then linearly discharging it by another.The discharge levels are determined by
smitt trigger action. The smitt trigger also provides the squar wave output.Both the output wave forms are
buffered so that the output impedance of each is 50ohms.The tipical amplitude of the triangular wave is
2.4 volts peak to peak and that of the squar wave is 5.4 volts peak to peak.-

4.1 INTRODUCTION TO 555 TIMER

or

TIMERS AND PHASE LOCKED LOOPS

One of the most versatile linear integrated circuits is the 555 timer. A sample of these applications
includes mono-stable and astable multivibrators, dc-dc converters, digital logic probes, waveform
generators, analog frequency meters and tachometers, temperature measurement and control, infrared
transmitters, burglar and toxic gas alarms, voltage regulators, electric eyes, and many others.

TU

The 555 is a monolithic timing circuit that can produce accurate and highly stable time delays or
oscillation. The timer basically operates in one of the two modes: either as monostable (one-shot)
multivibrator or as an astable (free running) multivibrator.The device is available as an 8-pin metal can, an
8-pin mini DIP, or a 14-pin DIP.

JN

The SE555 is designed for the operating temperature range from -55Cto + 125C, while the NE555
operates over a temperature range of 0 to +70C. The important features of the 555 timer are these: it
operates on +5 to + 18 V supply voltage in both free-running (astable) and one- shot (monostable) modes; it
has an adjustable duty cycle; timing is from microseconds hrough hours; it has a high current output; it can
source or sink 200 mA; the output can drive TTL and has a temperature stability of 50 parts per million
(ppm) per degree Celsius change in temperature, or equivalently 0.005%/C.
Like general-purpose op-amps, the 555 timer is reliable, easy to us, and low cost.

Pin 1: Ground. All voltages are measured with respect to this terminal.

Pin 2: Trigger. The output of the timer depends on the amplitude of the external trigger pulse applied to this
pin. The output is low if the voltage at this pin is greater than 2/3 VCC. However,when a negative-going pulse
of amplitude larger than 1/3 VCC is applied to this pin, the comparator 2 output goes low, which in turn
switches the output of the timer high [see Figure 4-

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

1(b)]. The output remains high as long as the trigger terminal is held at a low voltage.
Pin 3: Output. There are two ways a load can be connected to the output terminal: either between pin 3
and ground (pin 1) or between pin 3 and supply voltage + VCC (pin 8) . When the output is low, the load
current flows through the load connected between pin 3 and + VCC into the output terminal and is called the
sink current.

ld

However, the current through the grounded load is zero when the output is low. For this reason, the
load connected between pin 3 and + VCC is called the normally on load and that connected between pin 3
and ground is called the normally off load.

TU

or

On the other hand, when the output is high, the current through the load connected between pin
3and + VCC (normally on load) is zero. However, the output terminal supplies current to the normally off
load. This current is called the source current. The maximum value of sink or source current is 200 mA.

JN

Fig 4-1 Pin diagram of 555Timer

Pin 4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When the reset
function is not in use, the reset terminal should be connected to + VCC to avoid any possibility of false
triggering.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 4-1(a) Block Diagram

Pin 5: Control voltage. An external voltage applied to this terminal changes the threshold as well

TU

as the trigger voltage . In other words, by imposing a voltage on this pin or by connecting a pot between this
pin and ground, the pulse width of the output waveform can be varied. When not used, the control pin
should be bypassed to ground with a 0.01-F capacitor to prevent any noise problems.

Pin 6: Threshold. This is the non-inverting input terminal of comparator 1, which monitors the voltage
across the external capacitor . When the voltage at this pin is threshold voltage 2/3 V, the output of
comparator 1 goes high, which in turn switches the output of the timer low.

JN

Pin 7: Discharge. This pin is connected internally to the collector of transistor Q1, as shown in Figure 4-1(b).
When the output is high, Q1 is off and acts as an open circuit to the external capacitor C connected across it.
On the other hand, when the output is low, Q1 is saturated and acts as a short circuit, shorting out the
external capacitor C to ground.

Pin 8: + VCC. The supply voltage of +5 V to +18 is applied to this pin with respect to ground (pin 1).

4.2. FUNCTIONAL BLOCK DIAGRAM OF 555 TIMER

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

JN

Fig 4-1(b) Block diagram of timer

4.3 THE 555 AS A MONOSTABLE MULTIVIBRATOR

A monostable multivibrator, often called a one-shot multivibrator, is a pulse- generating circuit in

which the duration of the pulse is determined by the RC network connected externally to the 555 timer.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

In a stable or standby state the output of the circuit is approximately zero or at logic-low level.
When an external trigger pulse is applied, the output is forced to go high ( VCC). The time the output
remains high is determined by the external RC network connected to the timer. At the end of the timing
interval, the output automatically reverts back to its logic-low stable state. The output stays low until the
trigger pulse is again applied. Then the cycle repeats.

or

ld

The monostable circuit has only one stable state (output low), hence the name mono-stable.
Normally, the output of the mono- stable multivibrator is low. Fig 4.2 (a) shows the 555 configured for
monostable operation. To better explain the circuits operation, the internal block diagram is included in Fig
4-2(b).

TU

Figure 4-2(a) IC555 as monostable multivibrator

Mono-stable operation: According to Fig 4-2(b), initially when the output is low, that is, the circuit is in a
stable state, transistor Q is on and capacitor C is shorted out to ground. However, upon application of a
negative trigger pulse to pin 2, transistor Q is turned off, which releases the short circuit across the external
capacitor C and drives the output high. The capacitorC now starts charging up toward Vcc through RA.

JN

However, when the voltage across the capacitor equals 2/3 Va., comparator I s output switches
from low to high, which in turn drives the output to its low state via the output of the flip-flop. At the same
time, the output of the flip-flop turns transistor Q on, and hence capacitor C rapidly discharges through the
transistor.
The output of the rnonostable remains low until a trigger pulse is again applied. Then the cycle
repeats. Figure 4-2(c) shows the trigger input, output voltage, and capacitor voltage waveforms. As
shownhere, the pulse width of the trigger input must be smaller than the expected pulse width of the
output waveform. Also, the trigger pulse must be a negative-going input signal with amplitude larger than
1/3 the time during which the output remains high is given by where

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

JN

TU

or

ld

www.alljntuworld.in

Fig.4-2 (b)555 connected as a Monostable Multivibrator (c)input and output waveforms

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

where RA is in ohms and C is in farads. Figure 4-2(c) shows a graph of the various combinations of RA
and C necessary to produce desired time delays. Note that this graph can only be used as a guideline and
gives only the approximate value of RA and C for a given time delay. Once triggered, the circuits output will
remain in the high state until the set time 1, elapses. The output will not change its state even if an input
trigger is applied again during this time interval T. However, the circuit can be reset during the timing cycle
by applying a negative pulse to the reset terminal. The output will then remain in the low state until a
trigger is again applied.

Often in practice a decoupling capacitor (10 F) is used between + (pin 8) and ground (pin 1) to
eliminate unwanted voltage spikes in the output waveform. Sometimes, to prevent any possibility of
mistriggering the monostable multivibrator on positive pulse edges, a wave shapingcircuit consisting of R,
C2, and diode D is connected between the trigger input pin 2 and pin 8, as shown in Figure 4-3. The values of
R and C2 should be selected so that the time constant RC2

JN

TU

is smaller than the output pulse width.

Fig.4-3 Monostable Multivibrator with wave shaping network to prevent +ve pulse edge triggering

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

4.3.1 Monostable Multivibrator Applications

ld

(a) Frequency divider: The monostable multivibrator of Figure 4-2(a) can be used as a frequency divider by
adjusting the length of the timing cycle tp, with respect to the tine period T of the trigger input signal
applied to pin 2. To use monostable multivibrator as a divide-by-2 circuit, the timing interval tp must be
slightly larger than the time period T of the trigger input signal, as shown in Figure 4-4. By the same concept,
to use the monostable multivibrator as a divide-by-3 circuit, tp must be slightly larger than twice the period
of the input trigger signal, and

TU

or

so on. The frequency-divider application is possible because the monostable multivibrator cannot
betriggered during the timing cycle.

Fig 4-4 input and output waveforms of a monostable multi vibrator as a divide-by-2 network

JN

(b) Pulse stretcher: This application makes use of the fact that the output pulse width (timing interval) of
the rnonostable multivibrator is of longer duration than the negative pulse width of the input trigger. As
such, the output pulse width of the monostable multivibrator can be viewed as a stretched version of the
narrow input pulse, hence the name pulse stretcher. Often, narrow-pulse- width signals are not suitable for
driving an LED display, mainly because of their very narrow pulse widths. In other words, the LED may be
flashing but is not visible to the eye because its on time is infinitesimally small compared to its off time. The
555 pulse stretcher can be used to remedy this problem

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 4-5 Monostable multi vibrator as aPulse stretcher

Figure 4-5 shows a basic rnonostable used as a pulse stretcher with an LED indicator at the output.
The LED will be on during the timing interval tp = 1.1RAC, which can be varied by changing the value of RA
and/or C.

TU

4.4 THE 555 AS AN ASTABLE MULTIVIBRATOR

JN

The 555 as an Astable Multivibrator, often called a free-running multivibrator, is a rectangularwave-generating circuit. Unlike the monostable multivibrator, this circuit does not require an external
trigger to change the state of the output, hence the name freerunning. However, the time during which the
output is either high or low is determined by the two resistors and a capacitor, which are externally
connected to the 555 timer. Fig 4-6(a) shows the 555 timer connected as an astable multivibrator. Initially,
when the output is high, capacitor C starts charging toward V through RA and R8. However as soon as
voltage across the capacitor equals 2/3 Vcc, comparator I triggers the flip flop, and the output switches low
[see Fig 4-6(b)]. Now capacitor C starts discharging through R8 and transistor Q. When the voltage across C
equals 1/3 comparator 2s output triggers the flip-flop, and the output goes high. Then the cycle repeats.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

TU

Fig 4-6 The 555 as a Astable Multivibrator (a)Circuit(b)Voltage across Capacitor and O/P waveforms.

JN

The output voltage and capacitor voltage waveforms are shown in Figure 4-6(b). As shown in this
figure, the capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 V, respectively. The
time during which the capacitor charges from 1/3 V to 2/3 V. is equal to the time the output is high and is
given by

where RA and R3 are in ohms and C is in farads. Similarly, the time during which the capacitor discharges
from 2/3 V to 1/3 V is equal to the time the output is low and is given by

where RB is in ohms and C is in farads. Thus the total period of the output waveform is

This, in turn, gives the frequency of oscillation as

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

4.4.1 Astable Multivibrator Applications:

or

ld

Above equation indicates that the frequency fo is independent of the supply voltage V. Often the
term duty cycle is used in conjunction with the astable multivibrator . The duty cycle is the ratio of the time
t during which the output is high to the total time period T. It is generally expressed as a percentage. In
equation form,

JN

TU

Square-wave oscillator: Without reducing RA = 0 , the astable multivibrator can be used to produce
a square wave output simply by connecting diode D across resistor RB, as shown in Figure 4-7. The capacitor
C charges through RA and diode D to approximately 2/3 Vcc and discharges through RB and terminal 7 until
the capacitor voltage equals approximately 1/3 Vcc;

Fig 4-7 Astable Multivibrator as a Square wave generator

then the cycle repeats. To obtain a square wave output (50% duty cycle), RA must be a combination of a
fixed resistor and potentiometer so that the potentiorneter can be adjusted for the exact square wave.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Free-running ramp generator: The asab1e multivibrator can be used as a free-running ramp
generator when resistors RA and R3 are replaced by a current mirror. Figure 4-8(a) shows an astable
multivibrator configured to perform this function. The current mirror starts charging capacitor C toward Vcc
at a constant rate.

ld

Free-running ramp generator: The asab1e multivibrator can be used as a free-running ramp
generator when resistors RA and R3 are replaced by a current mirror. Figure 4-8(a) shows an astable
multivibrator configured to perform this function. The current mirror starts charging capacitor C toward Vcc
at a constant rate.

or

When voltage across C equals 2/3 Vcc, comparator 1 turns transistor Q on, and C rapidly discharges
through transistor Q. However, when the discharge voltage across C is approximately equal to 1/3 Vcc,
comparator 2 switches transistor Q off, and then capacitor C starts charging up again. Thus the charge
discharge cycle keeps repeating. The discharging time of the capacitor is relatively negligible compared to its
charging time; hence, for all practical purposes, the time period of the ramp waveform is equal to the
charging time and is approximately given by

JN

TU

Where I = (Vcc VBE)/R = constant current in amperes and C is in farads. Therefore, the
freerunningfrequency of the ramp generator is

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 4-8(a)Free Running ramp generator (b)Output waveform.

TU

4.5.SCHMITT TRIGGER

JN

The below fig 4.9 shows the use of 555 timer as a Schmitt trigger:

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 4.9 Timer as Schmitt trigger

The input is given to the pin 2 and pin 6 which are tied together.Pins 4 and 8 are connected to supply
voltage +Vcc.The common point of two pins 2 and 6 are externally biased at Vcc/2 through the resistance
network R1 and R2.Generally R1=R2 to the gate biasing of Vcc/2.The upper comparator will trip at 2/3Vccwhile
lower comparator at 1/3Vcc.The bias provided by R1 and R2 is centered within these two thresholds.

TU

Thus when sine wave of sufficient amplitude,greater thanVcc/6 is applied to the circuit as input,it
causes the internal flip flop to alternately set and reset.Due to this,the circuit produces the square wave at
the output.

4.6 PHASE-LOCKED LOOPS

JN

4.6.1 Introduction

The phase-locked loop principle has been used in applications such as FM (frequency modulation) stereo
decoders, motor speed controls, tracking filters, frequency synthesized transmitters and receivers, FM
demodulators, frequency shift keying (FSK) decoders, and a generation of local oscillator frequencies in TV
and in FM tuners.

Today the phase-locked loop is even available as a single package, typical examples of which include
the Signetics SE/NE 560 series (the 560, 561, 562, 564, 565, and 567). However, for more economical
operation, discrete ICs can be used to construct a phase-locked loop.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

4.6.2 Bloch Schematic and Operating Principle

or

ld

Figure 4-10 shows the phase-locked loop (PLL) in its basic form. As illustrated in this figure, the
phase-locked loop consists of (1) a phase detector, (2) a low-pass filter, and, (3) a voltage controlled
oscillator.

Fig 4-10 Block Diagram of Phase Locked Loop

TU

The phase detectors or comparator compares the input frequency fIN with the feedback frequency
fOUT.. The output voltage of the phase detector is a dc voltage and therefore is often referred to as the error
voltage. The output of the phase is then applied to the low-pass filter, which removes the high-frequency
noise and produces a dc level.

JN

This dc level, in turn, is the input to the voltage-controlled oscillator (VCO). The filter also helps in
establishing the dynamic characteristics of the PLL circuit. The output frequency of the VCO is directly
proportional to the input dc level. The VCO frequency is compared with the input frequencies and adjusted
until it is equal to the input frequencies. In short, the phase-locked loop goes through three states: freerunning, capture, and phase lock.
Before the input is applied, the phase-locked loop is in the free-running state. Once the input
frequency is applied, the VCO frequency starts to change and the phase-locked loop is said to be in the
capture mode. The VCO frequency continues to change until it equals the input frequency, and the phaselocked loop is then in the phase-locked state. When phase locked, the loop tracks any change in the input
frequency through its repetitive action.

Before studying the specialized phase-locked-loop IC, we shall consider the discrete phaselocked

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

loop, which may be assembled by combining a phase detector, a low-pass filter, and a voltage-controlled
oscillator.

(a) Phase detector:

or

ld

The phase detector compares the input frequency and the VCO frequency and generates a dc
voltage that is proportional to the phase difference between the two frequencies. Depending on the analog
or digital phase detector used, the PLL is either called an analog or digital type, respectively. Even though
most of the monolithic PLL integrated circuits use analog phase detectors, the majority of discrete phase
detectors in use are of the digital type mainly because of its simplicity.

A double-balanced mixer is a classic example of an analog phase detector. On the other

hand,examples of digital phase detectors are these:

1. Exclusive-OR phase detector

2. Edge-triggered phase detector

3. Monolithic phase detector (such as type 4044)

JN

TU

The following fig 4.11 shows Exclusive-OR phase detector:

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

TU

or

ld

www.alljntuworld.in

JN

Fig 4-11(a) Exclusive-OR phase detector: connection and logic diagram. (b) Input and output waveforms. (c)
Average output voltage versus phase difference between fIN and fOUT curve.

(b) Low-pass filter.

The second block shown in the PLL block diagram of Figure 4-10 is a low-pass filter. The function of
the low-pass filter is to remove the high-frequency components in the output of the phase detector and to
remove high-frequency noise.

More important, the 1ow-pass filter controls the dynamic characteristics of the phase-locked loop.
These characteristics include capture and lock ranges, bandwidth, and transient response. The lock range is
defined as the range of frequencies over which the PLL system follows the changes in the input frequency

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

fIN. An equivalent term for lock range is tracking range. On the other hand, the capture range is the
frequency range in which the PLL acquires phase lock. Obviously, the capture range is always smaller than
the lock range.

(c) Voltage-controlled oscillator:

or

ld

A third section of the PLL is the voltage-controlled oscillator.The VCO generates an output
frequency that is directly proportional to its input voltage.Typical example of VCO is Signetics NE/SE 566
VCO, which provides simultaneous square wave and triangular wave outputs as a function of input voltage.
The block diagram of the VCO is shown in Fig 4.12. The frequency of oscillations is determined by thee
external R1 and capacitor C1 and the voltage VC applied to the control terminal 5. The triangular wave is
generated by alternatively charging the external capacitor C1 by one current source and then linearly
discharging it by another. The charging and discharging levels are determined by Schmitt trigger action. The
schmitt trigger also provides square wave output. Both the wave forms are buffered so that the output
impedance of each is 50 ohms.

Fig 4.12 (c) is a typical connection diagram. In this arrangement the R1C1 combination determines
the free running frequency and the control voltage VC at pin 5 is set by voltage divider formed with R2 and
R3. The initial voltage VC at pin 5 must be in the range

TU

Where +V is the total supply voltage.The modulating signal is ac coupled with the capacitor C and must be
<3 VPP. The frequency of the output wave forms is approximated by

JN

where R1should be in the range 2K < R1< 20K. For affixed VC and constant C1, the frequency fO can be
varied over a 10:1 frequency range by the choice of R1 between 2K < R1< 20K.

Fig 4.12 VCO Block Diagram

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

4.7 MONOLITHIC PHASE LOCK LOOPS IC 565:

TU

or

ld

Monolithic PLLs are introduced by signetics as SE/NE 560 series and by national semiconductors LM 560
series.

JN

Fig 4.13 Pin configuration of IC 565

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig 4.14 Block Diagram of IC 565

TU

Fig 4.13 and 4.14 shows the pin diagram and block diagram of IC 565 PLL. It consists of phase
detector,amplifier,low pass filter and VCO.As shown in the block diagram the phase locked feedback loop is
not internally connected.Therefore,it is necessary to connect out put of VCO to the phase comparator
input,externally.In frequency multiplication applications a digital frequency divider is inserted into the loop
i.e between pin 4 and pin 5.

JN

The centre frequency of the PLL is determined by the free-running frequency of the VCO and it is
given by

Where R1 and C1 are an external resistor and capacitor connected to pins 8 and 9, respectively.The
values of R1 and C1 are adjusted such that the free running frequency will be at the centre of the input
frequency range.The values of R1 are restricted from 2 k to 20 k,but a capacitor can have any value.A
capacitor C2 connected between pin 7 and the positive supply forms a first order low pass filter with an
internal resistance of 3.6 k.The value of filter capacitor C2 should be larger enough to eliminate possible
demodulated output voltage at pin 7 in order to stabilize the VCO frequency
The PLL can lock to and track an input signal over typically 60% bandwidth w.r.t fo as the center
frequency. The lock range fL and the capture range fC of the PLL are given by the following equations.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Where fo=free running frequency

V=(+V)-(-V)Volts

ld

And

JN

TU

or

From above equation the lock range increases with an increase in input voltage but decrease with
increase in supply voltage.The two inputs to the phase detector allows direct coupling of an input
signal,provided that there is no dc voltage difference between the pins and the dc resistances seen from
pins 2 and 3 are equal.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

JN

TU

or

ld

UNIT: 5

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

DATA CONVERTER INTEGRATED CIRCUITS

or

ld

5.1 INTRODUCTION

Fig 5.1 shows the application of A/D and D/A converters.

The transducer circuit will gives an analog signal. This signal is transmitted through the LPF circuit to avoid
higher components, and then the signal is sampled at twice the frequency of the signal to avoid the

TU

overlapping. The output of the sampling circuit is applied to A/D converter where the samples are
converted into binary data i.e. 0s and 1s. Like this the analog data converted into digital data.

The digital data is again reconverted back into analog by doing exact opposite operation of first half of the
diagram. Then the output of the D/A convertor is transmitted through the smoothing filter to avoid the

JN

ripples.

5.2

BASIC DAC TECHNIQUES

The input of the block diagram is binary data i.e, 0 and 1,it contain n number of input bits designated as
d1,d2,d3,..dn .this input is combined with the reference voltage called Vdd to give an analog output.
Where d1 is the MSB bit and dn is the LSB bit

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

or

ld

Vo=Vdd(d1*2-1+d2*2-2+d3*2-3+..+dn*2-n)

Fig 5.2: Basic DAC diagram

Weighted Resistor:

TU

5.2.1

JN

Fig: 5.3 simple 4-bit weighted resistor

Fig. 5.3 shows a simplest circuit of weighted resistor. It uses a summing inverting amplifier. It contains nelectronic switches (i.e. 4 switches) and these switches are controlled by binary input bits d1, d2, d3, d4. If
the binary input bit is 1 then the switch is connected to reference voltage VREF , if the binary input bit is 0

then the switch is connected to ground.

The output current equation is

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Io=I1+I2+ I3+I 4
Io= VREF (d1*2-1+d2*2-2+d3*2-3+d4*2-4 )

or

ld

The transfer characteristics are shown below (fig 5.4) for a 3-bit weighted resistor

TU

Fig 5.4 Transfer characteristics of 3-bit weighted resistor

Disadvantages of Weighted resistor D/A converter:

Wide range of resistors are required in this circuit and it is very difficult to fabricate such a wide range of

JN

resistance values in monolithic IC. This difficulty can be eliminated using R-2R ladder network.

5.2.2 R-2R LADDER DAC

Wide range of resistors required in binary weighted resistor type DAC. This can be avoided by using R-2R
ladder type DAC. The circuit of R-2R ladder network is shown in fig 5.5. The basic theory of the R-2R ladder
network is that current flowing through any input resistor (2R) encounters two possible paths at the far end.
The effective resistances of both paths are the same (also 2R), so the incoming current splits equally along
both paths. The half-current that flows back towards lower orders of magnitude does not reach the op amp,
and therefore has no effect on the output voltage. The half that takes the path towards the op amp along

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

the ladder can affect the output. The inverting input of the op-amp is at virtual earth. Current flowing in the

or

ld

elements of the ladder network is therefore unaffected by switch positions.

Fig 5.5: A 4-bit R-2R Ladder DAC

TU

If we label the bits (or inputs) bit 1 to bit N the output voltage caused by connecting a particular bit to Vr
with all other bits grounded is:
Vout = Vr/2N

where N is the bit number. For bit 1, Vout =Vr/2, for bit 2, Vout = Vr/4 etc.
Since an R/2R ladder is a linear circuit, we can apply the principle of superposition to calculate Vout. The
expected output voltage is calculated by summing the effect of all bits connected to Vr. For example, if bits

JN

1 and 3 are connected to Vr with all other inputs grounded, the output voltage is calculated by:
Vout = (Vr/2)+(Vr/8)
which reduces to
Vout = 5Vr/8.

An R/2R ladder of 4 bits would have a full-scale output voltage of 1/2 +1/4 + 1/8 + 1/16 = 15Vr/16 or 0.9375
volts (if Vr=1 volt) while a 10bit R/2R ladder would have a full-scale output voltage of 0.99902 (if Vr=1 volt).
NOTE:
The number of resistors required for an N-bit D/A converter is 2N in case of R-2R ladder D/A converter

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

whereas it is only N in the case of weighted resistor D/A converter.

5.2.3 INVERTED R-2R LADDER DAC
In weighted resistor and R-2R ladder DAC the current flowing through the resistor is always changed
because of the changing input binary bits 0 and 1. More power dissipation causes heating, which in turn
cerates non-linearity in DAC. This problem can be avoided by using INVERTED R-2R LADDER DAC (fig 5.6)

ld

In this MSB and LSB is interchanged. Here each input binary word connects the corresponding switch either
to ground or to the inverting input terminal of op-amp which is also at virtual ground. When the input

binary in logic 1 then it is connected to the virtual ground, when input binary is logic 0 then it is connected

or

to the ground i.e. the current flowing through the resistor is constant.

TU

Fig 5.6: Inverted R-2R ladder

5.3

DIFFERENT TYPES OF ADCS

It provides the function just opposite to that of a DAC. It accepts an analog input voltage Va and produces

JN

an output binary word d1,d2,d3.dn. Where d1 is the most significant bit and dn is the least significant bit.
ADCs are broadly classified into two groups according to their conversion techniques

1) Direct type

2) Integrating type

Direct type ADCs compares a given analog signal with the internally generated equivalent signal. This group
includes

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

i)
ii)
iii)
iv)

Flash (Comparator) type converter

Successive approximation type convertor
Counter type
Servo or Tracking type

Integrated type ADCs perform conversion in an indirect manner by first changing the analog input signal to

i)

Dual slope ADC

or

5.3.1 FLASH (COMPARATOR) TYPE CONVERTER:

ld

linear function of time or frequency and then to a digital code

A direct-conversion ADC or flash ADC has a bank of comparators sampling the input signal in parallel, each
firing for their decoded voltage range. The comparator bank feeds a logic circuit that generates a code for
each voltage range. Direct conversion is very fast, capable of gigahertz sampling rates, but usually has only 8
bits of resolution or fewer, since the number of comparators needed, 2N - 1, doubles with each additional

bit, requiring a large, expensive circuit. ADCs of this type have a large die size, a high input capacitance, high
power dissipation, and are prone to produce glitches at the output (by outputting an out-of-sequence
code). Scaling to newer submicrometre technologies does not help as the device mismatch is the dominant
design limitation. They are often used for video, wideband communications or other fast signals in optical

TU

storage.

A Flash ADC (also known as a direct conversion ADC) is a type of analog-to-digital converter that

uses a linear voltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to

successive reference voltages. Often these reference ladders are constructed of many resistors; however
modern implementations show that capacitive voltage division is also possible. The output of these
comparators is generally fed into a digital encoder which converts the inputs into a binary value (the

JN

collected outputs from the comparators can be thought of as a unary value).

Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a

series of comparators, each one comparing the input signal to a unique reference voltage. The comparator
outputs connect to the inputs of a priority encoder circuit, which then produces a binary output.

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig-5.7: flash (parallel comparator) type ADC

TU

The following (fig-5.7) illustration shows a 3-bit flashADC circuit:

VR is a stable reference voltage provided by a precision voltage regulator as part of the converter
circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at

each comparator, the comparator outputs will sequentially saturate to a high state. The priority
encoder generates a binary number based on the highest-order active input, ignoring all other active

JN

inputs.

5.3.2 COUNTER TYPE A/D CONVERTER

In the fig-5.8 the counter is reset to zero count by reset pulse. After releasing the reset pulse

the clock pulses are counted by the binary counter. These pulses go through the AND gate which is
enabled by the voltage comparator high output. The number of pulses counted increase with

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

ld

www.alljntuworld.in

Fig-5.8 Countertype A/D converter

time. The binary word representing this count is used as the input of a D/A converter whose output

is a stair case. The analog output Vd of DAC is compared to the analog input input Va by the
comparator. If Va>Vd the output of the comparator becomes high and the AND gate is enabled to
allow the transmission of the clock pulses to the counter. When Va<Vd the output of the comparator
becomes low and the AND gate is disabled.This stops the counting we can get the digital data.

JN

TU

5.3.3 SERVO TRACKING A/D CONVERTER

Fig: 5.9 A tracking A/D converter (b) waveforms associated with a tracking A/D converter
An improved version of counting ADC is the tracking or servo converter shown in fig 5.9.

The circuit consists of an up/down counter with the comparator controlling the direction of the
count. The analog output of the DAC is Vd and is compared with the analog input Va.If the input Va
is greater than the DAC output signal, the output of the comparator goes high and the counter is

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

caused to count up. The DAC output increases with each incoming clock pulse when it becomes
more than Va the counter reverses the direction and counts down.
5.3.4 SUCCESSIVE-APPROXIMATION ADC:
One method of addressing the digital ramp ADC's shortcomings is the so-called successiveapproximationADC. The only change in this design as shown in the fig 5.10 is a very special

ld

counter circuit known as a successive-approximation register. Instead of counting up in binary

sequence, this register counts by trying all values of bits starting with the most-significant bit and
finishing at the least-significant bit. Throughout the count process, the register monitors the

comparator's output to see if the binary count is less than or greater than the analog signal input,

or

adjusting the bit values accordingly. The way the register counts is identical to the "trial-and-fit"

method of decimal-to-binary conversion, whereby different values of bits are tried from MSB to
LSB to get a binary number that equals the original decimal number. The advantage to this counting
strategy is much faster results: the DAC output converges on the analog signal input in much larger

JN

TU

steps than with the 0-to-full count sequence of a regular counter.

Fig: 5.10 successive approximation ADC

The successive approximation analog to digital converter circuit typically consists of four chief sub

circuits:

1. A sample and hold circuit to acquire the input voltage (Vin).

2. An analog voltage comparator that compares Vin to the output of the internal DAC and
outputs the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register sub circuit designed to supply an approximate digital

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

code of Vin to the internal DAC.

4. An internal reference DAC that supplies the comparator with an analog voltage equivalent
of the digital code output of the SAR for comparison with Vin.
The successive approximation register is initialized so that the most significant bit (MSB) is equal to
a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code

ld

(Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage
exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is
set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested.

The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC

or

at the end of the conversion (EOC).

Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage. The objective is to
approximately digitize x to an accuracy of 1/2n. The algorithm proceeds as follows:

1. Initial approximation x0 = 0.
2. ith approximation xi = xi-1 - s(xi-1 - x)/2i.

where, s(x) is the signum-function(sgn(x)) (+1 for x 0, -1 for x < 0). It follows using mathematical induction
that |xn - x| 1/2n.

As shown in the above algorithm, a SAR ADC requires:

TU

1. An input voltage source Vin.

2. A reference voltage source Vref to normalize the input.

3. A DAC to convert the ith approximation xi to a voltage.
4. A Comparator to perform the function s(xi - x) by comparing the DAC's voltage with the
input voltage.

JN

5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2i.

A successive-approximation ADC uses a comparator to reject ranges of voltages, eventually settling

on a final voltage range. Successive approximation works by constantly comparing the input voltage to the
output of an internal digital to analog converter (DAC, fed by the current value of the approximation) until
the best approximation is achieved. At each step in this process, a binary value of the approximation is

stored in a successive approximation register (SAR). The SAR uses a reference voltage (which is the largest
signalthe ADC is to convert) for comparisons. For example if the input voltage is 60 V and the reference
voltage is 100 V, in the 1st clock cycle, 60 V iscompared to 50 V (the reference,divided by two. This is the

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

voltage at the output of the internal DAC when the input is a '1' followed by zeros), and the voltage from
the comparator is positive (or '1') (because 60 V is greater than 50 V). At this point the first binary digit
(MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being halfway between
100 and 50 V: This is the output of the internal DAC when its input is '11' followed by zeros) because 60 V is
less than 75 V, the comparator output is now negative (or '0'). The second binary digit is therefore set to a
'0'. In the 3rd clock cycle, the input voltage is compared with 62.5 V (halfway between 50 V and 75 V: This is

ld

the output of the internal DAC when its input is '101' followed by zeros). The output of the comparator is
negative or '0' (because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle
similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC output for '1001'

followed by zeros). The result of this would be in the binary form 1001. This is also called bit-weighting

or

conversion, and is similar to a binary search. The analogue value is rounded to the nearest binary value

below, meaning this converter type is mid-rise (see above). Because the approximations are successive (not
simultaneous), the conversion takes one clock-cycle for each bit of resolution desired. The clock frequency
must be equal to the sampling frequency multiplied by the number of bits of resolution desired. For

example, to sample audio at 44.1 kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be
required. ADCs of this type have good resolutions and quite wide ranges. They are more complex than some
other designs.

JN

TU

5.3.5 DUAL-SLOPE ADC

Fig 5.11 Functional diagram of dual slope ADC

An integrating ADC (also dual-slopeADC) shown in fig 5.11a applies the unknown input voltage to the input
of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a known
reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator
output returns to zero (the run-down period). The input voltage is computed as a function of the reference
voltage, the constant run-up time period, and the measuredrun-down time period. The run-down time
measurement is usually made in units of the converter's clock, so longer integration times allow for higher

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

resolutions. Likewise, the speed of the converter can be improved by sacrificing resolution. Converters of

or

ld

this type (or variations on the concept) are used in most digital voltmeters for their linearity and flexibility.

Fig 5.11b o/p waveform of dual slope ADC

In operation the integrator is first zeroed (close SW2), then attached to the input (SW1 up) for a fixed time
M counts of theclock (frequency 1/t). At the end of that time it is attached to the reference voltage (SW1
down) and the number of counts Nwhich accumulate before the integrator reaches zero volts output and

the comparator output changes are determined. The waveform of dual slope ADC is shown in fig 5.11b.
The equations of operation are therefore:

TU

And

For an integrator,

JN

The voltage Vo will be equal to V1 at the instant t2 and can be written as

The voltage V1 is also given by

So,

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

Putting the values of

and

, we get

5.4

SPECIFICATIONS FOR DAC/ADC

ld

Or,

1.
RESOLUTION: The Resolution of a converter is the smallest change in voltage which may
be produced at the output of the converter.

or

Resolution (in volts)=(VFS)/(2n-1)= 1 LSB increment

Ex: an 8-bit D/A converter have 28-1=255 equal intervals. Hence the smallest change in output
voltage is (1/255) of the full scale output range.

An 8-bit DAC is said to have: 8 bit resolution

: a resolution of 0.392 of full scale

: a resolution of 1 part in 255

TU

Similarly the resolution of an A/D converter is defined as the smallest change in analog input for a
one bit change at the output.
Ex: the input range of 8-bit A/D converter is divided into 255 intervals. So the resolution for a 10V
input range is 39.22 mV(=10V/255)
2.

LINEARITY: The linearity of an A/D or D/A converter is an important measure of its

accuracy and tells us how close the converter output is to its ideal characteristics.

3.

GLITCHES (PARTICULARLY DAC): In transition from one digital input to the next, like

JN

0111 to 1000, it may effectively go through 1111 or 0000, which produces unexpected voltage
briefly. If can cause problems elsewhere.

4.

ACCURACY: Absolute accuracy is the maximum deviation between the actual converter

output and the ideal converter output.

5.

MONOTONIC: A monotonic DAC is the one whose analog output increases for an increase

in digital input. It is essential in control applications. If a DAC has to be monotonic, the error should
de lessthan (1/2) LSB at each output level.

6.

SETTLING TIME: The most important dynamic parameter is the settling time. It represents

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

the time it takes for the output to settle within a specified band (1/2) LSB of its final value
following a code change at the input. It depends upon the switching time of the logic circuitry due to
internal parasitic capacitances and inductances. Its ranges from 100ns to 10s.
7.

STABILITY: The performance of converter changes with temperature, age and power

JN

TU

or

ld

supply variations. So the stability is required.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

19. UNIT WISE BITS

1. Which of the following has least packaging density
a) PMOS
b) NMOS
c) CMOS
d) BJT

or

ld

2. In NMOS NAND circuit the Q1 and Q2 where the inputs are given are used for:
a) Switching
b) Loading
c) Sourcing
d) Sinking

3. In NMOS NOR circuit the Q3 whose drain is connected to Vcc is used for:
a) Loading
b) switching
c) Sourcing
d) Sinking

TU

4. The voltage in the undefined level is :

a) Low voltage
b) Threshold voltage
c) High voltage
d) Saturation level

JN

5. Noise margin constitute under :

a) Dynamic characteristic
b) Static characteristic
c) Voltage levels
d) Power rails

6. The following are not applicable for BJT:

a) Power rails
b) Fan in and fan out
c) Noise margin
d) None of the above

7. Component instantiation is under:

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

a)
b)
c)
d)

Structural model
Behavioral model
Data flow model
Verilog model

or

9. Concurrent statement declaration is seen in ___

a) Structural model
b) Behavioral model
c) Data flow model
d) Verilog model
10. Data types in VHDL are classified as:
a) 1
b) 5
c) 8
d) 2

ld

8. In ___ model entity is described as a set of interconnected components.

a) Data flow
b) Behavioral
c) Structural
d) None of the above

JN

TU

11. The electrical characteristics of CMOS constitute of __ and _____

12. The logic in which the diode is the main circuitry component is___
13. 74 series stands for ___.
14. Power dissipation per gate in TTL is ______
15. The other alternate available to achieve high speed TTL apart from Darlington pair is__
16. Totem pole has __ configuration.
17. The key word for structural model is_
18. Behavioral description is done using the _
19. ____ type defines the true or false statements.
20. RTL stands for_____.
KEY:

1.
2.
3.
4.
5.
6.
7.
8.

A
A
A
B
B
B
C
C

43

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

or

9. C
10. D
11. Steady state and dynamic characteristic
12. Diode logic
13. TTL
14. 10mW
15. Reducing the values of resistors
16. Complimentary
17. Component
18. HDL languages
19. Boolean data type
20. Register transfer logic

ld

www.alljntuworld.in

1. The circuit operated on the binary values is:

a) Logic circuit
b) Binary circuit
c) Switching circuit
d) VHDL circuit

TU

2. The circuit whose output depends only on the present values of input is:
A) Combinational circuit
B) Sequential circuit
C) Binary circuit
D) Logic circuit

JN

3. Code converter is an example of:

a) Combinational circuit
b) Sequential circuit
c) Binary circuit
d) Logic circuit

4. Counter is a :
a) Combinational circuit
b) Sequential circuit
c) Binary circuit
d) Logic circuit

5. RAM are ___

44

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

a)
b)
c)
d)

Non volatile
Volatile
Temporary
Permanent

or

7. Encoder involves:
a) N to 2n
b) N to 2n
c) 2n to n
d) N to n2

ld

6. Erasing of EPROM is by:

a) Switching
b) UV RAYS
c) Infra red rays
d) X rays

TU

8. No rules of encoder are followed by:

a) 4 to 2 encoder
b) 8 to 3 encoder
c) Key board encoder
d) None of the above

JN

9. PROM consists:
a) Non programmable or
b) Programmable and
c) Programmable or
d) None of the above

10. Refresh cycle is associated with :

a) Static ram
b) ROM
c) EPROM
d) Dynamic RAM

45

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

KEY:

JN

TU

1. A
2. A
3. A
4. B
5. B
6. B
7. C
8. C
9. C
10. D
11. 1
12. Past
13. Programmable read only memory
14. 8
15. 8
16. Concurrent
17. Behavioral
18. Less
19. Library
20. priority

or

ld

11. In keyboard encoder __ switch can be closed at a time

12. In sequential circuit output depends on present and ___
13. PROM stands for_____
14. In 256X8 there are ___ address lines
15. In 256X8 there are ___ data lines
16. Data flow model involves___ statements
17. Sequential statements are used in _ statements.
18. Static ram has ___capacity than dynamic ram
19. Specifications are mentioned in ___
20. ___ encoder is used to judge the priority

OBJECTIVE QUESTIONS FROM UNIT 1, 2, 3, 4

1. A transconductance amplifier is one which has (a)

Input current I and output voltage V
(b) Input voltage V and output current I

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

(c) Input voltage Vi and output voltage Vo

(d) Input current Iin and output current Io

ld

2. A transresistance amplifier is one which has

(a) Input current Iand output voltage V
(b) Input voltage V and output current I
(c) Input voltage Viand output voltage Vo
(d) Input current Iin and output current I0

or

3. The other name of voltage follower is

(a)
differential amplifier
(b) inverting amplifier
(c)
non-inverting amplifier
(d)
unity-gain amplifier

4. An op-amp current-to-voltage converter is also called

(a)
transconductance amplifier
(b)
transresistance amplifier
(c)
trans impedance amplifier
(d)
none of the above

TU

5. A volage-to-current op-amp converter is also called

(a)
transconductance amplifier
(b)
transresistance amplifier
(c)
trans impedance amplifier
(d)
none of the above

JN

6. An ideal op-amp should have

(a) zero input impedance and output impedance
(b) infinite input and output impedance
(c) infinite input impedance and zero output
(d) impedance zero input impedance and infinite output impedance

7.

An ideal op-amp should have

(a) Low gain at low frequencies
(b) low gain at low frequency and high gain at high frequencies
(c) high gain at low frequency and low gain at high frequencies
(d) high gain at all frequencies

8.

The actual gain of an op-amp at DC is of the order

(a)
10 to 100
(b)
100 to 1000

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

(c)
(d)

100 to 100,000
1000,00,0 to 100,000,000

9. Drift of amplifier means

(a) ) Variation of gain with load
(b) Variation of gain with frequency
(c) Change in sensitivity due
(d) none of the above

to

variation

in

temperature

ld

10. Which of the following amplifier compensates for drift?

(a) ) low-gain amplifier
(b) high-gain amplifier
(c) DC amplifier
(d) Differential amplifier

12. An ideal amplifier should have

(a) infinite gain at all frequencies
(b) Large bandwidth
(c) ) zero phase shift
(d) all of the above

or

11. In addition to reduction to drift, the advantage of a differential amplifier is

(a) ) mixing of two input voltages
(b) an output of either polarity
(c) ) rejection of common-mode signal
(d) all of the above

TU

13. An amplifier is an unstable condition when

(a) gain is low
(b) load is variable
(c) phase shift is 180
(d) supply is rectified DC

JN

14. Noise in op-arnp can be reduced to

(a) ) shielding
(b) use IPF
(c) ) proper grounding
(d) all of the above

15. Which of the following is linear system?

(a)
(b)
(c)
(d)

Log amplifier
I-to V converter
V-to-I Converter
All of the above

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

16. A logarithmic amplifier can be used as

(a) ) divider
(b) multiplier
(c) ) subtractor
(d) none of the above

or

18. A chip having more than 150 logic gates is known as

(a) LSI chip
(b) MSI chip
(c) ) SSI chip
(d) none of the above

ld

17. An integrator is mostly preferred over a differentiator because of

(a) ) more stability
(b) less voltage drift
(c) ) less noise
(d) all of the above

19.If a square wave is integrated by integrator using operational amplifier, the output is
(a) Triangular wave
(b) Ramp
(c) ) Sine wave
(d) None of the above

TU

20. Monolithic IC waters are typically of

(a) l/8-inch diameter
(b) 1/4- inch diameter
(c ) 1- inch diameter
(d) 2-inch diameter

JN

21. A good op-amphas

(a) ) Very high bandwidth
(b) Narrow bandwidth
(c) ) high selectivity
(d) All of the above
22. When an op-amp is operated in common-mode fashion, CMRR should be
(a) ) zero
(b) infinitelyhigh
(c) ) very small
(d) 5 dB
23. Which amplifier will be preferred for highest gain?
(a) ) Darlington's pair
(b) operational amplifier
(c) ) cascade amplifier
(d) none of the above
24. Decibel is defined in terms of
(a) ) voltage ratio
(b) current ratio.

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

(c) ) power ratio

(d) none of the above
25. A multivibrator produces
(a) ) pure sine waves
(b) square waves
( c) distortion sine waves
(d) sawtooth voltages

ld

26. A linear system can be described by

(a) ) state transition equation
(b) differential equation
(c) dynamic equation
(d) none of the above

or

27. At which of the following frequency, the gain of op-amp will be zero?
(a) ) ~ cut-off frequency
(b) a cut-off frequency
(c) ) unity-gain cross-over frequency
(d) gain cross-over frequency

28. The loss of precision in a quantity is called

(a) ) down time
(b) delay
(c) ) unavoidable delay
(d) none of the above

TU

29. A system is critically damp-vi Now if the gain of the system is increased, the system will
behave
(a) ) over-damped
(b) under-damped
(c) ) oscillatory
(d) critically damped

JN

30.Silicon is preferred for semiconductor devices because of its

( a) abundant availability
(b) easy formation of oxide layer
(c) ) hood mechanical strength
(d) all of the above

31.A monolithic circuit means

(a) circuit from single crystal
(b) circuit from more than one crystal
(c) ) uses double price of crystal to form a circuit
(d) none of the above
32.Photolithography involves
(a) ) making photographic mask and photo etching
(b) only photo etching
(c) ) only masking
(d) none of the above

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

33.Aluminium is generally used for metallization because it

(a) forms good mechanical bonds with silicon
(b) is a relatively good conductor
(c) ) deposits aluminium films on the surface
(d) all of the above

ld

34.The standard package configurations of manufacturing IC.

( a) glass metal package
(b) ceramic flat package
(c) ) dual-in-line
(d) all of the above

36.

or

35.Sheet resistance ofIC is defined in

(a) Ohms per square mm
(b) Ohms square mm
(c) Ohms per mm
(d) Ohms per cubic mm

The preference of polysilicon over aluminium

(a) ) lowers threshold voltage
(b) reduces capacitances
(c) good bond and mechanical strength, a form of silicon
(d) all of the above

TU

37. The CMRR of A 741 is

(a) ) 70 dB
(b) 50 dB
(c) ) 40 dB
(d) none of the above

38. For large CMRR, Acm should be

(a) as large as possible
(b) as small as possible
(c) ) zero
(d) level to Adm

JN

39. MOSFET op-amp is preferred over BJT and FET because of

(a) ) high input resistance 1012Q
(b) low input current, 1 PA
(c) ) high slew rate, 10 V /usec
(d) all the above
40.DC characters of op-amp are
(a) ) input bias and offset current
(b) Input offset voltage
(c) Thermal drift
(d) all of the above
41. Thermal drift of op-amp parameters
(a) force air cooling only
(b) carefully print circuit board layout
(c) ) both a and b

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

(d) keep op-amp away from source of heat

42. AC characteristics of op-amp includes
(a) ) frequency response
(b) slew rate
(c) both a and b
(d) none of the above

or

44. The slew rate for IC 741 is

(a) ) 0.5 V/sec
(b) 0.9 V/sec
(c) ) 0.8 V/usec
(d) 1 V/sec

ld

43. An ideal op-amp should have open-loop gain

(a) around 90 dB constant over audio and RF frequency
(b) less than 90 dB, varies on audio and RF frequency
(c) ) 20 dB, constant audio and RF frequency
(d) none of the above

45. Op-amp 74lC cannot be used for high-frequency applications because of

(a) ) low slew rate
(b) high slew rate
(c) O.T. V/QS
(d) none of the above
46. Number of diodes required in half-wave rectifier circuit using op-amp is
(a) I
(b) 2
(c) 3
(d)4

TU

47. Number of diodes required in full-wave rectifier using op-amp is

(a) 2
(b) 3
(c) 1
(d)4
OBJECTIVE QUESTIONS

JN

1. In a digital representation of voltages using an 8-bit binary code, how many values can be
defined?
a) 16
b) 64
c) 128
d) 256
Ans D

2. In a digital reproduction of an analog curve, accuracy can be increased by

a) Sampling the curve more often.
b) Sampling the curve less often

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

c) decreasing the number of bits used to represent each sampled value

d) all of the above

ans:A

. If the

ld

3. A binary-weighted-input digital-to-analog converter has an input resistor of 100 k

resistor is connected to a 5 V source, current through the resistor is
.
a) 50 mA
b) 50 micro amps
c) 5 mA
d) 500 micro amps
ans: D

. If

or

4. A binary-weighted-input digital-to-analog converter has a feedback resistor, Rf, of 12 k

50 A of current is through the resistor, voltage out of the circuit is
_.
a) 0.6 V
b) 0.6 V
c) 0.1 V
d) 0.1 V
Ans: B
.

5. A 4-bit R/2R ladder digital-to-analog converter uses

a) One resistor value
b) Two resistor value
c) Three resistor value
d) Four resistor value

Ans: B

TU

6. In a 4-bit R/2R ladder digital-to-analog converter, because of negative feedback, the

operational amplifier keeps the inverting (minus) input near
.
a) 5 V
b) 0 V
c) A voltage determined by the binary weighted input
d) None
Ans : B

JN

7. The resolution of a 6-bit DAC is

a) 63 %
b) 64%
c) 15.8%
d) 1.58%

8. For a 4-bit DAC, the least significant bit (LSB) is

a) 6.25% of full scale
b) 0.625% of full scale
c) 12% of full scale
d) 1.2% of full scale

Ans : D
.

Downloaded From JNTU World (http://www.alljntuworld.in)

Ans: A

www.alljntuworld.in

JNTU World

9. If a DAC has a full-scale, or maximum, output of 12 V and accuracy of

maximum error for any output voltage is
_.
a) 12 V
b) 120 mV
c) 12 mV
d) 0 V
Ans: A

0.1%, then the

or

ld

10. Settling time is normally defined as the time it takes a DAC to settle within
a) 1/8 LSB of its final value when a change occurs in the input code
b) 1/4 LSB of its final value when a change occurs in the input code
c) 1/2 LSB of its final value when a change occurs in the input code
Ans: c.
d) 1 LSB of its final value when a change occurs in the input code

11. In a flash analog-to-digital converter, the output of each comparator is connected to an input
of a
.
a) Decoder
b) Priority encoder
c) Multiplexer
d) Demultiplexer
Ans : B

TU

12. The dual-slope analog-to-digital converter finds extensive use in

a) Digital voltmeters
b) Function generators
c) Frequency counters
d) All of the above

Ans: D

JN

13. Which A/D conversion method has a fixed conversion time?

a) Single-slope analog-to-digital converter
b) Dual slope analog-to-digital converter
c) Digital ramp analog-to-digital converter
d) Successive-approximation analog-to-digital converter
14. The ADC0804 is an example of a
.
a) Single-slope analog-to-digital converter
b) Dual slope analog-to-digital converter
c) Digital ramp analog-to-digital converter
d) Successive-approximation analog-to-digital converter
15. In troubleshooting a DAC, we check its performance characteristics, such as
a) Non monotonicity
b) Differential nonlinearity
c) Low and high gain

Downloaded From JNTU World (http://www.alljntuworld.in)

Ans: D

Ans: D
.

www.alljntuworld.in

JNTU World

d) All of the above

Ans: D

16. Which is not an A/D conversion error?

a. differential nonlinearity
b. Missing code
c. Incorrect code
d. Offset

Ans: A

ld

17. What do we call the manipulation of an analog signal in a digital domain?

a) Analog to digital conversion
b) Digital-to-analog conversion
c) Digital signal processing
d) Signal filtering

or

ans B

18. How many 4-bit parallel adders would be required to add two binary numbers each
representing decimal numbers up through 30010?
a) 1
b) 2
c) 3
d) 4
ans: C
.

TU

19. The carry propagation can be expressed as

a) C=AB
b) C=A+B
c) C=A xor B

d) C=A+B

JN

20. Which gate is best used as a basic comparator?

a) NOR
b) OR
c) EXOR
d) AND

Ans:B

Ans: c

21. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What
are the output levels?
a) A > B = 1, A < B = 0, A < B = 1
b) A > B = 0, A < B = 1, A = B = 0
c) A > B = 1, A < B = 0, A = B = 0
ans:c
d) A > B = 0, A < B = 1, A = B = 1
22. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one OR gate

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

c) One 4-input NAND gate, one inverter

d) One 4-input AND gate, one inverter

ans: D

ld

23. A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which
output goes LOW when the inputs are 1001?
a) 0
b) 3
c) 9
d) None. All o/ps are high
ans: D

ans: D

25. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
a) 1
b) 2
c) 4
d) 8

ans: C

26. How many data select lines are required for selecting eight inputs?
a) 1
b) 2
c) 3
d) 4

ans:c

TU

or

24. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
a) 5
b) 6
c) 7
d) 8

JN

27. A decoder can be used as a demultiplexer by

.
a) tying all enable pins LOW
b) tying all data-select lines LOW
c) tying all data-select lines LOW
d) using the input lines for data selection and an enable line for data input. Ans: D

28. When adding an even parity bit to the code 110010, the result is
a) 1110010
b) 1111001
c) 110010

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

d) 001101

ans:a

Ans: C

30. Which is not an example of a truncated modulus?

a) 8
b) 9
c) 11
d) 15

Ans:a

or

ld

29. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16

31. Which of the following is an invalid state in an 8421 BCD counter?

a) 1110
b) 0000
c) 0010
d) 0001
.

Ans: D

TU

32. A 4-bit counter has a maximum modulus of

a) 3
b) 6
c) 8
d) 16

Ans:a

JN

33. A BCD counter is a

.
a) Binary counter
b) Full modulus counter
c) Decade counter
d) Divide by 10 counter

34. Three cascaded modulus-5 counters have an overall modulus of

a) 5
b) 25
c) 125
d) 500
35. The designation
means that the
.
a) up count is active-low, the down count is active-high

Downloaded From JNTU World (http://www.alljntuworld.in)

Ans: c

Ans: C

www.alljntuworld.in

JNTU World

b) up count is active-HIGH, the down count is active-LOW

c) up and down counts are both active-low
d) up and down counts are both active-high

Ans: B

ld

36. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state on the next
clock pulse. To what state does the counter go?
a) 1101
b) 1011
c) 1111
d) 0000
Ans: B
37. The terminal count of a 3-bit binary counter in the DOWN mode is
a) 000
b) 111
c) 101
d) 010

or

38. The final output of a modulus-8 counter occurs one time for every
a) 8 clock pulses
b) 16 clock pulses
c) 24 clock pulses
d) 32 clock pulses

Ans: A

_.

TU

39. A counter with a modulus of 16 acts as a

a) divide-by-8 counter
b) divide-by-16 counter
c) divide-by-32 counter
d) divide-by-64 counter

Ans: A

JN

40. Three cascaded decade counters will divide the input frequency by
a) 10
b) 20
c) 100
d) 1000

41. How much storage capacity does each stage in a shift register represent?
a) 1 bit
b) 2 bits
c) 4 bits

Downloaded From JNTU World (http://www.alljntuworld.in)

Ans: B

Ans: D

www.alljntuworld.in

JNTU World

d) 8 bits

Ans: a

42. Which is not characteristic of a shift register?

a) Serial in/parallel in
b) Serial in/parallel out
c) Parallel in/serial out
d) Parallel in/parallel out

Ans:a

or

ld

43. To serially shift a nibble (four bits) of data into a shift register, there must be----a) one clock pulse
b) two clock pulse
c) four clock pulse
d) one clock pulse for each 1 in the data
Ans c

44. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state 11110000. After two clock pulses, the register
contains
.
a) 10111000
b) 10110111
c) 11110000
d) 11111100
Ans: D

TU

45. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is
.
waiting to enter. After four clock pulses, theregister contains
a) 0000
b) 1111
c) 0111
d) 1000
Ans:c

JN

46. A 74HC195 4-bit parallel access shift register can be used for
a) serial in/serial out operation
b) serial in/parallel out operation
c) parallel in/serial out operation
d) all of the above

Ans: D

47. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock
pulses, the data outputs are
.
a) 1110
b) 0001
c) 1100
d) 1000
Ans: B

Downloaded From JNTU World (http://www.alljntuworld.in)

www.alljntuworld.in

JNTU World

JN

TU

or

ld

48. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second
clock pulse?
a) 1101000000
b) 0010100000
c) 1100000000
d) 0000000000
Ans: B

Downloaded From JNTU World (http://www.alljntuworld.in)

JNTU World

JN

TU

or

ld

www.alljntuworld.in

Downloaded From JNTU World (http://www.alljntuworld.in)