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TUSB3410, TUSB3410I
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
TUSB3410x USB to Serial Port Controller
1 Device Overview
1.1
Features
Fully Compliant With USB 2.0 Full-Speed
Specifications: TID#40340262
Supports 12-Mbps USB Data Rate (Full Speed)
Supports USB Suspend, Resume, and Remote
Wake-Up Operations
Configurable to Bus-Powered and Self-Powered
Operation
Supports a Total of Three Input and Three Output
(Interrupt, Bulk) Endpoints
Integrated 8052 Microcontroller With:
256 8 RAM for Internal Data
10K 8 ROM (With USB and I2C Bootloader)
16K 8 RAM for Code Space Loadable From
Host or I2C Port
2K 8 Shared RAM Used for Data Buffers and
Endpoint Descriptor Blocks (EDBs)
Master I2C Controller for EEPROM Device
Access
MCU Operates at 24 MHz, Providing 2-MIPS
Operation
128-ms Watchdog Timer
1
1.2
Applications
Modems
Peripherals:
Printers, Handheld Devices, and so on
1.3
Enhanced UART Features:
Software and Hardware Flow Control
Automatic RS-485 Bus Transceiver Control,
With and Without Echo
Selectable IrDA Mode for Up to 115.2-kbps
Transfer
Software-Selectable Baud Rate From 50 BPS to
921.6 kbps
Programmable Serial-Interface Characteristics
5-, 6-, 7-, or 8-Bit Characters
Even, Odd, or No Parity-bit Generation and
Detection
1-, 1.5-, or 2-Stop Bit Generation
Line Break Generation and Detection
Internal Test and Loopback Capabilities
Modem Control Functions (CTS, RTS, DSR, RI
and DCD)
Internal Diagnostic Capability
Loopback Control for Communications
Link-Fault Isolation
Break, Parity, Overrun, Framing-Error
Simulation
Medical Meters
DSP and C Interface
Description
The TUSB3410 device provides bridging between a USB port and an enhanced UART serial port. The
device contains an 8052 microcontroller unit (MCU) with 16KB of RAM that can be loaded from the host or
from the external onboard memory through an I2C. The device also contains 10KB of ROM that allows the
MCU to configure the USB port at boot time. The ROM code also contains an I2C bootloader. All device
functions (such as the USB command decoding, UART setup, and error reporting) are managed by the
internal MCU firmware in unison with the PC host.
Device Information
PART NUMBER
TUSB3410
PACKAGE
BODY SIZE
VQFN (32)
5.00 mm 5.00 mm
LQFP (32)
7.00 mm 7.00 mm
1. For all available packages, see the orderable addendum at the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB3410, TUSB3410I
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
1.4
www.ti.com
Functional Block Diagram
12 MHz
Clock
Oscillator
PLL and
Dividers
8052
Core
24 MHz
DP, DM
2 16-Bit
Timers
10K 8
ROM
USB
TxR
8
16K 8
RAM
4
Port 3
8
2K 8
SRAM
I 2C
Controller
P3.4
P3.3
P3.1
P3.0
I2C Bus
USB
Serial
Interface
Engine
CPU-I/F
Suspend/
Resume
DMA-1
DMA-3
8
8
UBM
USB Buffer
Manager
RTS
CTS
DTR
DSR
UART1
SIN
SOUT
TDM
Control
Logic
IR
Encoder
IR
Decoder
M
U
X
Device Overview
M
U
X
SOUT/IR_SOUT
SIN/IR_SIN
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SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Table of Contents
1
2
3
Device Overview ......................................... 1
5.4
Processor Subsystems .............................. 16
1.1
Features .............................................. 1
5.5
Memory .............................................. 24
1.2
Applications ........................................... 1
5.6
Boot Modes.......................................... 67
1.3
Description ............................................ 1
1.4
Application, Implementation, and Layout ......... 84
Functional Block Diagram ............................ 2
6.1
Application Information .............................. 84
Revision History ......................................... 3
Pin Configuration and Functions ..................... 4
6.2
Typical Application
6.3
Layout ............................................... 88
3.1
Pin Diagrams ......................................... 4
6.4
Power Supply Recommendations
3.2
Pin Functions ......................................... 5
6.5
6.6
Crystal Selection .................................... 90
External Circuit Required for Reliable Bus Powered
Suspend Operation ................................. 91
............................................ 6
4.1
Absolute Maximum Ratings .......................... 6
4.2
ESD Ratings .......................................... 6
4.3
Recommended Operating Conditions ................ 6
4.4
Thermal Information .................................. 6
4.5
Electrical Characteristics ............................. 7
4.6
Timing and Switching Characteristics Information.... 8
4.7
Typical Characteristics ............................... 9
Detailed Description .................................. 10
5.1
Overview ............................................ 10
5.2
Functional Block Diagram ........................... 11
5.3
Device Functional Modes ........................... 11
Specifications
..................................
..................
84
90
Device and Documentation Support ............... 92
7.1
Documentation Support ............................. 92
7.2
Related Links ........................................ 92
7.3
Community Resources .............................. 92
7.4
Trademarks.......................................... 92
7.5
Electrostatic Discharge Caution ..................... 92
7.6
Glossary ............................................. 92
Mechanical Packaging and Orderable
Information .............................................. 92
8.1
Packaging Information
..............................
92
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2013) to Revision I
Page
Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section,
and Mechanical, Packaging, and Orderable Information section .............................................................. 1
Deleted Ordering Information table. ................................................................................................ 1
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Pin Configuration and Functions
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SLLS519I MARCH 2002 REVISED NOVEMBER 2015
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3 Pin Configuration and Functions
3.1
Pin Diagrams
RHB Package
32-Pin VQFN
Top View
VF Package
32-Pin LQFP
Bottom View
Pin Configuration and Functions
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3.2
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Pin Functions
Table 3-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
(1)
CLKOUT
22
Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see
Section 5.5.5.5)
CTS
13
UART: Clear to send (2)
DCD
15
UART: Data carrier detect (2)
DM
I/O
Upstream USB port differential data minus
DP
I/O
Upstream USB port differential data plus
DSR
14
UART: Data set ready (2)
DTR
21
UART: Data terminal ready (1)
GND
8, 18, 28
GND
P3.0
32
I/O
General-purpose I/O 0 (port 3, terminal 0) (3) (4) (5)
P3.1
31
I/O
General-purpose I/O 1 (port 3, terminal 1) (3) (4) (5)
P3.3
30
I/O
General-purpose I/O 3 (port 3, terminal 3) (3) (4) (5)
P3.4
29
I/O
General-purpose I/O 4 (port 3, terminal 4) (3) (4) (5)
PUR
Pullup resistor connection (6)
RESET
Device master reset input (2)
RI/CP
16
UART: Ring indicator (2)
RTS
20
UART: Request to send (1)
SCL
11
Master I2C controller: clock signal (1)
SDA
10
I/O
Master I2C controller: data signal (1) (4)
SIN/IR_SIN
17
UART: Serial input data / IR Serial data input (7)
SOUT/IR_SOUT
19
UART: Serial output data / IR Serial data output (8)
SUSPEND
Suspend indicator terminal (3). When this terminal is asserted high, the device is in suspend mode.
TEST0
23
Test input (for factory test only). This terminal must be tied to VCC through a 10-k resistor.
TEST1
24
Test input (for factory test only) (4). This terminal must be tied to VCC through a 10-k resistor.
3, 25
PWR
3.3 V
PWR
1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When
VREGEN is high, 1.8 V must be supplied externally.
VREGEN
This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator.
WAKEUP
12
Remote wake-up request terminal. When low, wakes up system (4)
X1/CLKI
27
12-MHz crystal input or clock input
X2
26
12-MHz crystal output
VCC
VDD18
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
and
Digital ground
3-state CMOS output (4-mA drive and sink)
TTL-compatible, hysteresis input
3-state CMOS output (12-mA drive and sink)
TTL-compatible, hysteresis input, with internal 100-A active pullup resistor
The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two
clock cycles and then the output is high impedance.
3-state CMOS output (8-mA drive and sink)
TTL-compatible input without hysteresis, with internal 100-A active pullup resistor
Normal or IR mode: 3-state CMOS output (4-mA drive and sink)
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Pin Configuration and Functions
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SLLS519I MARCH 2002 REVISED NOVEMBER 2015
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4 Specifications
4.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
0.5
3.6
VI
Input voltage
0.5
VCC + 0.5
VO
Output voltage
0.5
VCC + 0.5
IIK
Input clamp current
20
mA
IOK
Output clamp current
20
mA
Tstg
Storage temperature
(1)
65
150
Standard
55
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2
ESD Ratings
Electrostatic discharge (ESD)
performance
VESD
(1)
(2)
Industrial
VALUE
UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
2000
kV
Charged Device Model (CDM),
per JESD22-C101 (2)
500
All pins
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions
MIN
TYP
3.3
MAX
UNIT
VCC
Supply voltage
3.6
VI
Input voltage
VCC
VCC
0.7 VCC
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating temperature
4.4
TTL
CMOS
TTL
0.8
CMOS
0.2 VCC
Commercial range
70
40
85
Industrial range
Thermal Information
TUSB3410
THERMAL METRIC (1)
RHB (VQFN)
VF (LQFP)
UNIT
32 PINS
RJA
Junction-to-ambient thermal resistance
32.1
70.5
C/W
RJC(top)
Junction-to-case (top) thermal resistance
24.6
31.4
C/W
RJB
Junction-to-board thermal resistance
6.5
28.3
C/W
JT
Junction-to-top characterization parameter
0.2
2.2
C/W
JB
Junction-to-board characterization parameter
6.5
28.2
C/W
Junction-to-case (bottom) thermal resistance
24.6
31.4
C/W
RJC(bot)
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Specifications
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4.5
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Electrical Characteristics
TA = 25C, VCC = 3.3 V 5%, VSS = 0 V
PARAMETER
TEST CONDITIONS
TTL
TYP
MAX
VCC 0.5
UNIT
VOH
High-level output voltage
VOL
Low-level output voltage
VIT+
Positive threshold voltage
VIT
Negative threshold voltage
Vhys
Hysteresis (VIT+ VIT)
IIH
High-level input current
IIL
Low-level input current
IOZ
Output leakage current (Hi-Z)
IOL
Output low drive current
0.1
mA
IOH
Output high drive current
0.1
mA
ICC
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
IOH = 4 mA
MIN
VCC 0.5
0.5
IOL = 4 mA
0.5
1.8
VI = VIH
VI = VIH
VI = VIH
0.7 VCC
0.8
1.8
0.2 VCC
0.3
0.7
0.17 VCC
0.3 VCC
20
VI = VIH
1
20
VI = VIL
VI = VCC or VSS
Supply current (operating)
20
Serial data at 921.6 k
Supply current (suspended)
Clock duty cycle (1)
V
V
V
V
A
A
A
15
mA
200
100
ppm
50%
Jitter specification (1)
CI
Input capacitance
18
pF
CO
Output capacitance
10
pF
(1)
Applies to all clock outputs
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Specifications
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SLLS519I MARCH 2002 REVISED NOVEMBER 2015
4.6
4.6.1
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Timing and Switching Characteristics Information
Wakeup Timing (WAKEUP or RI/CP Transitions)
The TUSB3410 device can be brought out of the suspended state, or woken up, by a command from the
host. The TUSB3410 device also supports remote wakeup and can be awakened by either of two input
signals. A low pulse on the WAKEUP terminal or a low-to-high transition on the RI/CP terminal wakes up
the device.
NOTE
For reliable operation, either condition must persist for approximately 3-ms minimum, which
allows time for the crystal to power up because in the suspend mode, the crystal interface is
powered down. The state of the WAKEUP or RI/CP terminal is then sampled by the clock to
verify there was a valid wake-up event.
4.6.2
Reset Timing
There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 s.
At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the
reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 s of
the reset window. The third requirement is that, according to the USB specification, the device must be
ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must
come out of reset, load any pertinent data from the I2C EEPROM device, and transfer execution to the
application firmware if any is present. Because the latter two events can require significant time, the
amount of which can change from system to system, TI recommends having the device come out of reset
within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal must rise to
1.8 V within 30 ms.
These requirements are depicted in Figure 4-1. When using a 12-MHz crystal, the clock signal may take
several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need
to be elongated up to 10 ms or more to ensure that there is a 60-s overlap with a valid clock.
3.3 V
VCC
CLK
90%
RESET
1.8 V
1.2 V
0V
t
>60 s
100 s < RESET TIME
RESET TIME < 30 ms
Figure 4-1. Reset Timing
8
Specifications
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4.7
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Typical Characteristics
9.8
8.94
3V
9.79
8.92
3.3 V
9.78
8.9
9.77
9.76
9.75
8.86
Supply Current (mA)
Supply Current (mA)
8.88
8.84
8.82
8.8
8.78
9.74
9.73
9.72
9.71
9.7
9.69
8.76
9.68
9.67
8.74
9.66
8.72
9.65
8.7
2400
4800
7200 9600
19200
38400
57600
115200
230400
460800
9.64
2400
921600
4800
7200 9600
Baud Rate (bps)
19200
38400
57600
115200
230400
460800
921600
Baud Rate (bps)
C004
C005
Figure 4-2. Supply Current at 3 V
Figure 4-3. Supply Current at 3.3 V
10.64
10.63
3.6 V
10.62
10.61
10.6
Supply Current (mA)
10.59
10.58
10.57
10.56
10.55
10.54
10.53
10.52
10.51
10.5
10.49
10.48
2400
4800
7200 9600
19200
38400
57600
115200
230400
460800
921600
Baud Rate (bps)
C006
Figure 4-4. Supply Current at 3.6 V
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Specifications
TUSB3410, TUSB3410I
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
www.ti.com
5 Detailed Description
5.1
Overview
The TUSB3410 device provides bridging between a USB port and an enhanced UART serial port. The
TUSB3410 device contains all the necessary logic to communicate with the host computer using the USB
bus. It contains an 8052 microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the
host or from the external on-board memory through an I2C bus. It also contains 10K bytes of ROM that
allow the MCU to configure the USB port at boot time. The ROM code also contains an I2C bootloader. All
device functions, such as the USB command decoding, UART setup, and error reporting, are managed by
the internal MCU firmware under the auspices of the PC host.
The TUSB3410 device can be used to build an interface between a legacy serial peripheral device and a
PC with USB ports, such as a legacy-free PC. When configured, data flows from the host to the
TUSB3410 device through USB OUT commands and then out from the TUSB3410 device on the SOUT
line. Conversely, data flows into the TUSB3410 device on the SIN line and then into the host through USB
IN commands.
Out
SOUT
Host
(PC or On-The-Go
Dual-Role Device)
USB
Legacy
Serial
Peripheral
TUSB3410
In
SIN
Figure 5-1. Data Flow
10
Detailed Description
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5.2
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Functional Block Diagram
12 MHz
Clock
Oscillator
PLL and
Dividers
8052
Core
24 MHz
DP, DM
2 16-Bit
Timers
10K 8
ROM
USB
TxR
8
16K 8
RAM
4
Port 3
8
2K 8
SRAM
I 2C
Controller
P3.4
P3.3
P3.1
P3.0
I2C Bus
USB
Serial
Interface
Engine
CPU-I/F
Suspend/
Resume
DMA-1
DMA-3
8
8
UBM
USB Buffer
Manager
RTS
CTS
DTR
DSR
UART1
SIN
SOUT
TDM
Control
Logic
IR
Encoder
M
U
X
IR
Decoder
M
U
X
SOUT/IR_SOUT
SIN/IR_SIN
Figure 5-2. USB-to-Serial (Single Channel) Controller Block Diagram
5.3
Device Functional Modes
The TUSB3410 device controls its USB interface in response to USB commands, and this action is
independent of the serial port mode selected. On the other hand, the serial port can be configured in three
different modes.
As with any interface device, data movement is the main function of the TUSB3410 device, but typically
the initial configuration and error handling consume most of the support code. The following sections
describe the various modes the device can be used in and the means of configuring the device.
5.3.1
USB Interface Configuration
The TUSB3410 device contains onboard ROM microcode, which enables the MCU to enumerate the
device as a USB peripheral. The ROM microcode can also load application code into internal RAM from
either external memory through the I2C bus or from the host through the USB.
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Detailed Description
11
TUSB3410, TUSB3410I
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5.3.1.1
www.ti.com
External Memory Case
After reset, the TUSB3410 device is disconnected from the USB. Bit 7 (CONT) in the USBCTL register
(see Section 5.5.5.4) is cleared. The TUSB3410 device checks the I2C port for the existence of valid code;
if it finds valid code, then the device uploads the code from the external memory device into the RAM
program space. When loaded, the TUSB3410 device connects to the USB by setting the CONT bit; then,
enumeration and configuration are performed. This is the most likely use of the device.
5.3.1.2
Host Download Case
If the valid code is not found at the I2C port, then the TUSB3410 device connects to the USB by setting bit
7 (CONT) in the USBCTL register (see Section 5.5.5.4), and then an enumeration and default
configuration are performed. The host can download additional microcode into RAM to tailor the
application. Then, the MCU causes a disconnect and reconnect by clearing and setting the CONT bit,
which causes the TUSB3410 device to be re-enumerated with a new configuration.
5.3.2
USB Data Movement
From the USB perspective, the TUSB3410 device looks like a USB peripheral device. It uses endpoint
zero as its control endpoint, as do all USB peripherals. It also configures up to three input and three output
endpoints, although most applications use one bulk input endpoint for data in, one bulk output endpoint for
data out, and one interrupt endpoint for status updates. The USB configuration likely remains the same
regardless of the serial port configuration.
Most data is moved from the USB side to the UART side and from the UART side to the USB side using
on-chip DMA transfers. Some special cases may use programmed I/O under control of the MCU.
5.3.3
Serial Port Setup
The serial port requires a few control registers to be written to configure its operation. This configuration
likely remains the same regardless of the data mode used. These registers include the line control register
that controls the serial word format and the divisor registers that control the baud rate.
These registers are usually controlled by the host application.
5.3.4
Serial Port Data Modes
The serial port can be configured in three different, although similar, data modes: the RS-232 data mode,
the RS-485 data mode, and the IrDA data mode. Similar to the USB mode, when configured for a specific
application, it is unlikely that the mode would be changed. The different modes affect the timing of the
serial input and output or the use of the control signals. However, the basic serial-to-parallel conversion of
the receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. Some
features are available in all modes, but are only applicable in certain modes. For instance, software flow
control through Xoff/Xon characters can be used in all modes, but would usually only be used in RS-232
or IrDA mode because the RS-485 mode is half-duplex communication. Similarly, hardware flow control
through RTS/CTS (or DTR/DSR) handshaking is available in RS-232 or IrDA mode. However, this would
probably be used only in RS-232 mode, because in IrDA mode only the SIN and SOUT paths are optically
coupled.
5.3.4.1
RS-232 Data Mode
The default mode is called the RS-232 mode and is typically used for full duplex communication on SOUT
and SIN. In this mode, the modem control outputs (RTS and DTR) communicate to a modem or are
general outputs. The modem control inputs (CTS, DSR, DCD, and RI/CP) communicate to a modem or
are general inputs. Alternatively, RTS and CTS (or DTR and DSR) can throttle the data flow on SOUT and
SIN to prevent receive FIFO overruns. Finally, software flow control through Xoff/Xon characters can be
used for the same purpose (see Section 5.2).
This mode represents the most general-purpose applications, and the other modes are subsets of this
mode.
12
Detailed Description
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5.3.4.2
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
RS-485 Data Mode
The RS-485 mode is very similar to the RS-232 mode in that the SOUT and SIN formats remain the same.
Because RS-485 is a bus architecture, it is inherently a single duplex communication system. The
TUSB3410 device in RS-485 mode controls the RTS and DTR signals such that either can enable an RS485 driver or RS-485 receiver. When in RS-485 mode, the enable signals for transmitting are
automatically asserted whenever the DMA is set up for outbound data.
NOTE
The receiver can be left enabled while the driver is enabled to allow an echo if desired, but
when receive data is expected, the driver must be disabled. This precludes use of hardware
flow control, because this is a half-duplex operation, it would not be effective. Software flow
control is supported, but may be of limited value.
The RS-485 mode is enabled by setting bit 7 (485E) in the FCRL register (see Section 5.5.7.4), and bit 1
(RCVE) in the MCR register (see Section 5.5.7.6) allows the receiver to eavesdrop while in the RS-485
mode.
5.3.4.3
IrDA Data Mode
The IrDA mode encodes SOUT and decodes SIN in the manner prescribed by the IrDA standard, up to
115.2 kbps. Connection to an external IrDA transceiver is required. Communications is usually full duplex.
Generally, in an IrDA system, only the SOUT and SIN paths are connected so hardware flow control is
usually not an option. Software flow control is supported (see Section 5.2).
The IrDA mode is enabled by setting bit 6 (IREN) in the USBCTL register (see Section 5.5.5.4).
The IR encoder and decoder circuitry work with the UART to change the serial bit stream into a series of
pulses and back again. For every zero bit in the outbound serial stream, the encoder sends a low-to-highto-low pulse with the duration of 3/16 of a bit frame at the middle of the bit time. For every one bit in the
serial stream, the output remains low for the entire bit time.
The decoding process consists of receiving the signal from the IrDA receiver and converting it into a series
of zeroes and ones. As the converse to the encoder, the decoder converts a pulse to a zero bit and the
lack of a pulse to a one bit.
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SOUT
0
M
U
X
From
UART
SOUT
IR_TX
IR
Encoder
SOUT/IR_SOUT
Terminal
IREN (in
USBCTL
Register)
0
UART
BaudOut
Clock
M
U
X
SOFTSW (in
MODECNFG
Register)
TXCNTL (in
MODECNFG
Register)
0
M
U
1
3.556 MHz
CLKSLCT (in
MODECNFG
Register)
CLKOUT
Terminal
CLKOUTEN
(in
MODECNFG
Register)
3.3 V
0
To
UART
Receiver
SIN
M
U
X
1
IR_RX
IR
Decoder
SIN/IR_SIN
Terminal
Figure 5-3. RS-232 and IR Mode Select
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DB9
Connector
Transceivers
X1/CLKI
12 MHz
DTR
RTS
X2
RI/CP
DCD
DSR
CTS
Serial Port
3 2
SOUT
DP
DM
USB-0
SIN
TUSB3410
P3.0
P3.1
P3.3
GPIO Terminals for
Other Onboard
Control Function
P3.4
Figure 5-4. USB-to-Serial Implementation (RS-232)
X1/CLKI
12 MHz
RTS
RS-485 Bus
X2
SOUT
DTR
SIN
DP
DM
USB-0
TUSB3410
RS-485
Transceiver
2-Bit Time
1-Bit Max
SOUT
DTR
RTS
Receiver is Disabled if RCVE = 0
Figure 5-5. RS-485 Bus Implementation
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5.4
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Processor Subsystems
5.4.1
DMA Controller
5.4.1.1
Bulk Data I/O Using the EDB
The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer
parameters for IN and OUT transactions (IN and OUT are with respect to host). In this discussion, it is
assumed that:
The MCU initialized the EDBs
DMA-continuous mode is being used
Double buffering is being used
The X/Y toggle is controlled by the UBM
5.4.1.1.1 IN Transaction (TUSB3410 to Host)
1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA
registers:
DMACSR3: Defines the transaction time-out value.
DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode).
Once this register is set with EN = 1, the transfer starts.
2. The DMA transfers data from the UART to the X buffer. When a block of 64 bytes is transferred, the
DMA updates the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to
the UBM that the X buffer is ready to be transferred to host). The UBM starts X-buffer transfer to host
using the byte-count value in the input endpoint byte count register and toggles the X/Y bit. The DMA
continues transferring data from a device to Y buffer. At the end of the block transfer, the DMA updates
the byte count and sets NAK to 0 in the input endpoint byte count register (indicating to the UBM that
the Y buffer is ready to be transferred to host). The DMA continues the transfer from the device to
host, alternating between X and Y buffers without MCU intervention.
3. Transfer termination: The DMA/UBM continues the data transfer, alternating between the X and Y
buffers. Termination of the transfer can happen under the following conditions:
Stop Transfer: The host notifies the MCU (through control-end-point) to stop the transfer. Under
this condition, the MCU sets bit 7 (EN) to 0 in the DMACDR register.
Partial Packet: The device receiver has no data to be transferred to host. Under this condition, the
byte-count value is less than 64 when the transaction timer time-out occurs. When the DMA detects
this condition, it sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, updates
the byte count and NAK bit in the input endpoint byte count register, and interrupts the MCU. The
UBM transfers the partial packet to host.
Buffer Overrun: The host is busy, X and Y buffers are full (X-NAK = 0 and Y-NAK = 0), and the
DMA cannot write to these buffers. The transaction time-out stops the DMA transfer, the DMA sets
bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 1 in the DMACSR3 register, and interrupts the MCU.
UART Error Condition: When receiving from a UART, a receiver-error condition stops the DMA
and sets bit 1 (TXFT) to 1 and bit 0 (OVRUN) to 0 in the DMACSR3 register, but the EN bit remains
set at 1. Therefore, the DMA does not interrupt the MCU. However, the UART generates a status
interrupt, notifying the MCU that an error condition has occurred.
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5.4.1.1.2 OUT Transaction (Host to TUSB3410)
1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA
registers:
DMACSR1: Provides an indication of a partial packet.
DMACDR1: Defines the output endpoint being used, and the DMA mode of operation (continuous
mode). When the EN bit is set to 1 in this register, the transfer starts.
2. The UBM transfers data from host to X buffer. When a block of 64 bytes is transferred, the UBM
updates the byte count and sets NAK to 1 in the output endpoint byte count register (indicating to DMA
that the X buffer is ready to be transferred to the UART). The DMA starts X buffer transfer using the
byte-count value in the output endpoint byte count register. The UBM continues transferring data from
host to Y buffer. At the end of the block transfer, the UBM updates the byte count and sets NAK to 1 in
the output endpoint byte count register (indicating to DMA that the Y buffer is ready to be transferred to
device). The DMA continues the transfer from the X and Y buffers to the device, alternating between X
and Y buffers without MCU intervention.
3. Transfer termination: The DMA/UBM continues the data transfer alternating between X and Y buffers.
The termination of the transfer can happen under the following conditions:
Stop Transfer: The host notifies the MCU (through control-end point) to stop the transfer. Under
this condition, the MCU sets EN to 0 in the DMACDR1 register.
Partial Packet: UBM receives a partial packet from host. Under this condition, the byte-count value
is less than 64. When the DMA detects this condition, it transfers the partial packet to the device,
sets PPKT to 1, updates NAK to 0 in the output endpoint byte count register and interrupts MCU.
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UART
5.4.2.1
UART Data Transfer
Figure 5-6 illustrates the data transfer between the UART and the host using the DMA controller and the
USB buffer manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit
and receive buffers). The UART channel has 64 bytes of double-buffer space (X and Y buffer). When the
DMA writes to the X buffer, the UBM reads from the Y buffer. Similarly, when the DMA reads from the X
buffer, the UBM writes to the Y buffer. The DMA channel is configured to operate in the continuous mode
(by setting bit 5 (CNT) in the DMACDR registers = 1). Once the MCU enables the DMA, data transfer
toggles between the UMB and the DMA without MCU intervention. See Section 5.4.1.1.1 for DMA
transfer-termination condition.
5.4.2.1.1 Receiver Data Flow
The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level
mark (HALT), which is set to 12 bytes, and the other is the low-level mark (RESUME), which is set to 4
bytes. When the HALT mark is reached, either the RTS terminal goes high or Xoff is transmitted
(depending on the auto setting). When the FIFO reaches the RESUME mark, then either the RTS terminal
goes low or Xon is transmitted.
Receiver
Halt on Error or Time-Out
64-Byte
Y-Buffer
RDR: 32-Byte FIFO
DMA
DMACDR3
SIN
64-Byte
X-Buffer
RTS/DTR = 1
or Xoff Transmitted
X/Y
Host
RTS/DTR = 0
or Xon Transmitted
USB
Buffer
Manager
Xoff/Xon
CTS/DTR = 1/0
64-Byte
Y-Buffer
Pause/Run
DMA
DMACDR1
SOUT
64-Byte
X-Buffer
TDR
Figure 5-6. Receiver and Transmitter Data Flow
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5.4.2.1.2 Hardware Flow Control
Figure 5-7 illustrates the connection necessary to achieve hardware flow control. The CTS and RTS
signals are provided for this purpose. Auto CTS and auto RTS (and Xon/Xoff) can be enabled and
disabled independently by programming the UART flow control register (FCRL).
TUSB3410
SIN
RTS
SOUT
CTS
External Device
SOUT
CTS
SIN
RTS
Figure 5-7. Auto Flow Control Interconnect
5.4.2.1.3 Auto RTS (Receiver Control)
In this mode, the RTS output terminal signals the receiver-FIFO status to an external device. The RTS
output signal is controlled by the high- and low-level marks of the FIFO. When the high-level mark is
reached, RTS goes high, signaling to an external sending device to halt its transfer. Conversely, when the
low-level mark is reached, RTS goes low, signaling to an external sending device to resume its transfer.
Data transfer from the FIFO to the X and Y buffer is performed by the DMA controller. See
Section 5.4.1.1.1 for DMA transfer-termination condition.
5.4.2.1.4 Auto CTS (Transmitter Control)
In this mode, the CTS input terminal controls the transfer from internal buffer (X or Y) to the TDR. When
the DMA controller transfers data from the Y buffer to the TDR and the CTS input terminal goes high, the
DMA controller is suspended until CTS goes low. Meanwhile, the UBM is transferring data from the host to
the X buffer. When CTS goes low, the DMA resumes the transfer. Data transfer continues alternating
between the X and Y buffers, without MCU intervention. See Section 5.4.1.1.2 for DMA transfertermination condition.
5.4.2.1.5 Xon/Xoff Receiver Flow Control
To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows:
MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the Xon/Xoff bytes are transmitted to an external
sending device to control the transmission of the device. When the high-level mark (of the FIFO) is
reached, the Xoff byte is transmitted, signaling to an external sending device to halt its transfer.
Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external
sending device to resume its transfer. The data transfer from the FIFO to X and Y buffer is performed by
the DMA controller.
5.4.2.1.6 Xon/Xoff Transmit Flow Control
To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows:
MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the incoming data are compared to the XON and
XOFF registers. If a match to XOFF is detected, the DMA is paused. If a match to XON is detected, the
DMA resumes. Meanwhile, the UBM is transferring data from the host to the X-buffer. The MCU does not
switch the buffers unless the Y buffer is empty and the X-buffer is full. When Xon is detected, the DMA
resumes the transfer.
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I2C Port
5.4.3
5.4.3.1
Random-Read Operation
A random read requires a dummy byte-write sequence to load in the data word address. Once the deviceaddress word and the data-word address are clocked out and acknowledged by the device, the MCU
starts a current-address sequence. The following describes the sequence of events to accomplish this
transaction.
5.4.3.1.1 Device Address + EPROM [High Byte]
1. The MCU clears bit 1 (SRD) within the I2CSTA register. This forces the I2C controller not to generate a
stop condition after the contents of the I2CDAI register are received.
2. The MCU clears bit 0 (SWR) within the I2CSTA register. This forces the I2C controller not to generate
a stop condition after the contents of the I2CDAO register are transmitted.
3. The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation)
4. The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the
transfer on the SDA line).
5. Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing data to the
I2CDAO register.
6. The contents of the I2CADR register are transmitted to EEPROM (preceded by start condition on
SDA).
7. The contents of the I2CDAO register are transmitted to EEPROM (EPROM address).
8. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
has been transmitted.
9. A stop condition is not generated.
5.4.3.1.2 EPROM [Low Byte]
1. The MCU writes the low byte of the EEPROM address into the I2CDAO register.
2. Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO
register.
3. The contents of the I2CDAO register are transmitted to the device (EEPROM address).
4. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
has been transmitted.
5. This completes the dummy write operation. At this point, the EEPROM address is set and the MCU
can do either a single- or a sequential-read operation.
5.4.3.2
Current-Address Read Operation
When the EEPROM address is set, the MCU can read a single byte by executing the following steps:
1. The MCU sets bit 1 (SRD) in the I2CSTA register to 1. This forces the I2C controller to generate a stop
condition after the I2CDAI-register contents are received.
2. The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).
3. The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on SDA line).
4. Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).
5. The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).
6. The data from EEPROM are latched into the I2CDAI register (stop condition is transmitted).
7. Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that the data are available.
8. The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
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Sequential-Read Operation
When the EEPROM address is set, the MCU can execute a sequential read operation by executing the
following steps (this example illustrates a 32-byte sequential read):
5.4.3.3.1 Device Address
1. The MCU clears bit 1 (SRD) in the I2CSTA register. This forces the I2C controller to not generate a
stop condition after the I2CDAI register contents are received.
2. The MCU writes the device address (bit 0 (R/W) = 1) to the I2CADR register (read operation).
3. The MCU writes a dummy byte to the I2CDAO register (this starts the transfer on the SDA line).
4. Bit 7 (RXF) in the I2CSTA register is cleared (RX is empty).
5. The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).
5.4.3.3.2 N-Byte Read (31 Bytes)
1.
2.
3.
4.
The data from the device is latched into the I2CDAI register (stop condition is not transmitted).
Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.
The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
This operation repeats 31 times.
5.4.3.3.3 Last-Byte Read (Byte 32)
1. MCU sets bit 1 (SRD) in the I2STA register to 1. This forces the I2C controller to generate a stop
condition after the I2CDAI register contents are received.
2. The data from the device is latched into the I2CDAI register (stop condition is transmitted).
3. Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available.
4. The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register.
5.4.3.4
Byte-Write Operation
The byte-write operation involves three phases: device address + EPROM [high byte] phase, EPROM [low
byte] phase, and EPROM [DATA] phase. The following describes the sequence of events to accomplish
the byte-write transaction.
5.4.3.4.1 Device Address + EPROM [High Byte]
1. The MCU sets clears the SWR bit in the I2CSTA register. This forces the I2C controller to not generate
a stop condition after the contents of the I2CDAO register are transmitted.
2. The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation).
3. The MCU writes the high byte of the EEPROM address into the I2CDAO register (this starts the
transfer on the SDA line).
4. Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
5. The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).
6. The contents of the I2CDAO register are transmitted to the device (EEPROM high address).
7. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
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5.4.3.4.2 EPROM [Low Byte]
1.
2.
3.
4.
The MCU writes the low byte of the EEPROM address into the I2CDAO register.
Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy).
The contents of the I2CDAO register are transmitted to the device (EEPROM address).
Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
5.4.3.4.3 EPROM [DATA]
1. The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to generate a stop
condition after the contents of the I2CDAO register are transmitted.
2. The data to be written to the EPROM is written by the MCU into the I2CDAO register.
3. Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
4. The contents of the I2CDAO register are transmitted to the device (EEPROM data).
5. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
6. The I2C controller generates a stop condition after the contents of the I2CDAO register are transmitted.
5.4.3.5
Page-Write Operation
The page-write operation is initiated in the same way as byte write, with the exception that a stop
condition is not generated after the first EPROM [DATA] is transmitted. The following describes the
sequence of writing 32 bytes in page mode.
5.4.3.5.1 Device Address + EPROM [High Byte]
1. The MCU clears bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to not generate a
stop condition after the contents of the I2CDAO register are transmitted.
2. The MCU writes the device address (bit 0 (R/W) = 0) to the I2CADR register (write operation).
3. The MCU writes the high byte of the EEPROM address into the I2CDAO register.
4. Bit 3 (TXE) in the I2CSTA register is cleared (indicating busy).
5. The contents of the I2CADR register are transmitted to the device (preceded by start condition on
SDA).
6. The contents of the I2CDAO register are transmitted to the device (EEPROM address).
7. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
5.4.3.5.2 EPROM [Low Byte]
1.
2.
3.
4.
22
The MCU writes the low byte of the EEPROM address into the I2CDAO register.
Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
The contents of the I2CDAO register are transmitted to the device (EEPROM address).
Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
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5.4.3.5.3 EPROM [DATA]31 Bytes
1.
2.
3.
4.
The data to be written to the EEPROM are written by the MCU into the I2CDAO register.
Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
The contents of the I2CDAO register are transmitted to the device (EEPROM data).
Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
5. This operation repeats 31 times.
5.4.3.5.4 EPROM [DATA]Last Byte
1. The MCU sets bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to generate a stop
condition after the contents of the I2CDAO register are transmitted.
2. The MCU writes the last date byte to be written to the EEPROM, into the I2CDAO register.
3. Bit 3 (TXE) in the I2CSTA register is cleared (indicates busy).
4. The contents of the I2CDAO register are transmitted to EEPROM (EEPROM data).
5. Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register
contents have been transmitted.
6. The I2C controller generates a stop condition after the contents of the I2CDAO register are transmitted.
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5.5
5.5.1
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Memory
MCU Memory Map
Figure 5-8 illustrates the MCU memory map under boot and normal operation.
NOTE
The internal 256 bytes of RAM are not shown, because they are assumed to be in the
standard 8052 location (0000h to 00FFh). The shaded areas represent the internal
ROM/RAM.
When bit 0 (SDW) of the ROMS register is 0 (boot mode)
The 10K ROM is mapped to address (0x00000x27FF) and is duplicated in location
(0x80000xA7FF) in code space. The internal 16K RAM is mapped to address range
(0x00000x3FFF) in data space. Buffers, MMR, and I/O are mapped to address range
(0xF8000xFFFF) in data space.
When bit 0 (SDW) is 1 (normal mode)
The 10K ROM is mapped to (0x80000xA7FF) in code space. The internal 16K RAM is
mapped to address range (0x00000x3FFF) in code space. Buffers, MMR, and I/O are
mapped to address range (0xF8000xFFFF) in data space.
CODE
Boot Mode (SDW = 0)
XDATA
Normal Mode (SDW = 1)
CODE
XDATA
0000h
10K Boot ROM
(16K)
Read/Write
16K
Code RAM
Read Only
27FFh
3FFFh
8000h
10K Boot ROM
10K Boot ROM
A7FFh
F800h
FF7Fh
FF80h
FFFFh
2K Data
2K Data
MMR
MMR
Figure 5-8. MCU Memory Map
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5.5.2
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Registers
5.5.2.1
Miscellaneous Registers
5.5.2.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)
This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set
on power-on reset only). In addition, this register provides the device revision number and the ROM/RAM
configuration.
7
ROA
R/O
BIT
NAME
SDW
41
RSVD
65
S[1:0]
ROA
6
S1
R/O
5
S0
R/O
4
RSVD
R/O
3
RSVD
R/O
2
RSVD
R/O
1
RSVD
R/O
0
SDW
R/W
RESET
FUNCTION
This bit enables/disables boot ROM. (Shadow the ROM).
SDW = 0
When clear, the MCU executes from the 10K boot ROM space. The boot ROM appears in two
locations: 0000h and 8000h. The 16K RAM is mapped to XDATA space; therefore, a read/write
operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU
0
cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset.
SDW = 1
When set by the MCU, the 10K boot ROM maps to location 8000h, and the 16K RAM is mapped
to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the
write operation is disabled (no write operation is possible in code space).
No effect These bits are always read as 0000b.
Code space size. These bits define the ROM or RAM code-space size (bit 7 (ROA) defines ROM or RAM).
These bits are permanently set to 10b, indicating 16K bytes of code space, and are not affected by reset (see
Table 5-1).
No effect 00 = 4K bytes code space size
01 = 8K bytes code space size
10 = 16K bytes code space size
11 = 32K bytes code space size
ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is
permanently set to 1, indicating the code space is RAM, and is not affected by reset (see Table 5-1).
No effect
ROA = 0
Code space is ROM
ROA = 1
Code space is RAM
Table 5-1. ROM and RAM Size Definition Table
ROMS REGISTER
ROA
S1
S0
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1 (1)
1 (1)
0 (1)
1
1
1
(1)
BOOT ROM
RAM CODE
ROM CODE
None
None
None
None
10K
10K
10K (1)
10K
None
None
None
None
4K
8K
16K (1)
32K (reserved)
4K
8K
16K (reserved)
32K (reserved)
None
None
None (1)
None
This is the hardwired setting.
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5.5.2.1.2 Boot Operation (MCU Firmware Loading)
Because the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must
be loaded from an external source. Two sources are available for booting: one from an external serial
EEPROM connected to the I2C bus and the other from the host through the USB. On device reset, bit 0
(SDW) in the ROMS register (see Section 5.5.2.1.1) and bit 7 (CONT) in the USBCTL register (see
Section 5.5.5.4) are cleared. This configures the memory space to boot mode (see Table 5-3) and keeps
the device disconnected from the host. The first instruction is fetched from location 0000h (which is in the
10K ROM). The 16K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from
an external EEPROM and tests whether it contains the code (by testing for boot signature). If it contains
the code, then the MCU reads from EEPROM and writes to the 16K RAM in XDATA space. If it does not
contain the code, then the MCU proceeds to boot from the USB.
When the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register. This switches the memory
map to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from
location 0000h. When the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register. This
connects the device to the USB and results in normal USB device enumeration.
5.5.2.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)
A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128
ms, then the WDT counter resets the MCU (see Figure 5-9). The watchdog timer is enabled by default
and can be disabled by writing a pattern of 101010b into the WDD[5:0] bits. The 1-ms clock for the
watchdog timer is generated from the SOF pulses. Therefore, for the watchdog timer to count, bit 7
(CONT) in the USBCTL register (see Section 5.5.5.4) must be set.
7
WDD0
R/W
6
WDR
R/C
BIT
NAME
RESET
WDT
51
WDD[5:1]
00000
WDR
WDD0
26
Detailed Description
5
WDD5
R/W
4
WDD4
R/W
3
WDD3
R/W
2
WDD2
R/W
1
WDD1
R/W
0
WDT
W/O
FUNCTION
MCU must write a 1 to this bit to prevent the watchdog timer from resetting the MCU. If the MCU does
not write a 1 in a period of 128 ms, the watchdog timer resets the device. Writing a 0 has no effect on
the watchdog timer. (The watchdog timer is a 7-bit counter using a 1-ms CLK.) This bit is read as 0.
These bits disable the watchdog timer. For the timer to be disabled these bits must be set to 10101b
and bit 7 (WDD0) must also be set to 0. If any other pattern is present, then the watchdog timer is in
operation.
Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog
timer reset.
WDR = 0
A power-up reset occurred
WDR = 1
A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0
has no effect.
This bit is one of the six disable bits for the watchdog timer. This bit must be cleared in order for the
watchdog timer to be disabled.
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Buffers + I/O RAM Map
The address range from F800h to FFFFh (2K bytes) is reserved for data buffers, setup packet, endpoint
descriptors block (EDB), and all I/O. There are 128 locations reserved for memory-mapped registers
(MMR). Table 5-2 represents the XDATA space allocation and access restriction for the DMA, USB buffer
manager (UBM), and MCU.
Table 5-2. XDATA Space
DESCRIPTION
ADDRESS RANGE
UBM ACCESS
DMA ACCESS
MCU
ACCESS
Internal MMRs
(Memory-Mapped Registers)
FFFFhFF80h
No
(Only EDB-0)
No
(only data register and EDB-0)
Yes
EDB
(Endpoint Descriptors Block)
FF7FhFF08h
Only for EDB update
Only for EDB update
Yes
Setup Packet
FF07hFF00h
Yes
No
Yes
Input Endpoint-0 Buffer
FEFFhFEF8h
Yes
Yes
Yes
Output Endpoint-0 Buffer
FEF7hFEF0h
Yes
Yes
Yes
Data Buffers
FEEFhF800h
Yes
Yes
Yes
Table 5-3. Memory-Mapped Registers Summary
(XDATA Range = FF80h FFFFh)
ADDRESS
REGISTER
DESCRIPTION
FFFFh
FUNADR
Function address register
FFFEh
USBSTA
USB status register
FFFDh
USBMSK
USB interrupt mask register
FFFCh
USBCTL
USB control register
FFFBh
MODECNFG
Mode configuration register
FFFAhFFF4h
Reserved
FFF3h
I2CADR
I2C-port address register
FFF2h
I2CDATI
I2C-port data input register
FFF1h
I2CDATO
I2C-port data output register
FFF0h
I2CSTA
I2C-port status register
FFEFh
SERNUM7
Serial number byte 7 register
FFEEh
SERNUM6
Serial number byte 6 register
FFEDh
SERNUM5
Serial number byte 5 register
FFECh
SERNUM4
Serial number byte 4 register
FFEBh
SERNUM3
Serial number byte 3 register
FFEAh
SERNUM2
Serial number byte 2 register
FFE9h
SERNUM1
Serial number byte 1 register
FFE8h
SERNUM0
Serial number byte 0 register
Reserved
FFE5h
DMACSR3
DMA-3: Control and status register
FFE4h
DMACDR3
DMA-3: Channel definition register
FFE7hFFE6h
FFE3hFFE2h
Reserved
FFE1h
DMACSR1
DMA-1: Control and status register
FFE0h
DMACDR1
DMA-1: Channel definition register
Reserved
FFABh
MASK
UART: Interrupt mask register
FFAAh
XOFF
UART: Xoff register
FFA9h
XON
UART: Xon register
FFDFhFFACh
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Table 5-3. Memory-Mapped Registers Summary
(XDATA Range = FF80h FFFFh) (continued)
ADDRESS
REGISTER
DESCRIPTION
FFA8h
DLH
UART: Divisor high-byte register
FFA7h
DLL
UART: Divisor low-byte register
FFA6h
MSR
UART: Modem status register
FFA5h
LSR
UART: Line status register
FFA4h
MCR
UART: Modem control register
FFA3h
FCRL
UART: Flow control register
FFA2h
LCR
UART: Line control registers
FFA1h
TDR
UART: Transmitter data registers
FFA0h
RDR
UART: Receiver data registers
FF9Eh
PUR_3
GPIO: Pullup register for port 3
Reserved
FF93h
WDCSR
Watchdog timer control and status register
FF92h
VECINT
Vector interrupt register
FF91h
Reserved
FF90h
ROMS
ROM shadow configuration register
FF9DhFF94h
FF8FhFF84h
Reserved
FF83h
OEPBCNT_0
Output endpoint_0: Byte count register
FF82h
OEPCNFG_0
Output endpoint_0: Configuration register
FF81h
IEPBCNT_0
Input endpoint_0: Byte count register
FF80h
IEPCNFG_0
Input endpoint_0: Configuration register
Table 5-4. EDB Memory Locations
ADDRESS
FF7FhFF60h
28
REGISTER
DESCRIPTION
Reserved
FF5Fh
IEPSIZXY_3
Input endpoint_3: X-Y buffer size
FF5Eh
IEPBCTY_3
Input endpoint_3: Y-byte count
FF5Dh
IEPBBAY_3
Input endpoint_3: Y-buffer base address
FF5Ch
Reserved
FF5Bh
Reserved
FF5Ah
IEPBCTX_3
Input endpoint_3: X-byte count
FF59h
IEPBBAX
Input endpoint_3: X-buffer base address
FF58h
IEPCNF_3
Input endpoint_3: Configuration
FF57h
IEPSIZXY_2v
Input endpoint_2: X-Y buffer size
FF56h
IEPBCTY_2
Input endpoint_2: Y-byte count
FF55h
IEPBBAY_2
Input endpoint_2: Y-buffer base address
FF54h
Reserved
FF53h
Reserved
FF52h
IEPBCTX_2
Input endpoint_2: X-byte count
FF51h
IEPBBAX_2
Input endpoint_2: X-buffer base address
FF50h
IEPCNF_2
Input endpoint_2: Configuration
FF4Fh
IEPSIZXY_1
Input endpoint_1: X-Y buffer size
FF4Eh
IEPBCTY_1
Input endpoint_1: Y-byte count
FF4Dh
IEPBBAY_1
Input endpoint_1: Y-buffer base address
FF4Ch
Reserved
FF4Bh
Reserved
Detailed Description
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Table 5-4. EDB Memory Locations (continued)
ADDRESS
REGISTER
DESCRIPTION
FF4Ah
IEPBCTX_1
Input endpoint_1: X-byte count
FF49h
IEPBBAX_1
Input endpoint_1: X-buffer base address
FF48h
IEPCNF_1
Input endpoint_1: Configuration
FF47h
FF20h
Reserved
FF1Fh
OEPSIZXY_3
Output endpoint_3: X-Y buffer size
FF1Eh
OEPBCTY_3
Output endpoint_3: Y-byte count
FF1Dh
OEPBBAY_3
Output endpoint_3: Y-buffer base address
Reserved
FF1Ah
OEPBCTX_3
Output endpoint_3: X-byte count
FF19h
OEPBBAX_3
Output endpoint_3: X-buffer base address
FF18h
OEPCNF_3
Output endpoint_3: Configuration
FF17h
OEPSIZXY_2
Output endpoint_2: X-Y buffer size
FF16h
OEPBCTY_2
Output endpoint_2: Y-byte count
FF15h
OEPBBAY_2
Output endpoint_2: Y-buffer base address
Reserved
FF12h
OEPBCTX_2
Output endpoint_2: X-byte count
FF11h
OEPBBAX_2
Output endpoint_2: X-buffer base address
FF10h
OEPCNF_2
Output endpoint_2: Configuration
FF0Fh
OEPSIZXY_1
Output endpoint_1: X-Y buffer size
FF0Eh
OEPBCTY_1
Output endpoint_1: Y-byte count
FF0Dh
OEPBBAY_1
Output endpoint_1: Y-buffer base address
Reserved
FF0Ah
OEPBCTX_1
Output endpoint_1: X-byte count
FF09h
OEPBBAX_1
Output endpoint_1: X-buffer base address
FF08h
OEPCNF_1
Output endpoint_1: Configuration
FF07h
FF00h
(8 bytes)
Setup packet block
FEFFh
FEF8h
(8 bytes)
Input endpoint_0 buffer
FEF7h
FEF0h
(8 bytes)
Output endpoint_0 buffer
FEEFh
TOPBUFF
Top of buffer space
FF1BhFF1Ch
FF14hFF13h
FF0ChFF0Bh
F800h
Buffer space
STABUFF
Start of buffer space
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Endpoint Descriptor Block (EDB1 to EDB3)
Data transfers between the USB, the MCU, and external devices that are defined by an endpoint
descriptor block (EDB). Three input and three output EDBs are provided. With the exception of EDB-0 (I/O
endpoint-0), all EDBs are located in SRAM as per Table 5-3. Each EDB contains information describing
the X- and Y-buffers. In addition, each EDB provides general status information.
Table 5-5 describes the EDB entries for EDB1 to EDB3. EDB0 registers are described in Table 5-6.
Table 5-5. Endpoint Registers and Offsets in RAM (n = 1 to 3)
OFFSET
ENTRY NAME
DESCRIPTION
07
EPSIZXY_n
I/O endpoint_n: X/Y-buffer size
06
EPBCTY_n
I/O endpoint_n: Y-byte count
05
EPBBAY_n
I/O endpoint_n: Y-buffer base address
04
SPARE
Not used
03
SPARE
Not used
02
EPBCTX_n
I/O endpoint_n: X-byte count
01
EPBBAX_n
I/O endpoint_n: X-buffer base address
00
EPCNF_n
I/O endpoint_n: Configuration
Table 5-6. Endpoint Registers
Base Addresses
BASE
ADDRESS
30
Detailed Description
DESCRIPTION
FF08h
Output endpoint 1
FF10h
Output endpoint 2
FF18h
Output endpoint 3
FF48h
Input endpoint 1
FF50h
Input endpoint 2
FF58h
Input endpoint 3
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OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h)
7
UBME
R/W
6
ISO=0
R/W
BIT
NAME
RESET
10
RSV
USBIE
5
TOGLE
R/W
4
DBUF
R/W
3
STALL
R/W
2
USBIE
R/W
1
RSV
R/W
0
RSV
R/W
FUNCTION
Reserved = 0
USB interrupt enable on transaction completion. Set/cleared by the MCU.
USBIE = 0
No interrupt on transaction completion
USBIE = 1
Interrupt on transaction completion
USB stall condition indication. Set/cleared by the MCU.
3
STALL
STALL = 0
No stall
STALL = 1
USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is
cleared by the MCU.
Double-buffer enable. Set/cleared by the MCU.
4
DBUF
DBUF = 0
Primary buffer only (X-buffer only)
TOGLE
DBUF = 1
USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.
Toggle bit selects buffer
ISO
ISO = 0
UBME
Nonisochronous transfer. This bit must be cleared by the MCU because only nonisochronous
transfer is supported.
USB buffer manager (UBM) enable/disable bit. Set/cleared by the MCU.
5.5.4.2
UBME = 0
UBM cannot use this endpoint
UBME = 1
UBM can use this endpoint
OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
7
A10
R/W
6
A9
R/W
5
A8
R/W
4
A7
R/W
3
A6
R/W
2
A5
R/W
1
A4
R/W
0
A3
R/W
BIT
NAME
RESET
FUNCTION
70
A[10:3]
A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the
MCU. The UBM or DMA uses this value as the start-address of a given transaction. Note that the UBM or
DMA does not change this value at the end of a transaction.
5.5.4.3
OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2)
7
NAK
R/W
BIT
6
C6
R/W
NAME
5
C5
R/W
4
C4
R/W
RESET
3
C3
R/W
2
C2
R/W
1
C1
R/W
0
C0
R/W
FUNCTION
60
C[6:0]
X-buffer byte count:
X000.0000b Count = 0
X000.0001b Count = 1 byte
:
:
X011.1111b Count = 63 bytes
X100.0000b Count = 64 bytes
Any value 100.0001b may result in unpredictable results.
NAK
NAK = 0 No valid data in buffer. Ready for host OUT
NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)
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5.5.4.4
OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
7
A10
R/W
6
A9
R/W
BIT
NAME
RESET
70
A[10:3]
5.5.4.5
BIT
5
A8
R/W
4
A7
R/W
3
A6
R/W
2
A5
R/W
1
A4
R/W
FUNCTION
A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by
the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM
or DMA does not change this value at the end of a transaction.
6
C6
R/W
NAME
5
C5
R/W
4
C4
R/W
RESET
3
C3
R/W
2
C2
R/W
1
C1
R/W
60
C[6:0]
NAK
NAK = 0 No valid data in buffer. Ready for host OUT
NAK = 1 Buffer contains a valid packet from host (gives NAK response to Host OUT request)
OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
7
RSV
R/W
BIT
0
C0
R/W
FUNCTION
Y-byte count:
X000.0000b Count = 0
X000.0001b Count = 1 byte
:
:
X011.1111b Count = 63 bytes
X100.0000b Count = 64 bytes
Any value 100.0001b may result in unpredictable results.
5.5.4.6
0
A3
R/W
OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
7
NAK
R/W
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6
S6
R/W
NAME
5
S5
R/W
RESET
4
S4
R/W
3
S3
R/W
2
S2
R/W
0
S0
R/W
FUNCTION
60
S[6:0]
X- and Y-buffer size:
0000.0000b Size = 0
0000.0001b Size = 1 byte
:
:
0011.1111b Size = 63 bytes
0100.0000b Size = 64 bytes
Any value 100.0001b may result in unpredictable results.
RSV
Reserved = 0
Detailed Description
1
S1
R/W
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IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h)
7
UBME
R/W
6
ISO=0
R/W
BIT
NAME
RESET
10
RSV
USBIE
5
TOGLE
R/W
4
DBUF
R/W
3
STALL
R/W
2
USBIE
R/W
1
RSV
R/W
0
RSV
R/W
FUNCTION
Reserved = 0
USB interrupt enable on transaction completion
USBIE = 0
No interrupt on transaction completion
USBIE = 1
Interrupt on transaction completion
USB stall condition indication. Set by the UBM but can be set/cleared by the MCU.
3
STALL
STALL = 0
No stall
STALL = 1
USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is
cleared automatically.
Double buffer enable
4
DBUF
TOGLE
ISO
UBME
DBUF = 0
Primary buffer only (X-buffer only)
DBUF = 1
Toggle bit selects buffer
USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1
ISO = 0
Nonisochronous transfer. This bit must be cleared by the MCU because only nonisochronous
transfer is supported.
UBM enable/disable bit. Set/cleared by the MCU
5.5.4.8
UBME = 0
UBM cannot use this endpoint
UBME = 1
UBM can use this endpoint
IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
7
A10
R/W
6
A9
R/W
5
A8
R/W
4
A7
R/W
3
A6
R/W
2
A5
R/W
1
A4
R/W
0
A3
R/W
BIT
NAME
RESET
FUNCTION
70
A[10:3]
A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the
MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM
or DMA does not change this value at the end of a transaction.
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IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2)
7
NAK
R/W
BIT
6
C6
R/W
NAME
5
C5
R/W
4
C4
R/W
RESET
3
C3
R/W
2
C2
R/W
1
C1
R/W
0
C0
R/W
1
A4
R/W
0
A3
R/W
FUNCTION
60
C[6:0]
X-Buffer byte count:
X000.0000b Count = 0
X000.0001b Count = 1 byte
:
:
X011.1111b Count = 63 bytes
X100.0000b Count = 64 bytes
Any value 100.0001b may result in unpredictable results.
NAK
NAK = 0 Buffer contains a valid packet for host-IN transaction
NAK = 1 Buffer is empty (gives NAK response to host-IN request)
5.5.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
7
A10
R/W
BIT
70
34
NAME
A[10:3]
6
A9
R/W
5
A8
R/W
4
A7
R/W
3
A6
R/W
2
A5
R/W
RESET
FUNCTION
A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by the
MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM
or DMA does not change this value at the end of a transaction.
Detailed Description
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5.5.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
7
NAK
R/W
BIT
6
C6
R/W
NAME
5
C5
R/W
4
C4
R/W
RESET
3
C3
R/W
2
C2
R/W
1
C1
R/W
0
C0
R/W
1
S1
R/W
0
S0
R/W
FUNCTION
60
C[6:0]
Y-byte count:
X000.0000b Count = 0
X000.0001b Count = 1 byte
:
:
X011.1111b Count = 63 bytes
X100.0000b Count = 64 bytes
Any value 100.0001b may result in unpredictable results.
NAK
NAK = 0 Buffer contains a valid packet for host-IN transaction
NAK = 1 Buffer is empty (gives NAK response to host-IN request)
5.5.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
7
RSV
R/W
BIT
6
S6
R/W
NAME
5
S5
R/W
4
S4
R/W
RESET
3
S3
R/W
2
S2
R/W
FUNCTION
60
S[6:0]
X- and Y-buffer size:
0000.0000b Size = 0
0000.0001b Size = 1 byte
:
:
0011.1111b Size = 63 bytes
0100.0000b Size = 64 bytes
Any value 100.0001b may result in unpredictable results.
RSV
Reserved = 0
5.5.4.13 Endpoint-0 Descriptor Registers
Unlike registers EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described
by a set of four registers (two for output and two for input). The registers and their respective addresses,
used for EDB-0 description, are defined in Table 5-7. EDB-0 has no buffer base-address register, because
these addresses are hardwired to FEF8h and FEF0h. Note that the bit positions have been preserved to
provide consistency with EDB-n (n = 1 to 3).
Table 5-7. Input/Output EDB-0 Registers
ADDRESS
REGISTER NAME
DESCRIPTION
FF83h
OEPBCNT_0
Output endpoint_0: Byte count
register
FF82h
OEPCNFG_0
Output endpoint_0: Configuration
register
FF81h
IEPBCNT_0
Input endpoint_0: Byte count
register
FF80h
IEPCNFG_0
Input endpoint_0: Configuration
register
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BUFFER BASE
ADDRESS
FEF0h
FEF8h
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5.5.4.13.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h)
7
UBME
R/W
6
RSV
R/O
BIT
NAME
RESET
10
RSV
USBIE
5
TOGLE
R/O
4
RSV
R/O
3
STALL
R/W
2
USBIE
R/W
1
RSV
R/O
0
RSV
R/O
FUNCTION
Reserved = 0
USB interrupt enable on transaction completion. Set/cleared by the MCU.
USBIE = 0
No interrupt
USBIE = 1
Interrupt on transaction completion
USB stall condition indication. Set/cleared by the MCU
3
STALL
STALL = 0
No stall
STALL = 1
USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared
automatically by the next setup transaction.
RSV
Reserved = 0
TOGLE
USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.
RSV
Reserved = 0
UBME
UBM enable/disable bit. Set/cleared by the MCU
UBME = 0
UBM cannot use this endpoint
UBME = 1
UBM can use this endpoint
5.5.4.13.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h)
7
NAK
R/W
BIT
6
RSV
R/O
5
RSV
R/O
NAME RESET
4
RSV
R/O
3
C3
R/W
1
C1
R/W
0
C0
R/W
FUNCTION
30
C[3:0]
0h
Byte count:
0000b Count = 0
:
:
0111b Count = 7
1000b Count = 8
1001b to 1111b are reserved. (If used, they default to 8)
64
RSV
Reserved = 0
NAK
NAK = 0
NAK = 1
36
2
C2
R/W
Detailed Description
Buffer contains a valid packet for host-IN transaction
Buffer is empty (gives NAK response to host-IN request)
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5.5.4.13.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h)
7
UBME
R/W
6
RSV
R/O
BIT
NAME
RESET
10
RSV
USBIE
5
TOGLE
R/O
4
RSV
R/O
3
STALL
R/W
2
USBIE
R/W
1
RSV
R/O
0
RSV
R/O
FUNCTION
Reserved = 0
USB interrupt enable on transaction completion. Set/cleared by the MCU.
USBIE = 0
No interrupt on transaction completion
USBIE = 1
Interrupt on transaction completion
USB stall condition indication. Set/cleared by the MCU
3
STALL
STALL = 0
No stall
STALL = 1
USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is
cleared automatically.
RSV
Reserved = 0
TOGLE
USB \toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.
RSV
Reserved = 0
UBME
UBM enable/disable bit. Set/cleared by the MCU
UBME = 0
UBM cannot use this endpoint
UBME = 1
UBM can use this endpoint
5.5.4.13.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h)
7
NAK
R/W
BIT
6
RSV
R/O
5
RSV
R/O
4
RSV
R/O
NAME RESET
3
C3
R/O
2
C2
R/O
1
C1
R/O
0
C0
R/O
FUNCTION
30
C[3:0]
0h
Byte count:
0000b Count = 0
:
:
0111b Count = 7
1000b Count = 8
1001b to 1111b are reserved.
64
RSV
Reserved = 0
NAK
NAK = 0
NAK = 1
No valid data in buffer. Ready for host OUT
Buffer contains a valid packet from host (gives NAK response to host-OUT request).
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5.5.5
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USB Registers
5.5.5.1
FUNADR: Function Address Register (Addr:FFFFh)
This register contains the device function address.
7
RSV
R/O
BIT
6
FA6
R/W
NAME
5
FA5
R/W
4
FA4
R/W
3
FA3
R/W
RESET
2
FA2
R/W
1
FA1
R/W
0
FA0
R/W
FUNCTION
60
FA[6:0]
These bits define the current device address assigned to the function. The MCU writes a value to this
register because of the SET-ADDRESS host command.
RSV
Reserved = 0
5.5.5.2
USBSTA: USB Status Register (Addr:FFFEh)
All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper
bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding
mask bit is set (R/C notation indicates read and clear only by the MCU).
7
RSTR
R/C
BIT
6
SUSR
R/C
NAME
5
RESR
R/C
4
RSV
R/O
3
URRI
R/C
RESET
2
SETUP
R/C
1
WAKEUP
R/C
0
STPOW
R/C
FUNCTION
SETUP overwrite bit. Set by hardware when a setup packet is received while there is already a packet
in the setup buffer.
STPOW
STPOW = 0
MCU can clear this bit by writing a 1 (writing 0 has no effect).
STPOW = 1
SETUP overwrite
Remote wakeup bit
1
WAKEUP
WAKEUP = 0 The MCU can clear this bit by writing a 1 (writing 0 has no effect).
WAKEUP = 1 Remote wake-up request from WAKEUP terminal
SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint-0 are NAKed,
regardless of their real NAK bits value.
SETUP
SETUP = 0
MCU can clear this bit by writing a 1 (writing 0 has no effect).
SETUP = 1
SETUP transaction received
UART RI (ring indicate) status bit a rising edge causes this bit to be set.
3
URRI
RSV
RESR
URRI = 0
The MCU can clear this bit by writing a 1 (writing 0 has no effect).
URRI = 1
Ring detected, which is used to wake the chip up (bring it out of suspend).
Reserved
Function resume request bit
RESR = 0
The MCU can clear this bit by writing a 1 (writing 0 has no effect).
RESR = 1
Function resume is detected
Function suspended request bit. This bit is set in response to a global or selective suspend condition.
6
SUSR
SUSR = 0
The MCU can clear this bit by writing a 1 (writing 0 has no effect).
SUSR = 1
Function suspend is detected
Function reset request bit. This bit is set in response to the USB host initiating a port reset. This bit is
not affected by the USB function reset.
7
38
RSTR
Detailed Description
RSTR = 0
The MCU can clear this bit by writing a 1 (writing 0 has no effect).
RSTR = 1
Function reset is detected
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5.5.5.3
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USBMSK: USB Interrupt Mask Register (Addr:FFFDh)
7
RSTR
R/W
6
SUSR
R/W
BIT
NAME
RESET
STPOW
5
RESR
R/W
4
RSV
R/O
3
URRI
R/W
2
SETUP
R/W
1
WAKEUP
R/W
0
STPOW
R/W
FUNCTION
SETUP overwrite interrupt-enable bit
STPOW = 0
STPOW interrupt disabled
STPOW = 1
STPOW interrupt enabled
Remote wake-up interrupt enable bit
1
WAKEUP
WAKEUP = 0 WAKEUP interrupt disable
WAKEUP = 1 WAKEUP interrupt enable
SETUP interrupt enable bit
SETUP
SETUP = 0
SETUP interrupt disabled
SETUP = 1
SETUP interrupt enabled
UART RI interrupt enable bit
3
URRI
RSV
RESR
URRI = 0
UART RI interrupt disable
URRI = 1
UART RI interrupt enable
Reserved
Function resume interrupt enable bit
RESR = 0
Function resume interrupt disabled
RESR = 1
Function resume interrupt enabled
Function suspend interrupt enable
6
SUSR
SUSR = 0
Function suspend interrupt disabled
SUSR = 1
Function suspend interrupt enabled
Function reset interrupt bit. This bit is not affected by USB function reset.
7
RSTR
RSTR = 0
Function reset interrupt disabled
RSTR = 1
Function reset interrupt enabled
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5.5.5.4
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USBCTL: USB Control Register (Addr:FFFCh)
Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset
cannot reset this register (see Figure 5-9).
7
CONT
R/W
BIT
NAME
6
IREN
R/W
5
RWUP
R/C
4
FRSTE
R/W
RESET
3
RSV
R/W
2
RSV
R/W
1
SIR
R/W
0
DIR
R/W
FUNCTION
As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data
transfer direction.
DIR
DIR = 0
USB data-OUT transaction (from host to TUSB3410)
DIR = 1
USB data-IN transaction (from TUSB3410 to host)
SETUP interrupt-status bit. This bit is controlled by the MCU to indicate to the hardware when the SETUP
interrupt is being serviced.
1
SIR
SIR = 0
SETUP interrupt is not served. The MCU clears this bit before exiting the SETUP interrupt
routine.
RSV
SIR = 1
Reserved = 0
SETUP interrupt is in progress. The MCU sets this bit when servicing the SETUP interrupt.
RSV
This bit must always be written as 0.
Function reset-connection bit. This bit connects/disconnects the USB function reset to/from the MCU reset.
FRSTE
FRSTE = 0
Function reset is not connected to MCU reset
FRSTE = 1
Function reset is connected to MCU reset
Device remote wake-up request. This bit is set by the MCU and is cleared automatically.
5
RWUP
RWUP = 0
Writing a 0 to this bit has no effect
RWUP = 1
When MCU writes a 1, a remote-wakeup pulse is generated.
IR mode enable. This bit is set and cleared by firmware.
6
IREN
IREN = 0
IR encoder/decoder is disabled, UART mode is selected
IREN = 1
IR encoder/decoder is enabled, UART mode is deselected
Connect/disconnect bit
7
40
CONT
Detailed Description
CONT = 0
Upstream port is connected. Pullup enabled.
CONT = 1
Upstream port is disconnected. Pullup disabled.
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5.5.5.5
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MODECNFG: Mode Configuration Register (Addr:FFFBh)
This register is cleared by the power-up reset signal only. The USB reset cannot reset this register.
7
RSV
R/O
BIT
6
RSV
R/O
NAME
5
RSV
R/O
4
RSV
R/O
3
CLKSLCT
R/W
RESET
2
CLKOUTEN
R/W
1
SOFTSW
R/W
0
TXCNTL
R/W
FUNCTION
Transmit output control: Hardware or firmware switching select for 3-state serial output buffer.
TSCNTL
TXCNTL = 0
Hardware automatic switching is selected
TXCNTL = 1
Firmware toggle switching is selected
Soft switch: Firmware controllable 3-state output buffer enable for serial output terminal.
1
SOFTSW
SOFTSW = 0
Serial output buffer is enabled
SOFTSW = 1
Serial output buffer is disabled
Clock output enable: Enables/disables the clock output at CLKOUT terminal.
2
CLKOUTEN
CLKOUTEN = 0 Clock output is disabled. Device drives low at CLKOUT terminal.
CLKOUTEN = 1 Clock output is enabled
Clock output source select: Selects between 3.556-MHz fixed clock or UART baud out clock as output
clock source.
CLKSLCT
47
RSV
5.5.5.6
CLKSLCT = 0
UART baud out clock is selected as clock output
CLKSLCT = 1
Fixed 3.556-MHz free running clock is selected as clock output
Reserved
Clock Output Control
Bit 2 (CLKOUTEN) in the MODECNFG register enables or disables the clock output at the CLKOUT
terminal of the TUSB3410 device. The power-up default of CLKOUT is disabled. Firmware can write a 1 to
enable the clock output if needed.
Bit 3 (CLKSLCT) in the MODECNFG register selects the output clock source from either a fixed
3.556-MHz free-running clock or the UART BaudOut clock.
5.5.5.7
Vendor ID/Product ID
USBIF and Microsoft WHQL certification requires that end equipment makers use their own unique
vendor ID and product ID for each product (model). OEMs cannot use silicon vendors VID/PID (for
instance, TIs default) in their end products. A unique VID/PID combination will avoid potential driver
conflicts and enable logo certification. See www.usb.org for more information.
5.5.5.8
SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh)
Each TUSB3410 device has a unique 64-bit serial die id number, which is generated during
manufacturing. The die id is incremented sequentially, however there is no assurance that numbers will
not be skipped. The device serial number registers mirror this unique 64-bit serial die id value.
After power-up reset, this read-only register (SERNUM7) contains the most significant byte (byte 7) of the
complete 64-bit device serial number. This register cannot be reset.
7
D63
R/O
6
D62
R/O
5
D61
R/O
4
D60
R/O
BIT
NAME
RESET
70
D[63:56]
Device serial number byte 7 value
3
D59
R/O
2
D58
R/O
1
D57
R/O
0
D56
R/O
FUNCTION
Device serial number byte 7 value
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Procedure to load device serial number value in shared RAM:
After power-up reset, the boot code copies the predefined USB descriptors to shared RAM. As a result,
the default serial number hard-coded in the boot code (0x00 hex) is copied to the shared RAM data
space.
The boot code checks to see if an EEPROM is present on the I2C port. If an EEPROM is present and
contains a valid device serial number as part of the USB device descriptor information stored in
EEPROM, then the boot code overwrites the serial number value stored in shared RAM with the one
found in EEPROM. Otherwise, the device serial number value stored in shared RAM remains
unchanged. If firmware is stored in the EEPROM, then it is executed. This firmware can read the
SERNUM7 through SERNUM0 registers and overwrite the serial number stored in RAM or store a
custom number in RAM.
In summary, the serial number value in external EEPROM has the highest priority to be loaded into
shared RAM data space. The serial number value stored in shared RAM is used as part of the valid
device descriptor information during normal operation.
5.5.5.9
SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM6) contains byte 6 of the complete 64-bit device
serial number. This register cannot be reset.
7
D55
R/O
BIT
70
6
D54
R/O
NAME
D[55:48]
5
D53
R/O
4
D52
R/O
3
D51
R/O
RESET
Device serial number byte 6 value
2
D50
R/O
1
D49
R/O
0
D48
R/O
FUNCTION
Device serial number byte 6 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
5.5.5.10 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM5) contains byte 5 of the complete 64-bit device
serial number. This register cannot be reset.
7
D47
R/O
BIT
70
6
D46
R/O
NAME
D[47:40]
5
D45
R/O
4
D44
R/O
3
D43
R/O
RESET
Device serial number byte 5 value
2
D42
R/O
1
D41
R/O
0
D40
R/O
FUNCTION
Device serial number byte 5 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
42
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5.5.5.11 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM4) contains byte 4 of the complete 64-bit device
serial number. This register cannot be reset.
7
D39
R/O
BIT
70
6
D38
R/O
NAME
D[39:32]
5
D37
R/O
4
D36
R/O
3
D35
R/O
RESET
Device serial number byte 4 value
2
D34
R/O
1
D33
R/O
0
D32
R/O
FUNCTION
Device serial number byte 4 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
5.5.5.12 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM3) contains byte 3 of the complete 64-bit device
serial number. This register cannot be reset.
7
D31
R/O
BIT
70
6
D30
R/O
NAME
D[31:24]
5
D29
R/O
4
D28
R/O
3
D27
R/O
RESET
Device serial number byte 3 value
2
D26
R/O
1
D25
R/O
0
D24
R/O
FUNCTION
Device serial number byte 3 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
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5.5.5.13 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM2) contains byte 2 of the complete 64-bit device
serial number. This register cannot be reset.
7
D23
R/O
BIT
70
6
D21
R/O
5
D20
R/O
NAME
D[23:16]
4
D19
R/O
3
D18
R/O
RESET
0
2
D17
R/O
1
D16
R/O
0
D15
R/O
FUNCTION
Device serial number byte 2 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
5.5.5.14 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM1) contains byte 1 of the complete 64-bit device
serial number. This register cannot be reset.
7
D15
R/O
6
D14
R/O
BIT
70
NAME
D[15:8]
5
D13
R/O
4
D12
R/O
3
D11
R/O
RESET
Device serial number byte 1 value
2
D10
R/O
1
D9
R/O
0
D8
R/O
FUNCTION
Device serial number byte 1 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
44
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5.5.5.15 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h)
The device serial number registers mirror the unique 64-bit die id value.
After power-up reset, this read-only register (SERNUM0) contains byte 0 of the complete 64-bit device
serial number. This register cannot be reset.
7
D7
R/O
6
D6
R/O
BIT
70
NAME
D[7:0]
5
D5
R/O
4
D4
R/O
3
D3
R/O
RESET
Device serial number byte 0 value
2
D2
R/O
1
D1
R/O
0
D0
R/O
FUNCTION
Device serial number byte 0 value
NOTE
See the procedure described in the SERNUM7 register (see Section 5.5.5.8) to load the
device serial number into shared RAM.
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5.5.5.16 Function Reset and Power-Up Reset Interconnect
Figure 5-9 represents the logical connection of the USB-function reset (USBR) signal and the power-up
reset (RESET) terminal. The internal RESET signal is generated from the RESET terminal (PURS signal)
or from the USB reset (USBR signal). The USBR can be enabled or disabled by bit 4 (FRSTE) in the
USBCTL register (see Section 5.5.5.4) (on power up, FRSTE = 0). The internal RESET is used to reset all
registers and logic, with the exception of the USBCTL and MODECNFG registers, which are cleared by
the PURS signal only.
USBCTL Register
MODECNFG Register
To Internal MMRs
MCU
RESET
PURS
RESET
USBR
USB Function Reset
G2
FRSTE
WDT Reset
WDD[5:0]
Figure 5-9. Reset Diagram
5.5.5.17 Pullup Resistor Connect and Disconnect
The TUSB3410 device enumeration can be activated by the MCU (there is no need to disconnect the
cable physically). Figure 5-10 represents the implementation of the TUSB3410 device connect and
disconnect from a USB up-stream port. When bit 7 (CONT) is 1 in the USBCTL register (see
Section 5.5.5.4), the CMOS driver sources VDD to the pullup resistor (PUR terminal) presenting a normal
connect condition to the USB host. When CONT is 0, the PUR terminal is driven low. In this state, the
1.5-k resistor is connected to GND, resulting in the device disconnection state. The PUR driver is a
CMOS driver that can provide (VDD 0.1 V) minimum at 8-mA source current.
CMOS
PUR
CONT Bit
1.5 k
D+
DP0
DM0
15 k
HOST
TUSB3410
Figure 5-10. Pullup Resistor Connect and Disconnect Circuit
46
Detailed Description
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5.5.6
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
DMA Controller Registers
Table 5-8 outlines the DMA channels and their associated transfer directions. Two channels are provided
for data transfer between the host and the UART.
Table 5-8. DMA Controller Registers
DMA CHANNEL
TRANSFER DIRECTION
COMMENTS
DMA1
Host to UART
DMA writes to UART TDR register
DMA3
UART to host
DMA reads from UART RDR register
Each DMA channel can point to one of three EDBs (EDB-1 to EDB-3) and transfer data to/from the UART
channel. The DMA can move data from a given out-point buffer (defined by the EDB) to the destination
port. Similarly, the DMA can move data from a port to a given input-endpoint buffer.
At the end of a block transfer, the DMA updates the byte count and bit 7 (NAK) in the EDB (see
Section 5.5.4) when receiving. In addition, it uses bit 4 (XY) in the DMACDR register to switch
automatically, without interrupting the MCU (the XY bit toggle is performed by the UBM). The DMA stops
only when a time-out or error condition occurs. When the DMA is transmitting (from the X/Y buffer) it
continues alternating between X/Y buffers until it detects a byte count smaller than the buffer size (buffer
size is typically 64 bytes). At that point it completes the transfer and stops.
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DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h)
These registers define the EDB number that the DMA uses for data transfer to the UARTS. In addition,
these registers define the data transfer direction and selects X or Y as the transaction buffer.
7
EN
R/W
BIT
6
INE
R/W
NAME
5
CNT
R/W
4
XY
R/W
RESET
3
T/R
R/O
2
E2
R/W
1
E1
R/W
0
E0
R/W
FUNCTION
20
E[2:0]
Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given
transfer.
T/R
This bit is always 1, indicating that the DMA data transfer is from SRAM to the UART TDR register (see
Section 5.5.7.2). (The MCU cannot change this bit.)
X/Y buffer select bit.
XY
CNT
XY = 0
Next buffer to transmit/receive is the X buffer
XY = 1
Next buffer to transmit/receive is the Y buffer
DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must
always be written as 1.
In this mode, the DMA and UBM alternate between the X- and Y-buffers. The DMA sets bit 4 (XY) and
the UBM uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues
transmitting (from X-/Y-buffer) without MCU intervention. The DMA terminates, and interrupts the MCU,
under the following conditions:
1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and
interrupt the MCU on completion.
2. Transaction timer expires. The DMA interrupts the MCU.
DMA Interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.
INE
INE = 0
Interrupt is disabled. In addition, bit 0 (PPKT) in the DMACSR1 register (see
Section 5.5.6.2) does not clear bit 7 (EN) and the DMAC is not disabled.
INE = 1
Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1 to 0
transition of the bit 7 (EN). (When transfer is completed, EN = 0.)
DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes,
or when it is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an
interrupt (if the interrupt is enabled).
7
48
EN
Detailed Description
EN = 0
DMA is halted. The DMA is halted when the byte count reaches zero or transaction timeout occurs. When halted, the DMA updates the byte count, sets NAK = 0 in the output
endpoint byte count register, and interrupts the MCU (if bit 6 (INE) = 1).
EN = 1
Setting this bit starts the DMA transfer.
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5.5.6.2
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1h)
This register defines the transaction time-out value. In addition, it contains a completion code that reports
any errors or a time-out condition.
7
0
R
BIT
6
0
R
NAME
5
0
R
4
0
R
RESET
3
0
R
2
0
R
1
0
R
0
PPKT
R/C
FUNCTION
Partial packet condition bit. This bit is set by the DMA and cleared by the MCU.
71
PPKT
PPKT =
0
No partial-packet condition
PPKT =
1
Partial-packet condition detected. When INE = 0, this bit does not clear bit 7 (EN) in the
DMACDR1 register; therefore, the DMAC stays enabled, ready for the next transaction.
Clears when MCU writes a 1. Writing a 0 has no effect.
These bits are read-only and return 0s when read.
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DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h)
These registers define the EDB number that the DMA uses for data transfer from the UARTS. In addition,
these registers define the data transfer direction and selects X or Y as the transaction buffer.
7
EN
R/W
BIT
6
INE
R/W
NAME
5
CNT
R/W
4
XY
R/W
RESET
3
T/R
R/O
2
E2
R/W
1
E1
R/W
0
E0
R/W
FUNCTION
20
E[2:0]
Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given
transfer.
T/R
This bit is always read as 1. This bit must be written as 0 to update the X/Y buffer bit (bit 4 in this
register), which must only be performed in burst mode.
X/Y buffer select bit.
XY
CNT
XY = 0
Next buffer to transmit/receive is X
XY = 1
Next buffer to transmit/receive is Y
DMA continuous transfer control bit. This bit defines the mode of the DMA transfer. This bit must
always be written as 1.
In this mode, the DMA and UBM alternate between the X- and Y-buffers. The UBM sets bit 4 (XY)
and the DMA uses it for the transfer. The DMA alternates between the X-/Y-buffers and continues
receiving (to X-/Y-buffer) without MCU intervention. The DMA terminates the transfer and interrupts
the MCU, under the following conditions:
1. Transaction time-out expired: DMA updates EDB and interrupts the MCU. UBM transfers the
partial packet to the host.
2. UART receiver error condition: DMA updates EDB and does not interrupt the MCU. UBM
transfers the partial packet to the host.
DMA Interrupt enable/disable bit. This bit enables/disables the interrupt on transfer completion.
INE
INE = 0
Interrupt is disabled. In addition, bit 0 (OVRUN) and bit 1 (TXFT) in the DMACSR3
register (see Section 5.5.6.4) do not clear bit 7 (EN) and the DMAC is not disabled.
INE = 1
Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0
transition of bit 7 (EN). (When transfer is completed, EN = 0).
DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When transfer completes,
or when terminated due to error, this bit is cleared. The 1-to-0 transition of this bit generates an
interrupt (if the interrupt is enabled).
7
50
EN
Detailed Description
EN = 0
DMA is halted. The DMA is halted when transaction time-out occurs, or under a UART
receiver-error condition. When halted, the DMA updates the byte count and sets NAK =
0 in the input endpoint byte count register. If the termination is due to transaction timeout, then the DMA generates an interrupt. However, if the termination is due to a UART
error condition, then the DMA does not generate an interrupt. (The UART generates the
interrupt.)
EN = 1
Setting this bit starts the DMA transfer.
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5.5.6.4
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h)
This register defines the transaction time-out value. In addition, it contains a completion code that reports
any errors or a time-out condition.
7
TEN
R/W
BIT
6
C4
R/W
NAME
5
C3
R/W
4
C2
R/W
3
C1
R/W
RESET
2
C0
R/W
1
TXFT
R/C
0
OVRUN
R/C
FUNCTION
Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 5-9)
OVRUN
OVRUN
=0
No overrun condition
OVRUN
=1
Overrun condition detected. When IEN = 0, this bit does not clear bit 7 (EN) in the
DMACDR register; therefore, the DMAC stays enabled, ready for the next transaction.
Clears when the MCU writes a 1. Writing a 0 has no effect.
Transfer time-out condition bit (see Table 5-9)
TXFT = 0 DMA stopped transfer without time-out
1
TXFT
62
C[4:0]
TEN
TXFT = 1 DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear bit 7 (EN) in
the DMACDR3 register (see Section 5.5.6.3); therefore, the DMAC stays enabled, ready for
the next transaction. Clears when the MCU writes a 1. Writing a 0 has no effect.
This field defines the transaction time-out value in 1-ms increments. This value is loaded to a down
counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms).
If the counter decrements to zero, then it sets bit 1 (TXFT) = 1 and halts the DMA transfer. The counter
starts counting only when bit 7 (TEN) = 1 and bit 7 (EN) = 1 in the DMACDR3 register and the first byte
00000b has been received.
00000 = 0-ms time-out
:
:
11111 = 31-ms time-out
Transaction time-out counter enable/disable bit
0
TEN = 0
Counter is disabled (does not time-out)
TEN = 1
Counter is enabled
Table 5-9. DMA IN-Termination Condition
IN TERMINATION
UART error
UART partial packet
UART overrun
TXFT
OVRUN
UART error condition detected
COMMENTS
This condition occurs when UART receiver has no more data for the host (data
starvation).
This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host
is busy).
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UART Registers
Table 5-10 summarizes the UART registers. These registers are used for data I/O, control, and status
information. UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However,
the MCU can perform data transfer without a DMA; this is useful when debugging the firmware.
Table 5-10. UART Registers Summary
REGISTER ADDRESS
REGISTER NAME
ACCESS
FFA0h
RDR
R/O
UART receiver data register
FUNCTION
Can be accessed by MCU or DMA
COMMENTS
FFA1h
TDR
W/O
UART transmitter data register
Can be accessed by MCU or DMA
FFA2h
LCR
R/W
UART line control register
FFA3h
FCRL
R/W
UART flow control register
FFA4h
MCR
R/W
UART modem control register
FFA5h
LSR
R/O
UART line status register
Can generate an interrupt
FFA6h
MSR
R/O
UART modem status register
Can generate an interrupt
FFA7h
DLL
R/W
UART divisor register (low byte)
FFA8h
DLH
R/W
UART divisor register (high byte)
FFA9h
XON
R/W
UART Xon register
FFAAh
XOFF
R/W
UART Xoff register
FFABh
MASK
R/W
UART interrupt mask register
5.5.7.1
Can control three interrupt sources
RDR: Receiver Data Register (Addr:FFA0h)
The receiver data register consists of a 32-byte FIFO. Data received through the SIN terminal is converted
from serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is
the responsibility of the DMA controller.
7
D7
R/O
6
D6
R/O
BIT
70
NAME
D[7:0]
5.5.7.2
5
D5
R/O
4
D4
R/O
3
D3
R/O
RESET
0
2
D2
R/O
1
D1
R/O
0
D0
R/O
FUNCTION
Receiver byte
TDR: Transmitter Data Register (Addr:FFA1h)
The transmitter data register is double buffered. Data written to this register is loaded into the shift
register, and shifted out on SOUT. Data transfer from the RAM buffer to this register is the responsibility of
the DMA controller.
7
D7
W/O
BIT
70
52
6
D6
W/O
NAME
D[7:0]
Detailed Description
5
D5
W/O
4
D4
W/O
RESET
0
3
D3
W/O
2
D2
W/O
1
D1
W/O
0
D0
W/O
FUNCTION
Transmit byte
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5.5.7.3
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LCR: Line Control Register (Addr:FFA2h)
This register controls the data communication format. The word length, number of stop bits, and parity
type are selected by writing the appropriate bits to the LCR.
7
FEN
R/W
BIT
10
6
BRK
R/W
NAME
WL[1:0]
5
FPTY
R/W
4
EPRTY
R/W
3
PRTY
R/W
RESET
2
STP
R/W
1
WL1
R/W
0
WL0
R/W
FUNCTION
Specifies the word length for transmit and receive
00b = 5 bits
01b = 6 bits
10b = 7 bits
11b = 8 bits
Specifies the number of stop bits for transmit and receive
STP
STP = 0
1 stop bit (word length = 5, 6, 7, 8)
STP = 1
1.5 stop bits (word length = 5)
STP = 1
2 stop bits (word length = 6, 7, 8)
Specifies whether parity is used
3
PRTY
PRTY = 0
No parity
PRTY = 1
Parity is generated
Specifies whether even or odd parity is generated
4
EPRTY
EPRTY =
0
Odd parity is generated (if bit 3 (PRTY) = 1)
EPRTY =
1
Even parity is generated (if PRTY = 1)
Selects the forced parity bit
5
FPTY
FPTY = 0
Parity is not forced
FPTY = 1
Parity bit is forced. If bit 4 (EPRTY) = 0, the parity bit is forced to 1
This bit is the break-control bit
6
BRK
BRK = 0
Normal operation
BRK = 1
Forces SOUT into break condition (logic 0)
FIFO enable. This bit disables/enables the FIFO. To reset the FIFO, the MCU clears and then sets this
bit.
7
FEN
FEN = 0
The FIFO is cleared and disabled. When disabled, the selected receiver flow control is
activated.
FEN = 1
The FIFO is enabled and it can receive data.
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FCRL: UART Flow Control Register (Addr:FFA3h)
This register provides the flow-control modes of operation (see Table 5-12 for more details).
7
485E
R/W
BIT
6
DTR
R/W
NAME
5
RTS
R/W
4
RXOF
R/W
3
DSR
R/W
RESET
2
CTS
R/W
1
TXOA
R/W
0
TXOF
R/W
FUNCTION
This bit controls the transmitter Xon/Xoff flow control.
TXOF
TXOF = 0
Disable transmitter Xon/Xoff flow control
TXOF = 1
Enable transmitter Xon/Xoff flow control
This bit controls the transmitter Xon-on-any/Xoff flow control
1
TXOA
TXOA = 0
Disable the transmitter Xon-on-any/Xoff flow control
TXOA = 1
Enable the transmitter Xon-on-any/Xoff flow control
Transmitter CTS flow-control enable bit
2
CTS
CTS = 0
Disables transmitter CTS flow control
CTS = 1
CTS flow control is enabled, that is, when CTS input terminal is high, transmission
is halted; when the CTS terminal is low, transmission resumes. When loopback
mode is enabled, this bit must be set if flow control is also required.
Transmitter DSR flow-control enable bit
3
DSR
RXOF
DSR = 0
Disables transmitter DSR flow control
DSR = 1
DSR flow control is enabled, that is, when DSR input terminal is high, transmission
is halted; when the DSR terminal is low, transmission resumes. When loopback
mode is enabled, this bit must be set if flow control is also required.
This bit controls the receiver Xon/Xoff flow control.
RXOF = 0
Receiver does not attempt to match Xon/Xoff characters
RXOF = 1
Receiver searches for Xon/Xoff characters
Receiver RTS flow control enable bit
5
RTS
RTS = 0
Disables receiver RTS flow control
RTS = 1
Receiver RTS flow control is enabled. RTS output terminal goes high when the
receiver FIFO HALT trigger level is reached; it goes low, when the receiver FIFO
RESUME receiving trigger level is reached.
Receiver DTR flow-control enable bit
6
DTR
DTR = 0
Disables receiver DTR flow control
DTR = 1
Receiver DTR flow control is enabled. DTR output terminal goes high when the
receiver FIFO HALT trigger level is reached; it goes low, when the receiver FIFO
RESUME receiving trigger level is reached.
RS-485 enable bit. This bit configures the UART to control external RS-485 transceivers. When
configured in half-duplex mode (485E = 1), RTS or DTR can be used to enable the RS-485 driver or
receiver (see Figure 5-5).
54
485E
Detailed Description
485E = 0
UART is in normal operation mode (full duplex)
485E = 1
The UART is in half duplex RS-485 mode. In this mode, RTS and DTR are active
with opposite polarity (when RTS = 0, DTR = 1). When the DMA is ready to
transmit, it drives RTS = 1 (and DTR = 0) 2-bit times before the transmission starts.
When the DMA terminates the transmission, it drives RTS = 0 (and DTR = 1) after
the transmission stops. When 485E is set to 1, bit 4 (DTR) and bit 5 (RTS) in the
MCR register (see Section 5.5.7.6) have no effect. Also, see bit 1 (RCVE) in the
MCR register (see Section 5.5.7.6).
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Transmitter Flow Control
On reset (power up, USB, or soft reset) the transmitter defaults to the Xon state and the flow control is set
to mode-0 (flow control is disabled).
Table 5-11. Transmitter Flow-Control Modes
BIT 3
BIT 2
BIT 1
BIT 0
DSR
CTS
TXOA
TXOF
All flow control is disabled
Xon/Xoff flow control is enabled
Xon on any/ Xoff flow control
Not permissible (1)
CTS flow control
Combination flow control
(2)
Combination flow control
DSR flow control
Combination flow control
(1)
(2)
This is a no permissible combination. If used, TXOA and TXOF are cleared.
Combination example: Transmitter stops when either CTS or Xoff is detected. Transmitter resumes when both CTS is negated and Xon
is detected.
Table 5-12. Receiver Flow-Control Possibilities
MODE
(1)
(2)
BIT 6
BIT 5
BIT 4
DTR
RTS
RXOF
All flow control is disabled
Xon/Xoff flow control is enabled
RTS flow control
Combination flow control (1)
DTR flow control
Combination flow control
Combination flow control (2)
Combination flow control
Combination example: Both RTS is asserted and Xoff transmitted when the FIFO is full. Both RTS is deasserted and Xon is transmitted
when the FIFO is empty.
Combination example: Both DTR and RTS are asserted when the FIFO is full. Both DTR and RTS are deasserted when the FIFO is
empty.
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MCR: Modem-Control Register (Addr:FFA4h)
This register provides control for modem interface I/O and definition of the flow control mode.
7
LCD
R/W
BIT
6
LRI
R/W
NAME
5
RTS
R/W
4
DTR
R/W
3
RSV
R/W
RESET
2
LOOP
R/W
1
RCVE
R/W
0
URST
R/W
FUNCTION
UART soft reset. This bit can be used by the MCU to reset the UART.
URST
URST = 0
Normal operation. Writing a 0 by MCU has no effect.
URST = 1
When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When
the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if
the UART completed the reset cycle.
Receiver enable bit. This bit is valid only when bit 7 (485E) in the FCRL register (see Section 5.5.7.4) is 1
(RS-485 mode). When 485E = 0, this bit has no effect on the receiver.
1
RCVE
RCVE = 0
When 485E = 1, the UART receiver is disabled when RTS = 1, that is, when data is being
transmitted, the UART receiver is disabled.
RCVE = 1
When 485E = 1, the UART receiver is enabled regardless of the RTS state, that is, UART
receiver is enabled all the time. This mode can detect collisions on the RS-485 bus when
received data does not match transmitted data.
This bit controls the normal-/loop-back mode of operation (see Figure 5-11).
LOOP
RSV
LOOP = 0
Normal operation
LOOP = 1
Enable loop-back mode of operation. In this mode the following occur:
SOUT is set high
SIN is disconnected from the receiver input.
The transmitter serial output is looped back into the receiver serial input.
The four modem-control inputs: CTS, DSR, DCD, and RI/CP are disconnected.
DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and
read in the MSR register (see Section 5.5.7.8) as described below. Note: the FCRL register
(see Section 5.5.7.4) must be configured to enable bits 2 (CTS) and 3 (DSR) to maintain
proper operation with flow control and loop back.
DTR is reflected in MSR register bit 4 (LCTS)
RTS is reflected in MSR register bit 5 (LDSR)
LRI is reflected in MSR register bit 6 (LRI)
LCD is reflected in MSR register bit 7 (LCD)
Reserved
This bit controls the state of the DTR output terminal (see Figure 5-11). This bit has no effect when auto-flow
control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 5.5.7.4).
DTR
DTR = 0
Forces the DTR output terminal to inactive (high)
DTR = 1
Forces the DTR output terminal to active (low)
This bit controls the state of the RTS output terminal (see Figure 5-11). This bit has no effect when auto-flow
control is used or when bit 7 (485E) = 1 (in the FCRL register, see Section 5.5.7.4).
5
RTS
RTS = 0
Forces the RTS output terminal to inactive (high)
RTS = 1
Forces the RTS output terminal to active (low)
This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 6 (LRI) in the
MSR register, (see Section 5.5.7.8 and Figure 5-11).
6
LRI
LRI = 0
Clears the MSR register bit 6 to 0
LRI = 1
Sets the MSR register bit 6 to 1
This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in bit 7 (LCD) in the
MSR register, (see Section 5.5.7.8 and Figure 5-11).
7
56
LCD
Detailed Description
LCD = 0
Clears the MSR register bit 7 to 0
LCD = 1
Sets the MSR register bit 7 to 1
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LSR: Line-Status Register (Addr:FFA5h)
This register provides the status of the data transfer. DMA transfer is halted when any of bit 0 (OVR), bit 1
(PTE), bit 2 (FRE), or bit 3 (BRK) is 1.
7
RSV
R/O
BIT
6
TEMT
R/O
NAME
5
TxE
R/O
4
RxF
R/O
3
BRK
R/C
RESET
2
FRE
R/C
1
PTE
R/C
0
OVR
R/C
FUNCTION
This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates
a status interrupt (if enabled).
OVR
OVR = 0
No overrun error
OVR = 1
Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.
This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and
generates a status interrupt (if enabled).
1
PTE
PTE = 0
No parity error in data received
PTE = 1
Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no
effect.
This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and
generates a status interrupt (if enabled).
2
FRE
FRE = 0
No framing error in data received
FRE = 1
Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.
This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and
generates a status interrupt (if enabled).
3
BRK
BRK = 0
No break condition
BRK = 1
A break condition in data received was detected. Clears when the MCU writes a 1.
Writing a 0 has no effect.
This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this
bit because data transfer is done by the DMA controller.
4
RxF
RxF = 0
No data in the RDR
RxF = 1
RDR contains data. Generates RX interrupt (if enabled).
This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor
this bit because data transfer is done by the DMA controller.
5
TxE
TxE = 0
TDR is not empty
TxE = 1
TDR is empty. Generates TX interrupt (if enabled).
This bit indicates the condition of both transmitter data register and shift register is empty.
6
7
TEMT
RSV
1
0
TEMT = 0
Either TDR or TSR is not empty
TEMT = 1
Both TDR and TSR are empty
Reserved = 0
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Device Terminals
CTS
DSR
Modem
Status
Register
Bit 4 LCTS
RI/CP
Bit 5 LDSR
DCD
Bit 6 LRI
Bit 7 LCD
FCRL Register Setting
Modem
Control
Register
Bit 4 DTR
DTR
Bit 5 RTS
RTS
Bit 6 LRI
Bit 7 LCD
Bit 2 LOOP
FCRL Register Setting
Figure 5-11. MSR and MCR Registers in Loop-Back Mode
58
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MSR: Modem-Status Register (Addr:FFA6h)
This register provides information about the current state of the control lines from the modem.
7
LCD
R/O
BIT
6
LRI
R/O
NAME
5
LDSR
R/O
3
CD
R/C
2
TRI
R/C
1
DSR
R/C
0
CTS
R/C
RESET
FUNCTION
This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit.
Writing a 0 has no effect.
CTS
4
LCTS
R/O
This bit indicates that the DSR input has changed state. Cleared when the MCU writes a 1 to this
bit. Writing a 0 has no effect.
DSR
DSR = 0
Indicates no change in the DSR input
DSR = 1
Indicates that the DSR input has changed state since the last time it was read.
Clears when the MCU writes a 1. Writing a 0 has no effect.
Trailing edge of the ring indicator. This bit indicates that the RI/CP input has changed from low to
high. This bit is cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect.
2
TRI
TRI = 0
Indicates no applicable transition on the RI/CP input
TRI = 1
Indicates that an applicable transition has occurred on the RI/CP input.
This bit indicates that the CD input has changed state. Cleared when the MCU writes a 1 to this bit.
Writing a 0 has no effect.
CD
CD = 0
Indicates no change in the CD input
CD = 1
Indicates that the CD input has changed state since the last time it was read.
During loopback, this bit reflects the status of bit 4 (DTR) in the MCR register (see Section 5.5.7.6
and Figure 5-11).
4
LCTS
LCTS = 0
CTS input is high
LCTS = 1
CTS input is low
During loop back, this bit reflects the status of bit 5 (RTS) in the MCR register (see Section 5.5.7.6
and Figure 5-11).
5
LDSR
LDSR = 0
DSR input is high
LDSR= 1
DSR input is low
During loop back, this bit reflects the status of bit 6 (LRI) in the MCR register (see Section 5.5.7.6
and Figure 5-11).
6
LRI
LRI = 0
RI/CP input is high
LRI = 1
RI/CP input is low
During loopback, this bit reflects the status of bit 7 (LCD) in the MCR register (see Section 5.5.7.6
and Figure 5-11).
7
LCD
5.5.7.9
LCD = 0
CD input is high
LCD = 1
CD input is low
DLL: Divisor Register Low Byte (Addr:FFA7h)
This register contains the low byte of the baud-rate divisor.
7
D7
R/W
6
D6
R/W
5
D5
R/W
4
D4
R/W
BIT
NAME
RESET
70
D[7:0]
08h
3
D3
R/W
2
D2
R/W
1
D1
R/W
0
D0
R/W
FUNCTION
Low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate
generator.
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5.5.7.10 DLH: Divisor Register High Byte (Addr:FFA8h)
This register contains the high byte of the baud-rate divisor.
7
D15
R/W
6
D14
R/W
5
D13
R/W
4
D12
R/W
BIT
NAME
RESET
70
D[15:8]
00h
3
D11
R/W
2
D10
R/W
1
D9
R/W
0
D8
R/W
FUNCTION
High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate
generator.
5.5.7.11 Baud-Rate Calculation
Equation 1 and Equation 2 calculate the baud-rate clock and the divisors. The baud-rate clock is derived
from the 96-MHz master clock (dividing by 6.5). Table 5-13 presents the divisors used to achieve the
desired baud rates, together with the associate rounding errors.
96 MHz
Baud CLK =
= 14.76923077 MHz
6.5
(1)
Divisor =
14.76923077 106
Desired Baud Rate 16
(2)
Table 5-13. DLL/DLH Values and Resulted Baud Rates (1)
(1)
60
DLL/DLH VALUE
DECIMAL
HEXADECIMAL
BAUD RATE
(bps)
ERROR %
1 200
769
301
1 200.36
0.03
2 400
385
181
2 397.60
0.01
4 800
192
00C0
4 807.69
0.16
7 200
128
80
7 211.54
0.16
9 600
96
60
9 615.38
0.16
14 400
64
40
14 423.08
0.16
19 200
48
30
19 230.77
0.16
38 400
24
18
38 461.54
0.16
57 600
16
10
57 692.31
0.16
115 200
115 384.62
0.16
230 400
230 769.23
0.16
460 800
461 538.46
0.16
921 600
923 076.92
0.16
DESIRED BAUD RATE
The TUSB3410 device does support baud rates lower than 1200 bps, which are not listed due to less
interest.
Detailed Description
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5.5.7.12 XON: Xon Register (Addr:FFA9h)
This register contains a value that is compared to the received data stream. Detection of a match
interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xon transmission.
7
D7
R/W
6
D6
R/W
5
D5
R/W
4
D4
R/W
BIT
70
NAME
D[7:0]
RESET
0000
3
D3
R/W
2
D2
R/W
1
D1
R/W
0
D0
R/W
FUNCTION
Xon value to be compared to the incoming data stream
5.5.7.13 XOFF: Xoff Register (Addr:FFAAh)
This register contains a value that is compared to the received data stream. Detection of a match halts the
DMA transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for
Xoff transmission.
7
D7
R/W
6
D6
R/W
5
D5
R/W
4
D4
R/W
BIT
70
NAME
D[7:0]
RESET
0000
3
D3
R/W
2
D2
R/W
1
D1
R/W
0
D0
R/W
1
SIE
R/W
0
MIE
R/W
FUNCTION
Xoff value to be compared to the incoming data stream
5.5.7.14 MASK: UART Interrupt-Mask Register (Addr:FFABh)
This register controls the UART interrupt sources.
7
RSV
R/O
6
RSV
R/O
5
RSV
R/O
BIT
NAME
RESET
4
RSV
R/O
3
RSV
R/O
2
TRI
R/W
FUNCTION
This bit controls the UART-modem interrupt.
0
MIE
MIE = 0
Modem interrupt is disabled
MIE = 1
Modem interrupt is enabled
This bit controls the UART-status interrupt.
1
SIE
SIE = 0
Status interrupt is disabled
SIE = 1
Status interrupt is enabled
This bit controls the UART-TxE/RxF interrupts
2
73
TRI
RSV
0
0
TRI = 0
TxE/RxF interrupts are disabled
TRI = 1
TxE/RxF interrupts are enabled
Reserved = 0
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Expanded GPIO Port
5.5.8.1
Input/Output and Control Registers
The TUSB3410 device has four general-purpose I/O terminals (P3.0, P3.1, P3.3, and P3.4) that are
controlled by firmware running on the MCU. Each terminal can be controlled individually and each is
implemented with a 12-mA push/pull CMOS output with 3-state control plus input. The MCU treats the
outputs as open drain types in that the output can be driven low continuously, but a high output is driven
for two clock cycles and then the output is high impedance.
An input terminal can be read using the MOV instruction. For example, MOV C, P3.3 reads the input on
P3.3. As a precaution, be certain the associated output is high impedance before reading the input.
An output can be set high (and then high impedance) using the SETB instruction. For example, SETB
P3.1 sets P3.1 high. An output can be set low using the CLR instruction, as in CLR P3.4, which sets P3.4
low (driven continuously until changed).
Each GPIO terminal has an associated internal pullup resistor. It is strongly recommended that the pullup
resistor remain connected to the terminal to prevent oscillations in the input buffer. The only exception is if
an external source always drives the input.
5.5.8.1.1 PUR_3: GPIO Pullup Register for Port 3 (Addr:FF9Eh)
62
7
RSV
R/O
6
RSV
R/O
5
RSV
R/O
BIT
NAME
RESET
Pin0
Pin1
Pin3
Pin4
2, 5, 6, 7
RSV
Reserved
Detailed Description
4
Pin4
R/W
3
Pin3
R/W
2
RSV
R/O
1
Pin1
R/W
0
Pin0
R/W
FUNCTION
The MCU may write to this register. If the MCU sets any of these bits to 1, then the
pullup resistor is disconnected from the associated terminal. If the MCU clears any of
these bits to 0, then the pullup resistor is connected from the terminal. The pullup
resistor is connected to the VCC power supply.
This bit controls the UART-status interrupt.
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5.5.9
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Interrupts
5.5.9.1
8052 Interrupt and Status Registers
All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that
controls the five interrupt sources. This is also known as IE0 located at S:A8h in the special function
register area. All the additional interrupt sources are ORed together to generate EX0.
Table 5-14. 8052 Interrupt Location Map
INTERRUPT SOURCE
DESCRIPTION
START ADDRESS
ES
UART interrupt
0023h
ET1
Timer-1 interrupt
001Bh
EX1
External interrupt-1
0013h
ET0
Timer-0 interrupt
000Bh
EX0
External interrupt-0
0003h
Reset
COMMENTS
Used for all internal peripherals
0000h
5.5.9.1.1 8052 Standard Interrupt Enable (SIE) Register
7
EA
R/W
6
RSV
R/W
5
RSV
R/W
BIT
NAME
RESET
4
ES
R/W
3
ET1
R/W
2
EX1
R/W
1
ET0
R/W
0
EX0
R/W
FUNCTION
Enable or disable external interrupt-0
EX0
EX0 = 0
External interrupt-0 is disabled
EX0 = 1
External interrupt-0 is enabled
Enable or disable timer-0 interrupt
1
ET0
ET0 = 0
Timer-0 interrupt is disabled
ET0 = 1
Timer-0 interrupt is enabled
Enable or disable external interrupt-1
2
EX1
EX1 = 0
External interrupt-1 is disabled
EX1 = 1
External interrupt-1 is enabled
Enable or disable timer-1 interrupt
3
ET1
ET1 = 0
Timer-1 interrupt is disabled
EX1 = 1
Timer-1 interrupt is enabled
Enable or disable serial port interrupts
4
ES
5, 6
RSV
EA
ES = 0
Serial-port interrupt is disabled
ES = 1
Serial-port interrupt is enabled
Reserved
Enable or disable all interrupts (global disable)
EA = 0
Disable all interrupts
EA = 1
Each interrupt source is individually controlled
5.5.9.1.2 Additional Interrupt Sources
All nonstandard 8052 interrupts (DMA, I2C, and so on) are ORed to generate an internal INT0.
Furthermore, the INT0 must be programmed as an active low-level interrupt (not edge-triggered). After
reset, if INT0 is not changed, then it is an edge-triggered interrupt. A vector interrupt register is provided to
identify all interrupt sources (see Section 5.5.9.1.3. Up to 64 interrupt vectors are provided. It is the
responsibility of the MCU to read the vector and dispatch to the proper interrupt routine.
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5.5.9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h)
This register contains a vector value, which identifies the internal interrupt source that is trapped to
location 0003h. Writing (any value) to this register removes the vector and updates the next vector value
(if another interrupt is pending).
NOTE
The vector value is offset; therefore, its value is in increments of two (bit 0 is set to 0).
When no interrupt is pending, the vector is set to 00h (see Table 5-15). As shown, the interrupt vector is
divided to two fields: I[2:0] and G[3:0]. The I field defines the interrupt source within a group (on a firstcome-first-served basis). In the G field, which defines the group number, group G0 is the lowest and G15
is the highest priority.
7
G3
R/O
6
G2
R/O
5
G1
R/O
4
G0
R/O
BIT
NAME
RESET
3
I2
R/O
2
I1
R/O
1
I0
R/O
0
0
R/O
FUNCTION
31
I[2:0]
0H
This field defines the interrupt source in a given group (see Table 5-15). Bit 0 = 0
always; therefore, vector values are offset by two.
74
G[3:0]
0H
This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual
interrupt vector.
Table 5-15. Vector Interrupt Values
64
G[3:0]
(Hex)
I[2:0]
(Hex)
VECTOR
(Hex)
00
1
1
1
1
1
0
1
2
3
47
10
12
14
16
181E
Not used
Output endpoint-1
Output endpoint-2
Output endpoint-3
Reserved
2
2
2
2
2
0
1
2
3
47
20
22
24
26
282E
Reserved
Input endpoint-1
Input endpoint-2
Input endpoint-3
Reserved
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
30
32
34
36
38
3A
3C
3E
4
4
4
4
4
0
1
2
3
47
40
42
44
46
48 4E
I2C TXE interrupt
I2C RXF interrupt
Input endpoint-0
Output endpoint-0
Reserved
5
5
5
0
1
27
50
52
54 5E
UART status interrupt
UART modem interrupt
Reserved
6
6
6
0
1
27
60
62
64 6E
UART RXF interrupt
UART TXE interrupt
Reserved
07
70 7E
Reserved
Detailed Description
INTERRUPT SOURCE
No interrupt
STPOW packet received
SETUP packet received
Reserved
Reserved
RESR interrupt
SUSR interrupt
RSTR interrupt
Wakeup
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Table 5-15. Vector Interrupt Values (continued)
G[3:0]
(Hex)
I[2:0]
(Hex)
VECTOR
(Hex)
8
8
8
0
2
37
80
84
868E
915
90 FE
INTERRUPT SOURCE
DMA1 interrupt
DMA3 interrupt
Reserved
Not used
5.5.9.1.4 Logical Interrupt Connection Diagram (Internal/External)
Figure 5-12 shows the logical connection of the interrupt sources and its relationship to INT0. The priority
encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt
priorities are hardwired. Vector 0x88 is the highest and 0x12 is the lowest.
Interrupts
Priority
Encoder
IEO
Vector
IEO (INT0)
Figure 5-12. Internal Vector Interrupt
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5.5.10 I2C Registers
5.5.10.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h)
This register controls the stop condition for read and write operations. In addition, it provides transmitter
and receiver handshake signals with their respective interrupt enable bits.
7
RXF
R/O
BIT
6
RIE
R/W
NAME
5
ERR
R/C
4
1/4
R/W
RESET
3
TXE
R/O
2
TIE
R/W
1
SRD
R/W
0
SWR
R/W
FUNCTION
Stop write condition. This bit determines if the I2C controller generates a stop condition when data from
the I2CDAO register is transmitted to an external device.
SWR
SWR = 0
Stop condition is not generated when data from the I2CDAO register is shifted out to an
external device.
SWR = 1
Stop condition is generated when data from the I2CDAO register is shifted out to an external
device.
Stop read condition. This bit determines if the I2C controller generates a stop condition when data is
received and loaded into the I2CDAI register.
1
SRD
SRD = 0
Stop condition is not generated when data from the SDA line is shifted into the I2CDAI
register.
SRD = 1
Stop condition is generated when data from the SDA line are shifted into the I2CDAI
register.
I2C transmitter empty interrupt enable
2
TIE
TIE = 0
Interrupt disable
TIE = 1
Interrupt enable
I2C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for
polling or it can generate an interrupt.
3
TXE
TXE = 0
Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDAO register.
TXE = 1
Transmitter is empty. The I2C controller sets this bit when the contents of the I2CDAO
register are copied to the SDA shift register.
Bus speed selection (1)
4
1/4
1/4 = 0
100-kHz bus speed
1/4 = 1
400-kHz bus speed
Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the
MCU.
5
ERR
ERR = 0
No bus error
ERR = 1
Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has no
effect.
I2C receiver ready interrupt enable
6
RIE
RIE = 0
Interrupt disable
RIE = 1
Interrupt enable
I2C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can
generate an interrupt.
7
(1)
66
RXF
RXF = 0
Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register.
RXF = 1
Receiver contains new data. This bit is set by the I2C controller when the received serial
data has been loaded into the I2CDAI register.
The bootcode automatically sets the I2C bus speed to 400 kHz. Only 400-kHz I2C EEPROMs can be used.
Detailed Description
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5.5.10.2 I2CADR: I2C Address Register (Addr:FFF3h)
This register holds the device address and the read/write command bit.
7
A6
R/W
6
A5
R/W
5
A4
R/W
BIT
NAME
RESET
4
A3
R/W
3
A2
R/W
2
A1
R/W
1
A0
R/W
0
R/W
R/W
1
D1
R/O
0
D0
R/O
FUNCTION
Read/write command bit
R/W
71
A[6:0]
0
0h
R/W = 0
Write operation
R/W = 1
Read operation
Seven address bits for device addressing
5.5.10.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h)
This register holds the received data from an external device.
7
D7
R/O
6
D6
R/O
5
D5
R/O
BIT
NAME
RESET
7-0
D[7:0]
4
D4
R/O
3
D3
R/O
2
D2
R/O
FUNCTION
8-bit input data from an I2C device
5.5.10.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h)
This register holds the data to be transmitted to an external device. Writing to this register starts the
transfer on the SDA line.
7
D7
W/O
6
D6
W/O
5
D5
W/O
BIT
NAME
RESET
7-0
5.6
5.6.1
D[7:0]
4
D4
W/O
3
D3
W/O
2
D2
W/O
1
D1
W/O
0
D0
W/O
FUNCTION
2
8-bit input data from an I C device
Boot Modes
Introduction
The TUSB3410 device bootcode is a program embedded in the 10k-byte boot ROM within the TUSB3410
device. This program is designed to load application firmware from either an external I2C memory device
or USB host bootloader device driver. After the TUSB3410 device finishes downloading, the bootcode
releases its control to the application firmware.
This section describes how the bootcode initializes the TUSB3410 device in detail. In addition, the default
USB descriptor, I2C device header format, USB host driver firmware downloading format, and supported
built-in USB vendor specific requests are listed for reference. Users should carefully follow the appropriate
format to interface with the bootcode. Unsupported formats may cause unexpected results.
The bootcode source code is also provided for programming reference.
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Bootcode Programming Flow
After power-on reset, the bootcode initializes the I2C and USB registers along with internal variables. The
bootcode then checks to see if an I2C device is present and contains a valid signature. If an I2C device is
present and contains a valid signature, the bootcode continues searching for descriptor blocks and then
processes them if the checksum is correct. If application firmware was found, then the bootcode
downloads it and releases the control to the application firmware. Otherwise, the bootcode connects to the
USB and waits for host driver to download application firmware. Once firmware downloading is complete,
the bootcode releases the control to the firmware.
The following is the bootcode step-by-step operation.
Check if bootcode is in the application mode. This is the mode that is entered after application code is
downloaded through either an I2C device or the USB. If the bootcode is in the application mode, then
the bootcode releases the control to the application firmware. Otherwise, the bootcode continues.
Initialize all the default settings.
Call CopyDefaultSettings() routine.
Set I2C to 400-kHz speed.
Call UsbDataInitialization() routine.
Set bFUNADR = 0
Disconnect from USB (bUSBCTL = 0x00)
Bootcode handles USB reset
Copy predefined device, configuration, and string descriptors to RAM
Disable all endpoints and enable USB interrupts (SETUP, RSTR, SUSR, and RESR)
Search for product signature
Check if valid signature is in I2C. If not, skip the I2C process.
Read 2 bytes from address 0x0000 with type III and device address 0. Stop searching if valid
signature is found.
Read 2 bytes from address 0x0000 with type II and device address 4. Stop searching if valid
signature is found.
If a valid I2C signature is found, then load the customized device, configuration and string descriptors
from I2C EEPROM.
Process each descriptor block from I2C until end of header is found
If the descriptor block contains device, configuration, or string descriptors, then the bootcode
overwrites the default descriptors.
If the descriptor block contains binary firmware, then the bootcode sets the header pointer to the
beginning of the binary firmware in the I2C EEPROM.
If the descriptor block is end of header, then the bootcode stops searching.
Enable global and USB interrupts and set the connection bit to 1.
Enable global interrupts by setting bit 7 (EA) within the SIE register (see Section 5.5.9.1.1) to 1.
Enable all internal peripheral interrupts by setting the EX0 bit within the SIE register to 1.
Connect to the USB by setting bit 7 (CONT) within the USBCNTL register (see Section 5.5.5.4) to
1.
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Wait for any interrupt events until Get DEVICE DESCIPTOR setup packet arrives.
Suspend interrupt
The idle bit in the MCU PCON register is set and suspend mode is entered. USB reset wakes up
the microcontroller.
Resume interrupt
Bootcode wakes up and waits for new USB requests.
Reset interrupt
Call UsbReset() routine.
Setup interrupt
Bootcode processes the request.
USB reboot request
Disconnect from the USB by clearing bit 7 (CONT) in the USBCTL register and restart at address
0x0000.
Download firmware from I2C EEPROM
Disable global interrupts by clearing bit 7 (EA) within the SIE register
Load firmware to XDATA space if available.
Download firmware from the USB.
If no firmware is found in an I2C EEPROM, the USB host downloads firmware through output
endpoint 1.
In the first data packet to output endpoint 1, the USB host driver adds 3 bytes before the application
firmware in binary format. These three bytes are the LSB and MSB indicating the firmware size and
followed by the arithmetic checksum of the binary firmware.
Release control to the application firmware.
Update the USB configuration and interface number.
Release control to application firmware.
Application firmware
Either disconnect from the USB or continue responding to USB requests.
Default Bootcode Settings
The bootcode has its own predefined device, configuration, and string descriptors. These default
descriptors should be used in evaluation only. They must not be used in the end-user product.
5.6.3.1
Device Descriptor
The device descriptor provides the USB version that the device supports, device class, protocol, vendor
and product identifications, strings, and number of possible configurations. The operation system
(Windows, MAC, or Linux) reads this descriptor to decide which device driver should be used to
communicate with this device.
The bootcode uses 0x0451 (Texas Instruments) as the vendor ID and 0x3410 (TUSB3410) as the product
ID. It also supports three different strings and one configuration. Table 5-16 lists the device descriptor.
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Table 5-16. Device Descriptor
OFFSET
(decimal)
FIELD
SIZE
VALUE
bLength
0x12
bDescriptorType
bcdUSB
0x0110
bDeviceClass
0xFF
bDeviceSubClass
We have no subclasses.
bDeviceProtocol
We use no protocols.
bMaxPacketSize0
Max. packet size for endpoint zero
idVendor
0x0451
USBassigned vendor ID = TI
10
idProduct
0x3410
TI part number = TUSB3410
12
bcdDevice
0x100
Device release number = 1.0
14
iManufacturer
Index of string descriptor describing manufacturer
15
iProducct
Index of string descriptor describing product
16
iSerialNumber
Index of string descriptor describing the serial number of the device
17
bNumConfigurations
Number of possible configurations
5.6.3.2
DESCRIPTION
Size of this descriptor in bytes
Device descriptor type
USB spec 1.1
Device class is vendorspecific
Configuration Descriptor
The configuration descriptor provides the number of interfaces supported by this configuration, power
configuration, and current consumption.
The bootcode declares only one interface running in bus-powered mode. It consumes up to 100 mA at
boot time. Table 5-17 lists the configuration descriptor.
Table 5-17. Configuration Descriptor
OFFSET
(decimal)
FIELD
SIZE
VALUE
DESCRIPTION
bLength
Size of this descriptor in bytes.
bDescriptor Type
Configuration descriptor type
wTotalLength
bNumInterfaces
Number of interfaces supported by this configuration
bConfigurationVal
ue
Value to use as an argument to the SetConfiguration() request to select this
configuration.
iConfiguration
Index of string descriptor describing this configuration.
Total length of data returned for this configuration. Includes the combined
25 = 9 + 9 + 7 length of all descriptors (configuration, interface, endpoint, and class- or
vendor-specific) returned for this configuration.
Configuration characteristics:
7
70
bmAttributes
bMaxPower
Detailed Description
0x80
0x32
D7:
Reserved (set to one)
D6:
Self-powered
D5:
Remote wake up is supported
D40:
Reserved (reset to zero)
This device consumes 100 mA.
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Interface Descriptor
The interface descriptor provides the number of endpoints supported by this interface as well as interface
class, subclass, and protocol.
The bootcode supports only one endpoint and use its own class. Table 5-18 lists the interface descriptor.
Table 5-18. Interface Descriptor
OFFSET
(decimal)
FIELD
SIZE
VALUE
bLength
Size of this descriptor in bytes
bDescriptorType
Interface descriptor type
bInterfaceNumber
Number of interface. Zero-based value identifying the index in the array of
concurrent interfaces supported by this configuration.
bAlternateSetting
Value used to select alternate setting for the interface identified in the prior field
bNumEndpoints
Number of endpoints used by this interface (excluding endpoint zero). If this
value is zero, this interface only uses the default control pipe.
bInterfaceClass
0xFF
bInterfaceSubClass
bInterfaceProtocol
iInterface
5.6.3.4
DESCRIPTION
The interface class is vendor specific.
Index of string descriptor describing this interface
Endpoint Descriptor
The endpoint descriptor provides the type and size of communication pipe supported by this endpoint.
The bootcode supports only one output endpoint with the size of 64 bytes in addition to control endpoint 0
(required by all USB devices). Table 5-19 lists the endpoint descriptor.
Table 5-19. Output Endpoint1 Descriptor
OFFSET
(decimal)
FIELD
SIZE
VALUE
bLength
Size of this descriptor in bytes
bDescriptorType
Endpoint descriptor type
bEndpointAddress
0x01
DESCRIPTION
Bit 30:
The endpoint number
Bit 7:
Direction
0 = OUT endpoint
1 = IN endpoint
Bit 10:
3
bmAttributes
Transfer type
10 = Bulk
11 = Interrupt
wMaxPacketSize
64
Maximum packet size this endpoint is capable of sending or receiving when this
configuration is selected.
bInterval
Interval for polling endpoint for data transfers. Expressed in milliseconds.
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String Descriptor
The string descriptor contains data in the Unicode format. It is used to show the manufacturers name,
product model, and serial number in human readable format.
The bootcode supports three strings. The first string is the manufacturers name. The second string is the
product name. The third string is the serial number. Table 5-20 lists the string descriptor.
Table 5-20. String Descriptor
OFFSET
(decimal)
72
FIELD
SIZE
VALUE
DESCRIPTION
bLength
bDescriptorType
0x03
wLANGID[0]
0x0409
bLength
36 (decimal)
bDescriptorType
0x03
bString
T,0x00
Unicode, T is the first byte
e,0x00
Texas Instruments
10
x,0x00
12
a,0x00
14
s,0x00
16
,0x00
18
I,0x00
20
n,0x00
22
s,0x00
24
t,0x00
26
r,0x00
28
u,0x00
30
m,0x00
32
e,0x00
34
n,0x00
36
t,0x00
38
s,0x00
Size of string 0 descriptor in bytes
String descriptor type
English
Size of string 1 descriptor in bytes
String descriptor type
40
bLength
42 (decimal)
41
bDescriptorType
0x03
Size of string 2 descriptor in bytes
STRING descriptor type
42
bString
T,0x00
UNICODE, T is first byte
44
U,0x00
TUSB3410 boot device
46
S,0x00
48
B,0x00
50
3,0x00
52
4,0x00
54
1,0x00
56
0,0x00
58
,0x00
60
B,0x00
62
o,0x00
64
o,0x00
66
t,0x00
68
,0x00
70
D,0x00
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Table 5-20. String Descriptor (continued)
OFFSET
(decimal)
FIELD
SIZE
VALUE
72
e,0x00
74
v,0x00
76
I,0x00
78
c,0x00
80
e,0x00
82
bLength
34 (decimal)
84
bDescriptorType
0x03
86
bString
DESCRIPTION
Size of string 3 descriptor in bytes
STRING descriptor type
r0,0x00
UNICODE
88
r1,0x00
R0 to rF are BCD of SERNUM0 to
90
r2,0x00
SERNUM7 registers. 16 digit hex
92
r3,0x00
16 digit hex numbers are created from
94
r4,0x00
SERNUM0 to SERNUM7 registers
96
r5,0x00
98
r6,0x00
100
r7,0x00
102
r8,0x00
104
r9,0x00
106
rA,0x00
108
rB,0x00
110
rC,0x00
112
rD,0x00
114
rE,0x00
116
rF,0x00
External I2C Device Header Format
5.6.4
A valid header should contain a product signature and one or more descriptor blocks. The descriptor block
contains the descriptor prefix and content. In the descriptor prefix, the data type, size, and checksum are
specified to describe the content. The descriptor content contains the necessary information for the
bootcode to process.
The header processing routine always counts from the first descriptor block until the desired block number
is reached. The header reads in the descriptor prefix with a size of 4 bytes. This prefix contains the type of
block, size, and checksum. For example, if the bootcode would like to find the position of the third
descriptor block, then it reads in the first descriptor prefix, calculates the position on the second descriptor
prefix based on the size specified in the prefix. bootcode, then repeats the same calculation to find out the
position of the third descriptor block.
5.6.4.1
Product Signature
The product signature must be stored at the first 2 bytes within the I2C storage device. These 2 bytes
must match the product number. The order of these 2 bytes must be the LSB first followed by the MSB.
For example, the TUSB3410 device is 0x3410. Therefore, the first byte must be 0x10 and the second byte
must be 0x34.
The TUSB3410 device bootcode searches the first 2 bytes of the I2C device. If the first 2 bytes are not
0x10 and 0x34, then the bootcode skips the header processing.
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Descriptor Block
Each descriptor block contains a prefix and content. The size of the prefix is always 4 bytes. It contains
the data type, size, and checksum for data integrity. The descriptor content contains the corresponding
information specified in the prefix. It could be as small as 1 byte or as large as 65535 bytes. The next
descriptor immediately follows the previous descriptor. If there are no more descriptors, then an extra byte
with a value of zero should be added to indicate the end of header.
5.6.4.2.1 Descriptor Prefix
The first byte of the descriptor prefix is the data type. This tells the bootcode how to process the data in
the descriptor content. The second and third bytes are the size of descriptor content. The second byte is
the low byte of the size and the third byte is the high byte. The last byte is the 8-bit arithmetic checksum of
descriptor content.
5.6.4.2.2 Descriptor Content
Information stored in the descriptor content can be the USB information, firmware, or other type of data.
The size of the content should be from 1 byte to 65535 bytes.
5.6.5
Checksum in Descriptor Block
Each descriptor prefix contains one checksum of the descriptor content. If the checksum is wrong, the
bootcode simply ignores the descriptor block.
5.6.6
Header Examples
The header can be specified in different ways. The following descriptors show examples of the header
format and the supported descriptor block.
5.6.6.1
TUSB3410 Bootcode Supported Descriptor Block
The TUSB3410 device bootcode supports the following descriptor blocks.
USB Device Descriptor
USB Configuration Descriptor
USB String Descriptor
Binary Firmware (1)
Autoexec Binary Firmware (2)
5.6.6.2
USB Descriptor Header
Table 5-21 contains the USB device, configuration, and string descriptors for the bootcode. The last byte
is zero to indicate the end of header.
Table 5-21. USB Descriptors Header
OFFSET
TYPE
SIZE
VALUE
Signature0
0x10
FUNCTION_PID_L
Signature1
0x34
FUNCTION_PID_H
Data Type
0x03
USB device descriptor
Data Size (low byte)
0x12
The device descriptor is 18 (decimal) bytes.
Data Size (high byte)
0x00
Check Sum
0xCC
Checksum of data below
bLength
0x12
Size of device descriptor in bytes
(1)
(2)
74
DESCRIPTION
Binary firmware is loaded when the bootcode receives the first get device descriptor request from host. Downloading the firmware
should either continue that request in the data stage or disconnect from the USB and then reconnect to the USB as a new device.
The bootcode loads this autoexec binary firmware before it connects to the USB. The firmware should connect to the USB once it is
loaded.
Detailed Description
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Table 5-21. USB Descriptors Header (continued)
OFFSET
TYPE
SIZE
VALUE
bDescriptorType
0x01
DESCRIPTION
Device descriptor type
bcdUSB
0x0110
10
bDeviceClass
0xFF
USB spec 1.1
Device class is vendor-specific
11
bDeviceSubClass
0x00
We have no subclasses.
12
bDeviceProtocol
0x00
We use no protocols
13
bMaxPacketSize0
0x08
Maximum packet size for endpoint zero
14
idVendor
0x0451
USBassigned vendor ID = TI
16
idProduct
0x3410
TI part number = TUSB3410
18
bcdDevice
0x0100
Device release number = 1.0
20
iManufacturer
0x01
Index of string descriptor describing manufacturer
21
iProducct
0x02
Index of string descriptor describing product
22
iSerialNumber
0x03
Index of string descriptor describing devices serial number
23
bNumConfigurations
0x01
Number of possible configurations:
24
Data Type
0x04
USB configuration descriptor
25
Data Size (low byte)
0x19
25 bytes
26
Data Size (high byte)
0x00
27
Check Sum
0xC6
Checksum of data below
28
bLength
0x09
Size of this descriptor in bytes
29
bDescriptorType
0x02
CONFIGURATION descriptor type
Total length of data returned for this configuration. Includes the
combined length of all descriptors (configuration, interface,
endpoint, and class- or vendor-specific) returned for this
configuration.
30
wTotalLength
25(0x19) =
9+9+7
32
bNumInterfaces
0x01
Number of interfaces supported by this configuration
33
bConfigurationValue
0x01
Value to use as an argument to the SetConfiguration() request to
select this configuration
34
iConfiguration
0x00
Index of string descriptor describing this configuration.
Configuration characteristics:
35
36
bmAttributes
0xE0
D7:
Reserved (set to one)
D6:
Self-powered
D5:
Remote wakeup is supported
D40:
Reserved (reset to zero)
bMaxPower
0x64
This device consumes 100 mA.
37
bLength
0x09
Size of this descriptor in bytes
38
bDescriptorType
0x04
INTERFACE descriptor type
39
bInterfaceNumber
0x00
Number of interface. Zero-based value identifying the index in the
array of concurrent interfaces supported by this configuration.
40
bAlternateSetting
0x00
Value used to select alternate setting for the interface identified in
the prior field
41
bNumEndpoints
0x01
Number of endpoints used by this interface (excluding endpoint
zero). If this value is zero, this interface only uses the default
control pipe.
42
bInterfaceClass
0xFF
The interface class is vendor specific.
43
bInterfaceSubClass
0x00
44
bInterfaceProtocol
0x00
45
iInterface
0x00
Index of string descriptor describing this interface
46
bLength
0x07
Size of this descriptor in bytes
47
bDescriptorType
0x05
ENDPOINT descriptor type:
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Table 5-21. USB Descriptors Header (continued)
OFFSET
48
TYPE
bEndpointAddress
SIZE
VALUE
0x01
DESCRIPTION
Bit
30:
The endpoint number
Bit 7:
Direction
0 = OUT endpoint
1 = IN endpoint
Bit
10:
49
bmAttributes
0x02
Transfer Type
10 = Bulk
11 = Interrupt
50
wMaxPacketSize
0x0040
Maximum packet size this endpoint is capable of sending or
receiving when this configuration is selected.
52
bInterval
0x00
Interval for polling endpoint for data transfers. Expressed in
milliseconds.
53
Data Type
0x05
USB String descriptor
54
Data Size (low byte)
0x1A
26(0x1A) = 4 + 6 + 6 + 10
55
Data Size (high byte)
0x00
56
Check Sum
0x50
Checksum of data below
57
bLength
0x04
Size of string 0 descriptor in bytes
58
bDescriptorType
0x03
STRING descriptor type
59
wLANGID[0]
0x0409
61
bLength
0x06
Size of string 1 descriptor in bytes
62
bDescriptorType
0x03
STRING descriptor type
63
bString
T,0x00
UNICODE, T is the first byte.
I,0x00
TI = 0x54, 0x49
0x06
Size of string 2 descriptor in bytes
STRING descriptor type
65
67
bLength
68
bDescriptorType
0x03
69
bString
u,0x00
UNICODE, u is the first byte.
C,0x00
C = 0x75, 0x43
71
73
bLength
0x0A
Size of string 3 descriptor in bytes
74
bDescriptorType
0x03
STRING descriptor type
75
bString
3,0x00
UNICODE, T is the first byte.
77
4,0x00
3410 = 0x33, 0x34, 0x31, 0x30
79
1,0x00
0,0x00
0x00
81
83
76
English
Data Type
Detailed Description
End of header
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Autoexec Binary Firmware
If the application requires firmware loaded prior to establishing a USB connection, then the following
header can be used. The bootcode loads the firmware and releases control to the firmware directly without
connecting to the USB. However, per the USB specification requirement, any USB device should connect
to the bus and respond to the host within the first 100 ms. Therefore, if downloading time is more than 100
ms, the USB and header speed descriptor blocks should be added before the autoexec binary firmware.
Table 5-22 shows an example of autoexec binary firmware header.
Table 5-22. Autoexec Binary Firmware
5.6.7
OFFSET
TYPE
SIZE
VALUE
0x0000
Signature0
0x10
FUNCTION_PID_L
DESCRIPTION
0x0001
Signature1
0x34
FUNCTION_PID_H
0x0002
Data Type
0x07
Autoexec binary firmware
0x0003
Data Size (low
byte)
0x67
0x4567 bytes of application code
0x0004
Data Size (high
byte)
0x45
0x0005
Check Sum
0xNN
0x0006
Program
0x4567
0x456d
Data Type
Checksum of the following firmware
Binary application code
0x00
End of header
USB Host Driver Downloading Header Format
If firmware downloading from the USB host driver is desired, then the USB host driver must follow the
format in Table 5-23. The Texas Instruments bootloader driver generates the proper format. Therefore,
users only need to provide the binary image of the application firmware for the Bootloader. If the
checksum is wrong, then the bootcode disconnects from the USB and waits before it reconnects to the
USB.
Table 5-23. Host Driver Downloading Format
OFFSET
TYPE
SIZE
VALUE
0x0000
Firmware size
(low byte)
0xXX
0x0001
Firmware size
(low byte)
0xYY
0x0002
Checksum
0xZZ
0x0003
Program
0xYYXX
DESCRIPTION
Application firmware size
Checksum of binary application code
Binary application code
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Built-In Vendor Specific USB Requests
The bootcode supports several vendor specific USB requests. These requests are primarily for internal
testing only. These functions should not be used in normal operation.
5.6.8.1
Reboot
The reboot command forces the bootcode to execute.
VARIABLE
5.6.8.2
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
01000000b
bRequest
BTC_REBOOT
0x85
wValue
None
0x0000
wIndex
None
0x0000
wLength
None
0x0000
Data
None
Force Execute Firmware
The force execute firmware command requests the bootcode to execute the downloaded firmware
unconditionally.
VARIABLE
5.6.8.3
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
01000000b
bRequest
BTC_FORCE_EXECUTE_FIRMWARE
0x8F
wValue
None
0x0000
wIndex
None
0x0000
wLength
None
0x0000
Data
None
External Memory Read
The bootcode returns the content of the specified address.
VARIABLE
78
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
11000000b
bRequest
BTC_EXETERNAL_MEMORY_WRITE
0x90
wValue
None
0x0000
wIndex
Data address
0xNNNN (From 0x0000 to 0xFFFF)
wLength
None
0x0000
Data
None
Detailed Description
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External Memory Write
The external memory write command tells the bootcode to write data to the specified address.
VARIABLE
5.6.8.5
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
01000000b
bRequest
BTC_EXETERNAL_MEMORY_WRITE
0x91
wValue
HI: 0x00
LO: Data
0x00NN
wIndex
Data address
0xNNNN (From 0x0000 to 0xFFFF)
wLength
None
0x0000
Data
None
I2C Memory Read
The bootcode returns the content of the specified address in I2C EEPROM.
In the wValue field, the I2C device number is from 0x00 to 0x07 in the high byte. The memory type is from
0x01 to 0x03 for CAT I to CAT III devices. If bit 7 of bValueL is set, then the bus speed is 400 kHz. This
request is also used to set the device number and speed before the I2C write request.
VARIABLE
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
11000000b
bRequest
BTC_I2C_MEMORY_READ
0x92
wValue
I C device number
HI:
Memory type bit[1:0]
LO:
Speed bit[7]
0xXXYY
wIndex
Data address
0xNNNN (From 0x0000 to 0xFFFF)
wLength
1 byte
0x0001
Data
Byte in the specified address
0xNN
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I2C Memory Write
The I2C memory write command tells the bootcode to write data to the specified address.
VARIABLE
5.6.8.7
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
01000000b
bRequest
BTC_I2C_MEMORY_WRITE
0x93
wValue
HI: should be zero
LO: Data
0x00NN
wIndex
Data address
0xNNNN (From 0x0000 to 0xFFFF)
wLength
None
0x0000
Data
None
Internal ROM Memory Read
The bootcode returns the byte of the specified address within the boot ROM. That is, the binary code of
the bootcode.
VARIABLE
5.6.9
CONSTANT NAME
VALUE
bmRequestType
USB_REQ_TYPE_DEVICE |
USB_REQ_TYPE_VENDOR |
USB_REQ_TYPE_OUT
bRequest
BTC_INTERNAL_ROM_MEMORY_RE
0x94
AD
wValue
None
0x0000
wIndex
Data address
0xNNNN (From 0x0000 to 0xFFFF)
wLength
1 byte
0x0001
Data
Byte in the specified address
0xNN
01000000b
Bootcode Programming Consideration
5.6.9.1
USB Requests
For each USB request, the bootcode follows these steps to ensure proper operation of the hardware:
1. Determine the direction of the request by checking the MSB of the bmRequestType field and set the
DIR bit within the USBCTL register accordingly.
2. Decode the command
3. If another setup is pending, then return. Otherwise, serve the request.
4. Check again, if another setup is pending then go to step 2.
5. Clear the interrupt source and then the VECINT register.
6. Exit the interrupt routine.
5.6.9.1.1 USB Request Transfers
The USB request consist of three types of transfers. They are control-read-with-data-stage, control-writewithout-data-stage, and control-write-with-data-stage transfer. In each transfer, arrows indicate interrupts
generated after receiving the setup packet, in or out token.
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Figure 5-13 and Figure 5-14 show the USB data flow and how the hardware and firmware respond to the
USB requests. Table 5-24 and Table 5-25 lists the bootcode reposes to the standard USB requests.
Setup Stage
Data Stage
Setup (0)
IN(1)
More
Packets
IN(0)
INT
INT
INT
1.Hardware generates interrupt to
MCU.
2.Copy data to IN buffer.
3.Clear the NAK bit.
4.If all data has been sent, stall input
endpoint.
1.Hardware generates interrupt
to MCU.
2.Hardware sets NAK on both
the IN and the OUT endpoints.
3.Set DIR bit in USBCTL to
indicate the data direction.
4.Decode the setup packet.
5.If another setup packet
arrives, abandon this one.
6.Execute appropriate routine per
Table 11-9.
a) Clear NAK bit in OUT
endpoint.
b) Copy data to IN endpoint
buffer and set byte count.
StatusStage
IN(0/1)
OUT(1)
INT
1.Hardware does NOT generate
interrupt to MCU.
Figure 5-13. Control Read Transfer
Table 5-24. Bootcode Response to Control Read Transfer
CONTROL READ
ACTION IN BOOTCODE
Get status of device
Return power and remote wake-up settings
Get status of interface
Return 2 bytes of zeros
Get status of endpoint
Return endpoint status
Get descriptor of device
Return device descriptor
Get descriptor of configuration
Return configuration descriptor
Get descriptor of string
Return string descriptor
Get descriptor of interface
Stall
Get descriptor of endpoint
Stall
Get configuration
Return bConfiguredNumber value
Get interface
Return bInterfaceNumber value
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Setup Stage
Status Stage
Setup (0)
IN(1)
INT
1.Hardware generates interrupt
to MCU.
2.Hardware sets NAK on both the IN
and the OUT endpoints.
3.Set DIR bit in USBCTL to
indicate the data direction.
4.Decode the setup packet.
5.If another setup packet
arrives, abandon this one.
6.Execute appropriate routine per
Table 1110.
1.Hardware does NOT generates
interrupt to MCU.
Figure 5-14. Control Write Transfer Without Data Stage
Table 5-25. Bootcode Response to Control Write Without Data Stage
CONTROL WRITE WITHOUT DATA STAGE ACTION IN BOOTCODE
Clear feature of device
Stall
Clear feature of interface
Stall
Clear feature of endpoint
Clear endpoint stall
Set feature of device
Stall
Set feature of interface
Stall
Set feature of endpoint
Stall endpoint
Set address
Set device address
Set descriptor
Stall
Set configuration
Set bConfiguredNumber
Set interface
SetbInterfaceNumber
Sync. frame
Stall
5.6.9.1.2 Interrupt Handling Routine
The higher-vector number has a higher priority than the lower-vector number. Table 5-26 lists all the
interrupts and source of interrupts.
Table 5-26. Vector Interrupt Values and Sources
82
G[3:0]
(Hex)
I[2:0]
(Hex)
No Interrupt
No Source
1
1
1
1
2
3
12
14
16
Outputendpoint1
Outputendpoint2
Outputendpoint3
VECINT register
VECINT register
VECINT register
47
181E
2
2
2
1
2
3
22
24
26
47
282E
Detailed Description
VECTOR
(Hex)
INTERRUPT SOURCE
MUST BE CLEARED
INTERRUPT SOURCE
Reserved
Inputendpoint1
Inputendpoint2
Inputendpoint3
VECINT register
VECINT register
VECINT register
Reserved
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Table 5-26. Vector Interrupt Values and Sources (continued)
G[3:0]
(Hex)
I[2:0]
(Hex)
VECTOR
(Hex)
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
30
32
34
36
38
3A
3C
3E
STPOW packet received
SETUP packet received
Reserved
Reserved
RESR interrupt
SUSR interrupt
RSTR interrupt
Wake-up interrupt
USBSTA
USBSTA
USBSTA
USBSTA
USBSTA
USBSTA
4
4
4
4
0
1
2
3
40
42
44
46
I2C TXE interrupt
I2C TXE interrupt
Inputendpoint0
Outputendpoint0
VECINT register
VECINT register
VECINT register
VECINT register
47
484E
5
5
0
1
50
52
27
545E
6
6
0
1
60
62
27
646E
Reserved
07
707E
Reserved
8
8
8
0
1
2
80
82
84
37
915
07
5.6.9.2
INTERRUPT SOURCE
MUST BE CLEARED
INTERRUPT SOURCE
/ VECINT registers
/ VECINT registers
/
/
/
/
VECINT registers
VECINT registers
VECINT registers
VECINT registers
Reserved
UART1 status interrupt
UART1 modern interrupt
LSR / VECNT register
LSR / VECINT register
Reserved
UART1 RXF interrupt
UART1 TXE interrupt
LSR / VECNT register
LSR / VECINT register
DMA1 interrupt
Reserved
DMA3 interrupt
DMACSR/VECINT register
DMACSR/VECINT register
867E
Reserved
90FE
Reserved
Hardware Reset Introduced by the Firmware
This feature can be used during a firmware upgrade. Once the upgrade is complete, the application
firmware disconnects from the USB for at least 200 ms to ensure the operating system has unloaded the
device driver. The firmware then enables the watchdog timer (enabled by default after power-on reset)
and enters an endless loop without resetting the watchdog timer. Once the watchdog timer times out, it
resets the TUSB3410 device similar to a power on reset. The bootcode takes control and executes the
power-on boot sequence.
5.6.10 File Listings
The TUSB3410 Bootcode Source Listing (SLLC139) is available on the Tools & Software tab of the
TUSB3410 device product page on the TI website. The following files are included in the zip file.
Types.h
USB.h
TUSB3410.h
Bootcode.h
Watchdog.h
Bootcode.c
Bootlsr.c
BootUSB.c
Header.h
Header.c
I2c.h
I2c.c
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6 Application, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1
Application Information
The implementation in Section 6.2 describes the minimum requirements to set up the TUSB3410 device
for use as a basic USB to UART bridge to link the communication of a PC to any serial device through a
USB port (see Figure 6-1).
Figure 6-1. Typical Example for TUSB3410 as USB to UART Bridge
6.2
Typical Application
Figure 6-2. USB to UART Implementation
84
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Design Requirements
Table 6-1 lists the design parameters for the typical application shown in Section 6.2.
Table 6-1. Design Parameters
DESIGN PARAMETER
6.2.2
VALUE
VCC Supply
3.3 V
VDD1/8
1.8 V
Upstream port USB (HS, FS)
HS, FS
RS-232 Transceivers
RS-232
XTAL
12 MHz
Detailed Design Procedure
6.2.2.1
Upstream Port Implementation
Figure 6-3 shows how the upstream of the TUSB3410 device is connected to a USB-2.0 Type B
connector. The VBUS of the USB-2.0 connector is connected to a 3.3-V voltage regulator, which
generates the 3.3 V required for VCC. The 3.3 V generated by this voltage regulator will pass through a
voltage divider to generate the 1.8 V that is required for VDD.
Figure 6-3. Upstream Port Implementation Schematic
6.2.2.2
Crystal Implementation
The TUSB3410 device requires a 12-MHz clock source to work properly, which is placed across the X1
and X2 terminals as shown in Figure 6-4.
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TI recommends using a parallel-resonant crystal. Most parallel-resonant crystals are specified at a
frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from
each end of the crystal to ground. Together with the input capacitance of the TUSB3410 device and stray
board capacitance, this setup provides close to two 36-pF capacitors in series to emulate the 18-pF load
requirement.
Figure 6-4. Crystal Implementation Schematic
6.2.2.3
RS-232 Implementation
All the serial data lines and serial control signals (DTR, RTS, SOUT/IR_SOUT, SIN/IR_SIN, RI/CP, DCD,
DSR, and CTS) must go through an RS-232 driver (see Figure 6-5). For this example, the SN75LV4737A
device is used (see SLLS178 for more details about the RS-232 driver). After the RS-232 driver is placed,
the serial data lines and serial control signals are connected to a DB9 connector.
Figure 6-5. RS-232 Implementation Schematic
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TUSB3410 Power Implementation
Figure 6-6 shows the power implementation for the TUSB3410 device.
Figure 6-6. Power Implementation
6.2.3
Application Performance Plot
Figure 6-7. High-Speed Upstream Port
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6.3.1
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Layout
Layout Guidelines
A primary concern when designing a system is accommodating and isolating high-speed signals. As
highspeed signals are most likely to impact or be impacted by other signals, they must be laid out early
(preferably first) in the PCB design process to ensure that prescribed routing rules can be followed.
Table 6-2 outlines the signals requiring the most attention in a USB layout.
Table 6-2. Critical Signals
SIGNAL NAME
DESCRIPTION
DP
USB 2.0 differential pair, positive
DM
USB 2.0 differential pair, negative
SSTXP
SuperSpeed differential pair, TX, positive
SSTXN
SuperSpeed differential pair, TX, negative
SSRXP
SuperSpeed differential pair, RX, positive
SSRXN
SuperSpeed differential pair, RX, negative
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
Place the USB PHY and major components on the un-routed board first.
Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
When it becomes necessary to turn 90, use two 45 turns or an arc instead of making a single 90
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
6.3.2
Differential Signal Spacing
To minimize crosstalk in USB implementations, the spacing between the signal pairs must be a minimum
of 5 times the width of the trace. This spacing is the 5W rule. Also, maintain a minimum keep-out area of
30 mils to any other signal throughout the length of the trace. Where the USB differential pair abuts a
clock or a periodic signal, increase this keep-out to a minimum of 50 mils to ensure proper isolation.
Figure 6-8 shows an example of USB2 differential signal spacing.
Figure 6-8. USB2 Differential Signal Spacing (mils)
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SLLS519I MARCH 2002 REVISED NOVEMBER 2015
Differential Signal Rules
Do not place probe or test points on any USB differential signal.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching power
regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
After BGA breakout, keep USB differential signals clear of the SoC because high current transients
produced during internal state transitions can be difficult to filter out.
When possible, route the USB differential pair signals on the top or bottom layer of the PCB with an
adjacent GND layer. TI does not recommend stripline routing of the USB differential signals.
Ensure that USB differential signals are routed 90 mils from the edge of the reference plane.
Ensure that USB differential signals are routed at least 1.5 W (calculated trace-width 1.5) away from
voids in the reference plane. This rule does not apply where SMD pads on the USB differential signals
are voided.
Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the
transmission lines.
Maximize differential pair-to-pair spacing when possible.
For specific USB-2.0 layout guidelines, refer to USB Layout Guidelines (SPRAAR7).
6.3.4
Layout Example
10
13
11
12
22 pF
33
USB TYPE B
Connector
1
8
TUSB3410
7
6
5
4
3
22 pF
33
1
32
31
29
30
28
Figure 6-9. Layout Example for TUSB3410
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6.4.1
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Power Supply Recommendations
Digital Supplies 3.3 V
The TUSB3410 requires a 3.3-V digital power source.
The 3.3-V terminals are named VCC and supply power to most of the input and output cells. VCC supplies
must have 0.1-F bypass capacitors to VSS (ground) to ensure proper operation. One capacitor per
power terminal is sufficient and should be placed as close to the terminal as possible to minimize trace
length. TI also recommends smaller value capacitors like 0.01-F on the digital supply terminals.
When placing and connecting all bypass capacitors, follow high-speed board design rules.
6.4.2
Digital Supplies 1.8 V
The TUSB3410 requires a 1.8-V digital power source.
The 3.3-V terminals are named VDD18 and supply power to most of the input and output cells. VDD18
supplies must have 0.1-F bypass capacitors to VSS (ground) to ensure proper operation. One capacitor
per power terminal is sufficient and should be placed as close to the terminal as possible to minimize trace
length. TI also recommends smaller value capacitors like 0.01-F on the digital supply terminals.
When placing and connecting all bypass capacitors, follow high-speed board design rules.
An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When
VREGEN is high, 1.8 V must be supplied externally.
6.5
Crystal Selection
The TUSB3410 device requires a 12-MHz clock source to work properly (see Figure 6-10). This clock
source can be a crystal placed across the X1 and X2 terminals. A parallel resonant crystal is
recommended. Most parallel resonant crystals are specified at a frequency with a load capacitance of
18 pF. This load can be realized by placing 33-pF capacitors from each end of the crystal to ground.
Together with the input capacitance of the TUSB3410 device and stray board capacitance, this provides
close to two 36-pF capacitors in series to emulate the 18-pF load requirement.
NOTE
When using a crystal, it takes about 2 ms after power up for a stable clock to be produced.
When using a clock oscillator, the signal applied to the X1/CLKI terminal must not exceed 1.8 V. In this
configuration, the X2 terminal is unconnected.
TUSB3410
33 pF
X2
33 pF
12 MHz
X1/CLKI
Figure 6-10. Crystal Selection
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6.6
SLLS519I MARCH 2002 REVISED NOVEMBER 2015
External Circuit Required for Reliable Bus Powered Suspend Operation
TI has found a potential problem with the action of the SUSPEND output terminal immediately after power
on. In some cases the SUSPEND terminal can power up asserted high. When used in a bus powered
application this can cause a problem because the VREGEN input is usually connected to the SUSPEND
output. This in turn causes the internal 1.8-V voltage regulator to shut down, which means an external
crystal may not have time to begin oscillating, thus the device will not initialize itself correctly.
TI has determined that using components R2 and D1 (rated to 25 mA) in the circuit shown in Figure 6-11
can be used as a workaround.
NOTE
R1 and C1 are required components for proper reset operation, unless the reset signal is
provided by another means.
Use of an external oscillator (1.8-V output) versus a crystal would avoid this situation. Selfpowered applications would probably not see this problem because the VREGEN input
would likely be tied low, enabling the internal 1.8-V regulator at all times.
3.3 V
TUSB3410
R1
15 k
RESET
R2
32 k
VREGEN
C1
1 F
D1
SUSPEND
Figure 6-11. External Circuit
Application, Implementation, and Layout
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7 Device and Documentation Support
7.1
Documentation Support
7.1.1
Related Documentation
For related documentation, see the following:
7.2
SLLS178
SN75LV4737A 3.3-V/5-V Multichannel RS-232 Line Driver/Receiver
SPRAAR7
USB Layout Guidelines
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
7.3
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TUSB3410
Click here
Click here
Click here
Click here
Click here
TUSB3410I
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
7.4
Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.5
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical Packaging and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TUSB3410IRHB
ACTIVE
VQFN
RHB
32
73
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3410I
TUSB3410IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3410I
TUSB3410IRHBRG4
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3410I
TUSB3410IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3410I
TUSB3410IVF
ACTIVE
LQFP
VF
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB3410I
TUSB3410IVFG4
ACTIVE
LQFP
VF
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TUSB3410I
TUSB3410RHB
ACTIVE
VQFN
RHB
32
73
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3410
TUSB3410RHBG4
ACTIVE
VQFN
RHB
32
73
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3410
TUSB3410RHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3410
TUSB3410RHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3410
TUSB3410VF
ACTIVE
LQFP
VF
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB3410
TUSB3410VFG4
ACTIVE
LQFP
VF
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB3410
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TUSB3410 :
Automotive: TUSB3410-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TUSB3410IRHBR
VQFN
RHB
32
TUSB3410IRHBT
VQFN
RHB
TUSB3410RHBR
VQFN
RHB
TUSB3410RHBT
VQFN
RHB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TUSB3410IRHBR
VQFN
RHB
32
3000
338.1
338.1
20.6
TUSB3410IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
TUSB3410RHBR
VQFN
RHB
32
3000
338.1
338.1
20.6
TUSB3410RHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF002B JANUARY 1995 REVISED MAY 2000
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,25
0,80
24
0,20 M
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,05 MIN
0,25
0 7
1,45
1,35
Seating Plane
0,75
0,45
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
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concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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Applications
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