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Lecture-43 Intel 8255A: Programming and Operating Modes

This is a device initiated p controlled I/O transfer. A p may be communicating other time. In the case of CPU initiated polled I/O transfer. Polling of I/O service request flags monopolizes a significant amount of a microprocessor time. This reduces system through put the total useful information processed or communicated during a specified time period therefore, it is advantageous, in term of increasing throughput as well as reducing program complexity, if an I/O device demands service directly from the microprocessor. Interrupts provide this capability essentially an interrupt is a subroutine call initiated by external hardware device and is asynchronous meaning it can be initiated at any time without reference to the system clock however, the response to an interrupt is directed or controlled by the p. A simple structure that allows a

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61 views

Lecture-43 Intel 8255A: Programming and Operating Modes

This is a device initiated p controlled I/O transfer. A p may be communicating other time. In the case of CPU initiated polled I/O transfer. Polling of I/O service request flags monopolizes a significant amount of a microprocessor time. This reduces system through put the total useful information processed or communicated during a specified time period therefore, it is advantageous, in term of increasing throughput as well as reducing program complexity, if an I/O device demands service directly from the microprocessor. Interrupts provide this capability essentially an interrupt is a subroutine call initiated by external hardware device and is asynchronous meaning it can be initiated at any time without reference to the system clock however, the response to an interrupt is directed or controlled by the p. A simple structure that allows a

Uploaded by

Osy Osy
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Lecture-43

Intel 8255A: Programming and Operating Modes

The format for the control word is,

Single bit/set/Reset feature:


Any of the right bits of PORT C can be set (High) or Reset
(Low) using a single OUTPUT instruction without affecting other bits.
This feature reduces software requirement in control based
application. When PORT C is being used as status /control for PORT

A or B, these bit can be set or reset by using the bit set/reset


operation just as if they were data output ports. The bit set/reset
format is given below:

An example for interfacing 8255A with CPU:


If 8255 is programmed in isolated I/O mapped manner, then IN &OUT
instructions are used for data transfer. When these instruction are
executed the 8085 A duplicates the PORT number on the address
bus and on the address data bus. Thus,
A15 A8 = AD7 AD0
This equation is called the duplication equation. Therefore PORT A is
read if
A15 A8 = AD7 AD0
XXXXXX 00

We may allocate any address to 8255. Let us assume A15- A11 bits to
be 00000 for generating the chip select signal along with IO/

= 1.

Therefore PORT A is accessed when address bus is having A15- A8


be 00000X00. Therefore, primary addr for PORT A is 00H and fold
back addr is 04H.The PORT B , PORT C and control register are
selected with address 01(05),02(06) fold back address. Normally
primary addresses are used.

Example:
Configure 8255 A in following I/O mode.
PORT A; Input; POET B: output
PCU output; PCL: Input

The control word with I/O modes as mode0 will be


1 00 1 00 012 = 91H
The control word will be outputted to control word register having add
03H.The relevant instruction will be follows:
MVI A, 91H
OUT 03H
For the above example, set bit PC0 High through bit set/reset. Note
PCU is configured in output mode. Only the bit of the PORT C,
configured in output mode can be set/reset. The relevant control word
will be 0XXX 110 1 = 0DH. The instructions to SET the port bit PC1
will be
MVI A, 0DH
OUT 03H
Operating Modes:

Mode0 (Basic Input/output)


This mode provides simple input/output operation for three ports.
After the mode is set, data is simple read from or written to the ports.
The mode0 functional definitions are,
1. Any poet can be input or output.
2. Two 8-bit ports and two 4-bit ports.
3. Outputs are latched.
4. Inputs are not latched.
5. 16 different 2 input/output configurations are possible.
6. Writing to the mode register resets any bits that are output.

Mode 1 (Strobed Input/Output Mode)


In this mode data can be transformed to and from 8255A with the use
of handshaking signals or strobes. In mode 1, PORT A & PORT B
use the lines of on PORT C to generate or accept these handshaking
signals. The mode 1 functional conditions are as follows.
1. Two groups Group A & Group B can be set independently.
2. Each group contains an 8-bit data port and a 4-bit control/data
port.
3. The 8-bit ports can be used as either input or output. Both input
& output are latched.
4. The 4-bit port is used for control & status of the 8-bit data port.

Strobes Input Mode:


Fig illustrates an 8255 set up with Group A & Group B both in input
strobes mode i.e. Mode1.
Input control signal definitions:
The functions of the port c lines as determined by the mode are as
described below:
PORT C bit 4 (PC4)

Input strobe

is pulsed LOW the data

prevented to the PORT A lines is latched into PORT A latch.


PC5: IBF A
Input buffer full PORT A. This line goes HIGH after the data is strobes
into port A by the
edge of the

signal. The bit becomes LOW by the using

input ie when CPU reads data from PORT D. Their

signal is used to identify when data can be written into PORT A by an


external device.
PC3: INTRA
Interrupt request PORT A. A high on this output can be used to
interrupt the CPU when an input device is requesting service. This
signal will go HIGH after IBFA line goes HIGH;

is HIGH and

interview interrupt enable is set. The interrupt enables is controlled by


the bit set/reset of port C bit 4 (PC4). When this signal is set, INTR
will follow INTA. If the bit reset, INTRA will always be low. INTRA can
therefore be used as a mask able interrupt to the CPU to indicate a
data transferred into port A.
PC2

Input strobe for PORT B.

PC1

Input buffer full port B.

PC0 INTR B Interrupt request PORT B.


Interrupt enable bit is set by PC2
In case PC4/PC2 bit is reset, the concerned interrupt will be disabled.
PORT C bits 6&7 are not used as control or status lines and therefore
they can be used as either input or output bit 3 of the control word
determines whether these lines are input or output.
The control word to program PORT A & B in strobed input mode is
(1 0 11 1 1 1 X) 2 =BAH

Fig shows the timing diagram under strobed input mode. The
pay device that is inputting the data puts the data at PORT A (or
PORT B) pins and then sends a low strobe to indicate to the 8255
that data is available. This loads the data into the concerned input
port buffer. The 8255A acknowledges receiving the data by sending
IBF HIGH back to the peripheral device. When the externally
generated strobe signal goes back to HIGH, the INTR is set high
(provided, if the INTE f/f was initially set to enable the interrupts). This
INTR signal interrupts the CPU (provided the concerned interrupt of
8085 been unmasked earlier). The 8085 CPU when ready, reads
(input) the data into assumable by generating a low
reset to low disabling the interrupt at the start of low
reset to low at the instant of

going high again.

. The INTR is
. The IBF is

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