H8/3644 Series

H8/3644
HD6473644, HD6433644
H8/3643
HD6433643
H8/3642
HD6433642
H8/3641
HD6433641
H8/3640
HD6433640

H8/3644F-ZTAT
HD64F3644

H8/3643F-ZTAT
HD64F3643

H8/3642AF-ZTAT
HD64F3642A
Hardware Manual

ADE-602-087C
Rev. 4.0
08/08/98
Hitachi, Ltd.
MC-Setsu

Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third partys
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachis sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachis sales office for any questions regarding this document or Hitachi
semiconductor products.

Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible
with the H8/300 CPU.
The H8/3644 Series has a system-on-a-chip architecture that includes such peripheral functions as
a D/A converter, five timers, a 14-bit PWM, a two-channel serial communication interface, and an
A/D converter. This makes it ideal for use in advanced control systems.
This manual describes the hardware of the H8/3644 Series. For details on the H8/3644 Series
instruction set, refer to the H8/300L Series Programming Manual.

Contents
Section 1
1.1
1.2
1.3

Overview ...........................................................................................................
Overview............................................................................................................................
Internal Block Diagram .....................................................................................................
Pin Arrangement and Functions ........................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions........................................................................................................

Section 2
2.1

2.2

2.3

2.4

2.5

2.6

2.7

CPU .....................................................................................................................
Overview............................................................................................................................
2.1.1 Features ................................................................................................................
2.1.2 Address Space ......................................................................................................
2.1.3 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
2.2.1 General Registers..................................................................................................
2.2.2 Control Registers..................................................................................................
2.2.3 Initial Register Values ..........................................................................................
Data Formats......................................................................................................................
2.3.1 Data Formats in General Registers.......................................................................
2.3.2 Memory Data Formats..........................................................................................
Addressing Modes .............................................................................................................
2.4.1 Addressing Modes................................................................................................
2.4.2 Effective Address Calculation..............................................................................
Instruction Set....................................................................................................................
2.5.1 Data Transfer Instructions ....................................................................................
2.5.2 Arithmetic Operations ..........................................................................................
2.5.3 Logic Operations ..................................................................................................
2.5.4 Shift Operations....................................................................................................
2.5.5 Bit Manipulations .................................................................................................
2.5.6 Branching Instructions..........................................................................................
2.5.7 System Control Instructions .................................................................................
2.5.8 Block Data Transfer Instruction ...........................................................................
Basic Operational Timing..................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM) .........................................................
2.6.2 Access to On-Chip Peripheral Modules ...............................................................
CPU States .........................................................................................................................
2.7.1 Overview ..............................................................................................................
2.7.2 Program Execution State ......................................................................................
2.7.3 Program Halt State ...............................................................................................
2.7.4 Exception-Handling State ....................................................................................

1
1
5
6
6
9
15
15
15
16
16
17
17
17
19
19
20
21
22
22
24
28
30
32
33
33
35
39
41
42
44
44
45
46
46
48
48
48
i

2.8
2.9

Memory Map ..................................................................................................................... 49

Application Notes.............................................................................................................. 50
2.9.1 Notes on Data Access........................................................................................... 50
2.9.2 Notes on Bit Manipulation ................................................................................... 52
2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 58

Section 3
3.1
3.2

3.3

3.4

Exception Handling........................................................................................
Overview............................................................................................................................
Reset ..................................................................................................................................
3.2.1 Overview ..............................................................................................................
3.2.2 Reset Sequence.....................................................................................................
3.2.3 Interrupt Immediately after Reset ........................................................................
Interrupts............................................................................................................................
3.3.1 Overview ..............................................................................................................
3.3.2 Interrupt Control Registers ...................................................................................
3.3.3 External Interrupts................................................................................................
3.3.4 Internal Interrupts .................................................................................................
3.3.5 Interrupt Operations..............................................................................................
3.3.6 Interrupt Response Time ......................................................................................
Application Notes..............................................................................................................
3.4.1 Notes on Stack Area Use......................................................................................
3.4.2 Notes on Rewriting Port Mode Registers.............................................................

Section 4
4.1

4.2
4.3
4.4
4.5

Clock Pulse Generators .................................................................................

Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
4.1.2 System Clock and Subclock .................................................................................
System Clock Generator....................................................................................................
Subclock Generator ...........................................................................................................
Prescalers ...........................................................................................................................
Note on Oscillators ............................................................................................................

Section 5
5.1
5.2

5.3

ii

59
59
59
59
59
61
61
61
63
72
72
73
78
79
79
80
83
83
83
83
84
87
88
88

Power-Down Modes ...................................................................................... 89

Overview............................................................................................................................ 89
5.1.1 System Control Registers ..................................................................................... 92
Sleep Mode........................................................................................................................ 96
5.2.1 Transition to Sleep Mode ..................................................................................... 96
5.2.2 Clearing Sleep Mode ............................................................................................ 96
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode.............................................. 96
Standby Mode.................................................................................................................... 97
5.3.1 Transition to Standby Mode ................................................................................. 97
5.3.2 Clearing Standby Mode........................................................................................ 97
5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 98

5.4

5.5

5.6

5.7

5.8

Watch Mode ......................................................................................................................

5.4.1 Transition to Watch Mode....................................................................................
5.4.2 Clearing Watch Mode ..........................................................................................
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................
Subsleep Mode ..................................................................................................................
5.5.1 Transition to Subsleep Mode................................................................................
5.5.2 Clearing Subsleep Mode ......................................................................................
Subactive Mode .................................................................................................................
5.6.1 Transition to Subactive Mode ..............................................................................
5.6.2 Clearing Subactive Mode .....................................................................................
5.6.3 Operating Frequency in Subactive Mode .............................................................
Active (Medium-Speed) Mode..........................................................................................
5.7.1 Transition to Active (Medium-Speed) Mode .......................................................
5.7.2 Clearing Active (Medium-Speed) Mode..............................................................
5.7.3 Operating Frequency in Active (Medium-Speed) Mode......................................
Direct Transfer...................................................................................................................

Section 6
6.1
6.2

6.3

6.4

6.5

6.6

6.7

99
99
99
99
100
100
100
101
101
101
101
102
102
102
102
103

ROM ................................................................................................................... 105

Overview............................................................................................................................
6.1.1 Block Diagram......................................................................................................
PROM Mode......................................................................................................................
6.2.1 Setting to PROM Mode........................................................................................
6.2.2 Socket Adapter Pin Arrangement and Memory Map ...........................................
Programming .....................................................................................................................
6.3.1 Writing and Verifying ..........................................................................................
6.3.2 Programming Precautions ....................................................................................
6.3.3 Reliability of Programmed Data ..........................................................................
Flash Memory Overview ...................................................................................................
6.4.1 Principle of Flash Memory Operation..................................................................
6.4.2 Mode Pin Settings and ROM Space .....................................................................
6.4.3 Features ................................................................................................................
6.4.4 Block Diagram......................................................................................................
6.4.5 Pin Configuration .................................................................................................
6.4.6 Register Configuration .........................................................................................
Flash Memory Register Descriptions ................................................................................
6.5.1 Flash Memory Control Register (FLMCR)..........................................................
6.5.2 Erase Block Register 1 (EBR1)............................................................................
6.5.3 Erase Block Register 2 (EBR2)............................................................................
On-Board Programming Modes ........................................................................................
6.6.1 Boot Mode............................................................................................................
6.6.2 User Program Mode .............................................................................................
Programming and Erasing Flash Memory.........................................................................
6.7.1 Program Mode......................................................................................................

105
105
106
106
106
108
109
112
113
113
113
114
115
116
117
117
118
118
120
121
123
123
128
130
130
iii

6.8

6.9

6.7.2 Program-Verify Mode ..........................................................................................

6.7.3 Programming Flowchart and Sample Program ....................................................
6.7.4 Erase Mode...........................................................................................................
6.7.5 Erase-Verify Mode ...............................................................................................
6.7.6 Erase Flowcharts and Sample Programs ..............................................................
6.7.7 Prewrite-Verify Mode ..........................................................................................
6.7.8 Protect Modes.......................................................................................................
6.7.9 Interrupt Handling during Flash Memory Programming/Erasing........................
Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF) ...........................
6.8.1 PROM Mode Setting............................................................................................
6.8.2 Socket Adapter and Memory Map .......................................................................
6.8.3 Operation in PROM Mode ...................................................................................
Flash Memory Programming and Erasing Precautions .....................................................

131
132
135
135
136
149
149
150
151
151
151
154
163

Section 7
7.1

RAM ................................................................................................................... 169

Overview............................................................................................................................ 169
7.1.1 Block Diagram...................................................................................................... 169

Section 8
8.1
8.2

8.3

8.4

8.5

iv

I/O Ports ............................................................................................................

Overview............................................................................................................................
Port 1..................................................................................................................................
8.2.1 Overview ..............................................................................................................
8.2.2 Register Configuration and Description...............................................................
8.2.3 Pin Functions........................................................................................................
8.2.4 Pin States ..............................................................................................................
8.2.5 MOS Input Pull-Up ..............................................................................................
Port 2..................................................................................................................................
8.3.1 Overview ..............................................................................................................
8.3.2 Register Configuration and Description...............................................................
8.3.3 Pin Functions........................................................................................................
8.3.4 Pin States ..............................................................................................................
Port 3..................................................................................................................................
8.4.1 Overview ..............................................................................................................
8.4.2 Register Configuration and Description...............................................................
8.4.3 Pin Functions........................................................................................................
8.4.4 Pin States ..............................................................................................................
8.4.5 MOS Input Pull-Up ..............................................................................................
Port 5..................................................................................................................................
8.5.1 Overview ..............................................................................................................
8.5.2 Register Configuration and Description...............................................................
8.5.3 Pin Functions........................................................................................................
8.5.4 Pin States ..............................................................................................................
8.5.5 MOS Input Pull-Up ..............................................................................................

171
171
173
173
173
177
178
178
179
179
179
181
181
182
182
182
186
187
187
188
188
188
190
191
191

8.6

Port 6..................................................................................................................................
8.6.1 Overview ..............................................................................................................
8.6.2 Register Configuration and Description...............................................................
8.6.3 Pin Functions........................................................................................................
8.6.4 Pin States ..............................................................................................................
8.7 Port 7..................................................................................................................................
8.7.1 Overview ..............................................................................................................
8.7.2 Register Configuration and Description...............................................................
8.7.3 Pin Functions........................................................................................................
8.7.4 Pin States ..............................................................................................................
8.8 Port 8..................................................................................................................................
8.8.1 Overview ..............................................................................................................
8.8.2 Register Configuration and Description...............................................................
8.8.3 Pin Functions........................................................................................................
8.8.4 Pin States ..............................................................................................................
8.9 Port 9..................................................................................................................................
8.9.1 Overview ..............................................................................................................
8.9.2 Register Configuration and Description...............................................................
8.9.3 Pin Functions........................................................................................................
8.9.4 Pin States ..............................................................................................................
8.10 Port B .................................................................................................................................
8.10.1 Overview ..............................................................................................................
8.10.2 Register Configuration and Description...............................................................
8.10.3 Pin Functions........................................................................................................
8.10.4 Pin States ..............................................................................................................

192
192
192
193
194
195
195
195
197
197
198
198
198
200
201
202
202
202
204
204
205
205
205
206
206

Section 9

207
207
208
208
210
212
213
214
214
215
217
218
219
219
222
228
233

9.1
9.2

9.3

9.4

Timers ................................................................................................................
Overview............................................................................................................................
Timer A..............................................................................................................................
9.2.1 Overview ..............................................................................................................
9.2.2 Register Descriptions............................................................................................
9.2.3 Timer Operation ...................................................................................................
9.2.4 Timer A Operation States.....................................................................................
Timer B1............................................................................................................................
9.3.1 Overview ..............................................................................................................
9.3.2 Register Descriptions............................................................................................
9.3.3 Timer Operation ...................................................................................................
9.3.4 Timer B1 Operation States ...................................................................................
Timer V..............................................................................................................................
9.4.1 Overview ..............................................................................................................
9.4.2 Register Descriptions............................................................................................
9.4.3 Timer Operation ...................................................................................................
9.4.4 Timer V Operation Modes....................................................................................

9.5

9.6

9.4.5 Interrupt Sources ..................................................................................................

9.4.6 Application Examples ..........................................................................................
9.4.7 Application Notes.................................................................................................
Timer X..............................................................................................................................
9.5.1 Overview ..............................................................................................................
9.5.2 Register Descriptions............................................................................................
9.5.3 CPU Interface .......................................................................................................
9.5.4 Timer Operation ...................................................................................................
9.5.5 Timer X Operation Modes....................................................................................
9.5.6 Interrupt Sources ..................................................................................................
9.5.7 Timer X Application Example .............................................................................
9.5.8 Application Notes.................................................................................................
Watchdog Timer................................................................................................................
9.6.1 Overview ..............................................................................................................
9.6.2 Register Descriptions............................................................................................
9.6.3 Timer Operation ...................................................................................................
9.6.4 Watchdog Timer Operation States .......................................................................

233
234
236
242
242
246
257
260
267
267
268
269
274
274
275
278
279

Section 10 Serial Communication Interface ................................................................ 281

10.1 Overview............................................................................................................................ 281
10.2 SCI1 ................................................................................................................................... 281
10.2.1 Overview .............................................................................................................. 281
10.2.2 Register Descriptions............................................................................................ 284
10.2.3 Operation in Synchronous Mode.......................................................................... 288
10.2.4 Operation in SSB Mode........................................................................................ 291
10.2.5 Interrupts .............................................................................................................. 293
10.3 SCI3 ................................................................................................................................... 293
10.3.1 Overview .............................................................................................................. 293
10.3.2 Register Descriptions............................................................................................ 296
10.3.3 Operation .............................................................................................................. 314
10.3.4 Operation in Asynchronous Mode........................................................................ 318
10.3.5 Operation in Synchronous Mode.......................................................................... 327
10.3.6 Multiprocessor Communication Function............................................................ 334
10.3.7 Interrupts .............................................................................................................. 341
10.3.8 Application Notes................................................................................................. 342

Section 11 14-Bit PWM ..................................................................................................... 347

11.1 Overview............................................................................................................................
11.1.1 Features ................................................................................................................
11.1.2 Block Diagram......................................................................................................
11.1.3 Pin Configuration .................................................................................................
11.1.4 Register Configuration ........................................................................................
11.2 Register Descriptions.........................................................................................................
vi

347
347
347
348
348
348

11.2.1 PWM Control Register (PWCR).......................................................................... 348

11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 349
11.3 Operation ........................................................................................................................... 350

Section 12 A/D Converter ................................................................................................. 351

12.1 Overview............................................................................................................................
12.1.1 Features ................................................................................................................
12.1.2 Block Diagram......................................................................................................
12.1.3 Pin Configuration .................................................................................................
12.1.4 Register Configuration .........................................................................................
12.2 Register Descriptions.........................................................................................................
12.2.1 A/D Result Register (ADRR)...............................................................................
12.2.2 A/D Mode Register (AMR)..................................................................................
12.2.3 A/D Start Register (ADSR)..................................................................................
12.3 Operation ...........................................................................................................................
12.3.1 A/D Conversion Operation...................................................................................
12.3.2 Start of A/D Conversion by External Trigger Input.............................................
12.4 Interrupts............................................................................................................................
12.5 Typical Use........................................................................................................................
12.6 Application Notes..............................................................................................................

351
351
352
353
353
354
354
354
356
357
357
357
358
358
361

Section 13 Electrical Characteristics .............................................................................. 363

13.1 Absolute Maximum Ratings..............................................................................................
13.2 Electrical Characteristics (ZTAT, Mask ROM Version)...............................................
13.2.1 Power Supply Voltage and Operating Range.......................................................
13.2.2 DC Characteristics (HD6473644) ........................................................................
13.2.3 AC Characteristics (HD6473644) ........................................................................
13.2.4 DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641,
HD6433640) .........................................................................................................
13.2.5 AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641,
HD6433640) .........................................................................................................
13.2.6 A/D Converter Characteristics .............................................................................
13.3 Electrical Characteristics (F-ZTAT Version) ................................................................
13.3.1 Power Supply Voltage and Operating Range.......................................................
13.3.2 DC Characteristics (HD64F3644, HD64F3643, HD64F3642A) .........................
13.3.3 AC Characteristics (HD64F3644, HD64F3643, HD64F3642A) .........................
13.3.4 A/D Converter Characteristics .............................................................................
13.4 Operation Timing ..............................................................................................................
13.5 Output Load Circuit...........................................................................................................

363
364
364
367
373
376
381
385
386
386
389
395
398
399
402

Appendix A CPU Instruction Set.................................................................................... 403

A.1
A.2

Instructions ........................................................................................................................ 403

Operation Code Map.......................................................................................................... 411
vii

A.3

Number of Execution States.............................................................................................. 413

Appendix B Internal I/O Registers ................................................................................. 420

B.1
B.2

Addresses........................................................................................................................... 420
Functions............................................................................................................................ 424

Appendix C I/O Port Block Diagrams .......................................................................... 471

C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9

Block Diagrams of Port 1 ..................................................................................................

Block Diagrams of Port 2 ..................................................................................................
Block Diagrams of Port 3 ..................................................................................................
Block Diagrams of Port 5 ..................................................................................................
Block Diagram of Port 6....................................................................................................
Block Diagrams of Port 7 ..................................................................................................
Block Diagrams of Port 8 ..................................................................................................
Block Diagram of Port 9....................................................................................................
Block Diagram of Port B ...................................................................................................

471
475
478
481
484
485
489
497
498

Appendix D Port States in the Different Processing States .................................... 499

Appendix E Product Code Lineup ................................................................................. 500
Appendix F

viii

Package Dimensions .................................................................................. 501

Section 1 Overview
1.1

Overview

The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3644 Series of microcomputers are equipped with a UART
(Universal Asynchronous Receiver/Transmitter). Other on-chip peripheral functions include five
timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, and
an A/D converter, providing an ideal configuration as a microcomputer for embedding in highlevel control systems. In addition to the mask ROM version, the H8/3644 is also available in a
ZTAT*1 version with on-chip user-programmable PROM, and an F-ZTAT*2 version with onchip flash memory that can be programmed on-board. Table 1 summarizes the features of the
H8/3644 Series.
Notes: 1. ZTAT is a trademark of Hitachi, Ltd.
2. F-ZTAT is a registered trademark of Hitachi, Ltd.

Table 1.1

Features

Item

Description

CPU

High-speed H8/300L CPU

General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)

Operating speed
Max. operation speed: 5 MHz (mask ROM and ZTAT versions)
8 MHz (F-ZTAT version)
Add/subtract: 0.4 s (operating at = 5 MHz)
0.25 s (operating at = 8 MHz)
Multiply/divide: 2.8 s (operating at = 5 MHz)
1.75 s (operating at = 8 MHz)
Can run on 32.768 kHz subclock

Instruction set compatible with H8/300 CPU

Instruction length of 2 bytes or 4 bytes
Basic arithmetic operations between registers
MOV instruction for data transfer between memory and registers

Typical instructions
Multiply (8 bits 8 bits)
Divide (16 bits 8 bits)
Bit accumulator
Register-indirect designation of bit position

Interrupts

Clock pulse
generators

Power-down
modes

33 interrupt sources

12 external interrupt sources (IRQ 3 to IRQ 0, INT7 to INT0)

21 internal interrupt sources

Two on-chip clock pulse generators

System clock pulse generator:

Crystal or ceramic resonator:

2 to 10 MHz (2 to 16 MHz)*

External clock input:

1 to 10 MHz (1 to 16 MHz)*

1 to 10 MHz (1 to 16 MHz)*

Seven power-down modes

Sleep (high-speed) mode

Sleep (medium-speed) mode

Standby mode

Watch mode

Subsleep mode

Subactive mode

Active (medium-speed) mode

Note: * Values in parentheses are for the F-ZTAT version.
2

Table 1.1

Features (cont)

Item

Description

Memory

Large on-chip memory

I/O ports

Timers

H8/3644: 32-kbyte ROM, 1-kbyte RAM

H8/3643: 24-kbyte ROM, 1-kbyte RAM

H8/3642: 16-kbyte ROM, 512 byte RAM (1-kbyte RAM F-ZTAT version)

H8/3641: 12-kbyte ROM, 512 byte RAM

H8/3640: 8-kbyte ROM, 512 byte RAM

53 pins

45 I/O pins

8 input pins

Five on-chip timers

Timer A: 8-bit timer

Count-up timer with selection of eight internal clock signals divided from the
system clock ()* and four clock signals divided from the watch clock (w )*

Timer B1: 8-bit timer

Count-up timer with selection of seven internal clock signals or event
input from external pin
Auto-reloading

Timer V: 8-bit timer

Count-up timer with selection of six internal clock signals or event input
from external pin
Compare-match waveform output
Externally triggerable

Timer X: 16-bit timer

Count-up timer with selection of three internal clock signals or event
input from external pin
Output compare (2 output pins)
Input capture (4 input pins)

Watchdog timer
Reset signal generated by 8-bit counter overflow

Note: * and W are defined in section 4, Clock Pulse Generators.

Table 1.1

Features (cont)

Item

Description

Serial
communication
interface

Two on-chip serial communication interface channels

SCI1: synchronous serial interface

Choice of 8-bit or 16-bit data transfer

SCI3: 8-bit synchronous/asynchronous serial interface

Incorporates multiprocessor communication function

14-bit PWM

Pulse-division PWM output for reduced ripple

A/D converter

Can be used as a 14-bit D/A converter by connecting to an external low-pass

filter.

Successive approximations using a resistance ladder

8-channel analog input pins

Conversion time: 31/ or 62/ per channel

Product lineup

Product Code
Mask ROM
Version

ZTAT
Version

HD6433644H
HD6433644P

F-ZTAT
Version

Package

ROM/RAM Size

HD6473644H HD64F3644H

64-pin QFP (FP-64A)

HD6473644P HD64F3644P

64-pin SDIP (DP-64S)

ROM: 32 kbytes
RAM: 1 kbyte

HD6433644W HD6473644W HD64F3644W

80-pin TQFP (TFP-80C)

HD6433643H

HD64F3643H

64-pin QFP (FP-64A)

HD6433643P

HD64F3643P

64-pin SDIP (DP-64S)

HD6433643W

HD64F3643W

80-pin TQFP (TFP-80C)

HD6433642H

HD64F3642AH 64-pin QFP (FP-64A)

ROM: 16 kbytes

HD6433642P

HD64F3642AP

RAM: 512 kbytes

64-pin SDIP (DP-64S)

ROM: 24 kbytes
RAM: 1 kbyte

HD6433642W

HD64F3642AW 80-pin TQFP (TFP-80C) RAM: 1 kbyte

(F-ZTAT version)

HD6433641H

64-pin QFP (FP-64A)

HD6433641P

64-pin SDIP (DP-64S)

HD6433641W

80-pin TQFP (TFP-80C)

HD6433640H

64-pin QFP (FP-64A)

HD6433640P

64-pin SDIP (DP-64S)

HD6433640W

80-pin TQFP (TFP-80C)

ROM: 12 kbytes
RAM: 512 bytes

ROM: 8 kbytes
RAM: 512 bytes

1.2

Internal Block Diagram

Timer B1

SCI3

Port 8

SCI1

Port 7

Timer A

P77
P76/TMOV
P75/TMCIV
P74/TMRIV
P73

Port 6

P30/SCK1
P31/SI1
P32/SO1

RAM

P67
P66
P65
P64
P63
P62
P61
P60

Port 5

Port 1

P20/SCK3
P21/RXD
P22/TXD

ROM

P87
P86/FTID
P85/FTIC
P84/FTIB
P83/FTIA
P82/FTOB
P81/FTOA
P80/FTCI

P57/INT7
P56/INT6/TMIB
P55/INT5/ADTRG
P54/INT4
P53/INT3
P52/INT2
P51/INT1
P50/INT0

Port 3

P10/TMOW
P14/PWM
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV

Port 2

Data bus (lower)

Data bus (upper)

CPU
H8/300L

Address bus

VSS
VCC
RES
IRQ0
TEST

X1
X2
Subclock
generator

System clock
generator

OSC1
OSC2

Figure 1.1 shows a block diagram of the H8/3644 Series.

Timer X

P90/FVPP*
P91
P92
P93
P94

Port 9

Timer V

Watchdog
timer

14-bit PWM

A/D converter

CMOS largecurrent port

IOL= 10 mA
@VOL= 1V

PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7

AVCC
AVSS

Port B

Note: * There is no P90 function in the flash memory version.

Figure 1.1 Block Diagram

5

1.3

Pin Arrangement and Functions

1.3.1

Pin Arrangement

PB3/AN3

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

AVCC

P17/IRQ3/TRGV

P16/IRQ2

P15/IRQ1

P14/PWM

P10/TMOW

P30/SCK1

P31/SI1

P32/SO1

P22/TXD

62

61

60

59

58

57

56

55

54

53

52

51

50

49

PB0/AN0

64

PB2/AN2
PB1/AN1

64

The H8/3644 Series pin arrangement is shown in figures 1.2 (FP-64A), 1.3 (DP-64S), and 1.4
(TFP-80C).

48

P21/RXD

47

P20/SCK3

AVSS

46

P87

TEST

45

P86/FTID

X2

44

P85/FTIC

X1

43

P84/FTIB

VSS

42

P83/FTIA

OSC1

41

P82/FTOB

OSC2

40

P81/FTOA

RES

10

39

P80/FTCI

P90/FVPP*

11

38

P77

26

27

28

29

30

31

32

P51/INT1

P52/INT2

P53/INT3

P54/INT4

P55/INT5/ADTRG

P56/INT6/TMIB

P57/INT7

P60

25

VCC

24

33

P67

16

P50/INT0

IRQ0

23

P73

P66

34
22

15

P65

P94

21

P74/TMRIV

20

35

P64

14

P63

P93

19

P75/TMCIV

P62

P76/TMOV

36

18

37

13

P61

12

17

P91
P92

Note: * There is no P90 function in the flash memory version.

Figure 1.2 Pin Arrangement (FP-64A: Top View)

6

P17/IRQ3/TRGV

64

P16/IRQ2

AVCC

63

P15/IRQ1

PB7/AN7

62

P14/PWM

PB6/AN6

61

P10/TMOW

PB5/AN5

60

P30/SCK1

PB4/AN4

59

P31/SI1

PB3/AN3

58

P32/SO1

PB2/AN2

57

P22/TXD

PB1/AN1

56

P21/RXD

PB0/AN0

10

55

P20/SCK3

AVSS

11

54

P87

TEST

12

53

P86/FTID

X2

13

52

P85/FTIC

X1

14

51

P84/FTIB

VSS

15

50

P83/FTIA

OSC1

16

49

P82/FTOB

OSC2

17

48

P81/FTOA

RES

18

47

P80/FTCI

P90/FVPP*

19

46

P77

P91

20

45

P76/TMOV

P92

21

44

P75/TMCIV

P93

22

43

P74/TMRIV

P94

23

42

P73

IRQ0

24

41

VCC

P60

25

40

P57/INT7

P61

26

39

P56/INT6/TMIB

P62

27

38

P55/INT5/ADTRG

P63

28

37

P54/INT4

P64

29

36

P53/INT3

P65

30

35

P52/INT2

P66

31

34

P51/INT1

P67

32

33

P50/INT0

Note: * There is no P90 function in the flash memory version.

Figure 1.3 Pin Arrangement (DP-64S: Top View)

7

NC
NC
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
AVCC
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1
P14/PWM
P10/TMOW
P30/SCK1
P31/SI1
P32/SO1
P22/TXD
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

NC
P60
P61
P62
P63
P64
P65
P66
P67
NC
P50/INT0
P51/INT1
P52/INT2
P53/INT3
P54/INT4
P55/INT5/ADTRG
P56/INT6/TMIB
P57/INT7
NC
NC

NC
PB1/AN1
PB0/AN0
AVSS
TEST
X2
X1
VSS1
OSC1
OSC2
VSS2
RES
P90/FVPP*
P91
P92
NC
P93
P94
IRQ0
NC

Note: * There is no P90 function in the flash memory version.

Figure 1.4 Pin Arrangement (TFP-80C: Top View)

NC
P21/RXD
P20/SCK3
P87
P86/FTID
P85/FTIC
P84/FTIB
NC
P83/FTIA
P82/FTOB
P81/FTOA
P80/FTCI
NC
P77
P76/TMOV
P75/TMCIV
P74/TMRIV
P73
VCC
NC

1.3.2

Pin Functions

Table 1.2 outlines the pin functions of the H8/3644 Series.

Table 1.2

Pin Functions
Pin No.

Type

Symbol

FP-64A

DP-64S

TFP-80C I/O

Name and Functions

33

41

42

Input

Power supply: All V CC pins

should be connected to the user
system VCC.

VSS

15

8, 11

Input

Ground: All V SS pins should be

connected to the user system
GND.

AVCC

58

72

Input

Analog power supply: This is

the power supply pin for the A/D
converter. When the A/D
converter is not used, connect
this pin to the user system VCC.

AVSS

11

Input

Analog ground: This is the A/D

converter ground pin. It should be
connected to the user system
GND.

OSC 1

16

Input

OSC 2

17

10

Output

System clock: These pins

connect to a crystal or ceramic
oscillator, or can be used to input
an external clock.
See section 4, Clock Pulse
Generators, for a typical
connection diagram.

X1

14

Input

X2

13

Output

RES

10

18

12

Input

Reset: When this pin is driven

low, the chip is reset

TEST

12

Input

Test: This is a test pin, not for

use in application systems. It
should be connected to V SS .

Power
VCC
source pins

Clock pins

System
control

Subclock: These pins connect to

a 32.768-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical
connection diagram.

Table 1.2

Pin Functions (cont)

Pin No.

Type

Symbol

Interrupt
pins

Timer pins

10

FP-64A

DP-64S

TFP-80C I/O

IRQ0
IRQ1
IRQ2
IRQ3

16
55
56
57

24
63
64
1

19
69
70
71

Input

IRQ interrupt request 0 to 3:

These are input pins for edgesensitive external interrupts, with
a selection of rising or falling
edge

Name and Functions

INT7 to
INT0

32 to 25

40 to 33

38 to 31

Input

INT interrupt request 0 to 7:

These are input pins for edgesensitive external interrupts, with
a selection of rising or falling
edge

TMOW

53

61

67

Output

Clock output: This is an output

pin for waveforms generated by
the timer A output circuit

TMIB

31

39

37

Input

Timer B1 event counter input:

This is an event input pin for input
to the timer B1 counter

TMOV

37

45

46

Output

Timer V output: This is an output

pin for waveforms generated by
the timer V output compare
function

TMCIV

36

44

45

Input

Timer V event input: This is an

event input pin for input to the
timer V counter

TMRIV

35

43

44

Input

Timer V counter reset: This is a

counter reset input pin for timer V

TRGV

57

71

Input

Timer V counter trigger input:

This is a trigger input pin for the
timer V counter and realtime
output port

FTCI

39

47

49

Input

Timer X clock input: This is an

external clock input pin for input
to the timer X counter

FTOA

40

48

50

Output

Timer X output compare A

output: This is an output pin for
timer X output compare A

FTOB

41

49

51

Output

Timer X output compare B

output: This is an output pin for
timer X output compare B

Table 1.2

Pin Functions (cont)

Pin No.

Type

Symbol

FP-64A

DP-64S

TFP-80C I/O

Name and Functions

Timer pins

FTIA

42

50

52

Input

Timer X input capture A input:

This is an input pin for timer X
input capture A

FTIB

43

51

54

Input

Timer X input capture B input:

This is an input pin for timer X
input capture B

FTIC

44

52

55

Input

Timer X input capture C input:

This is an input pin for timer X
input capture C

FTID

45

53

56

Input

Timer X input capture D input:

This is an input pin for timer X
input capture D

14-bit
PWM pin

PWM

54

62

68

Output

14-bit PWM output: This is an

output pin for waveforms
generated by the 14-bit PWM

I/O ports

PB7 to
PB0

59 to 64, 3 to 10
1 to 2

73 to 78
2, 3

Input

Port B: This is an 8-bit input port

P17 to
P14,
P10

57 to 53

1,
64 to 61

71 to 67

I/O

Port 1: This is a 5-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 1 (PCR1)

P22 to
P20

49 to 47

57 to 55

63, 59
58

I/O

Port 2: This is a 3-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 2 (PCR2)

P32 to
P30

50 to 52

58 to 60

64 to 66

I/O

Port 3: This is a 3-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 3 (PCR3)

P57 to
P50

32 to 25

40 to 33

38 to 31

I/O

Port 5: This is an 8-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 5 (PCR5)

P67 to
P60

24 to 17

32 to 25

29 to 22

I/O

Port 6: This is an 8-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 6 (PCR6)

11

Table 1.2

Pin Functions (cont)

Pin No.

Type

Symbol

FP-64A

DP-64S

TFP-80C I/O

Name and Functions

I/O ports

P77 to
P73

38 to 34

46 to 42

47 to 43

I/O

Port 7: This is a 5-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 7 (PCR7)

P87 to
P80

46 to 39

54 to 47

57 to 54, I/O
52 to 49

Port 8: This is an 8-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 8 (PCR8)

P94 to
P90

15 to 11

23 to 19

18, 17
15 to 13

Port 9: This is a 5-bit I/O port.

Input or output can be designated
for each bit by means of port
control register 9 (PCR9)

I/O

Note: There is no P9 0 function in

the flash memory version
since P9 0 is used as the
FV PP pin.
Serial com- SI 1
munication
interface
SO1
(SCI)

A/D
converter

12

51

59

65

Input

SCI1 receive data input:

This is the SCI1 data input pin

50

58

64

Output

SCI1 transmit data output:

This is the SCI1 data output pin

SCK 1

52

60

66

I/O

SCI1 clock I/O:

This is the SCI1 clock I/O pin

RXD

48

56

59

Input

SCI3 receive data input:

This is the SCI3 data input pin

TXD

49

57

63

Output

SCI3 transmit data output:

This is the SCI3 data output pin

SCK 3

47

55

58

I/O

SCI3 clock I/O:

This is the SCI3 clock I/O pin

AN 7 to
AN 0

59 to 64, 3 to 10
1 to 2

73 to 78
2, 3

Input

Analog input channels 11 to 0:

These are analog data input
channels to the A/D converter

ADTRG

30

36

Input

A/D converter trigger input:

This is the external trigger input
pin to the A/D converter

38

Table 1.2

Pin Functions (cont)

Pin No.

Type

Symbol

FP-64A

DP-64S

TFP-80C I/O

Name and Functions

Flash
memory

FV PP

11

19

13

On-board-programmable flash
memory power supply:
Connected to the flash memory
programming power supply
(+12 V). When the flash memory
is not being programmed,
connect to the user system VCC.
In versions other than the on-chip
flash memory version, this pin is
P90

Other

NC

1, 16,
20, 21,
30, 39,
40, 41,
48, 53,
60 to 62,
79, 80

Input

Non-connected pins: These

pins must be left unconnected

13

Section 2 CPU
2.1

Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1

Features

Features of the H8/300L CPU are listed below.

General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
Instruction set with 55 basic instructions, including:
Multiply and divide instructions
Powerful bit-manipulation instructions
Eight addressing modes
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment or pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
64-kbyte address space
High-speed operation
All frequently used instructions are executed in two to four states
High-speed arithmetic and logic operations
8- or 16-bit register-register add or subtract: 0.4 s (operating at = 5 MHz)
0.25 s (operating at = 8 MHz)*
8 8-bit multiply:
2.8 s (operating at = 5 MHz)
1.75 s (operating at = 8 MHz)*
16 8-bit divide:
2.8 s (operating at = 5 MHz)
1.75 s (operating at = 8 MHz)*
Note: * F-ZTAT version only.
Low-power operation modes
SLEEP instruction for transfer to low-power operation
Note: * These values are at = 5 MHz.
15

2.1.2

Address Space

The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and
data.
See 2.8, Memory Map, for details of the memory map.
2.1.3

Register Configuration

Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7

0 7

R0H

R0L

R1H

R1L

R2H

R2L

R3H

R3L

R4H

R4L

R5H

R5L

R6H

R6L

R7H

(SP)

SP: Stack pointer

R7L

Control registers (CR)

15

0
PC
7 6 5 4 3 2 1 0
CCR I U H U N Z V C

PC: Program counter

CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit

Figure 2.1 CPU Registers

16

2.2

Register Descriptions

2.2.1

General Registers

All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area

Upper address side [H'FFFF]

Figure 2.2 Stack Pointer

2.2.2

Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of
the PC is ignored (always regarded as 0).

17

Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,
ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for
conditional branching (Bcc) instructions.
Bit 7Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written by
software. For further details, see section 3.3, Interrupts.
Bit 6User Bit (U): Can be used freely by the user.
Bit 5Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4User Bit (U): Can be used freely by the user.
Bit 3Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift/rotate carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.

18

2.2.3

Initial Register Values

In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000)
load, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not
initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be
initialized by software, by the first instruction executed after a reset.

2.3

Data Formats

The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
The H8/300L CPU can process 1-bit, 4-bit BCD, 8-bit (byte), and 16-bit (word) data. 1-bit data is
handled by bit manipulation instructions, and is accessed by being specified as bit n (n = 0, 1, 2, ...
7) in the operand data (byte).
Byte data is handled by all arithmetic and logic instructions except ADDS and SUBS. Word data
is handled by the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU ( b bits 8 bits),
and DIVXU (16 bits 8 bits) instructions.
With the DAA and DAS decimal adjustment instructions, byte data is handled as two 4-bit BCD
data units.

19

2.3.1

Data Formats in General Registers

Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type

Register No.

Data Format

1-bit data

RnH

1-bit data

RnL

Byte data

RnH

Byte data

RnL

Word data

Rn

4-bit BCD data

RnH

4-bit BCD data

RnL

dont care

dont care

MSB

LSB

dont care

dont care

MSB

LSB

15

MSB

LSB

Upper digit

0
Lower digit

dont care

dont care

4
Upper digit

Legend:
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit

Figure 2.3 General Register Data Formats

20

3
Lower digit

2.3.2

Memory Data Formats

Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data
stored in memory must always begin at an even address. When word data beginning at an odd
address is accessed, the least significant bit is regarded as 0, and the word data beginning at the
preceding address is accessed. The same applies to instruction codes.
Data Type

Address

Data Format

1-bit data

Address n

Byte data

Address n

MSB

Even address

MSB

Word data

Odd address

Byte data (CCR) on stack

Word data on stack

0
LSB

Upper 8 bits
Lower 8 bits

LSB

MSB

CCR

LSB

Odd address

MSB

CCR*

LSB

Even address

MSB

Even address

Odd address

LSB

CCR: Condition code register

Note: * Ignored on return

Figure 2.4 Memory Data Formats

When the stack is accessed using R7 as an address register, word access should always be
performed. The CCR is stored as word data with the same value in the upper 8 bits and the lower 8
bits. On return, the lower 8 bits are ignored.

21

2.4

Addressing Modes

2.4.1

Addressing Modes

The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1

Addressing Modes

No.

Address Modes

Symbol

Register direct

Rn

Register indirect

@Rn

Register indirect with displacement

@(d:16, Rn)

Register indirect with post-increment

Register indirect with pre-decrement

@Rn+
@Rn

Absolute address

@aa:8 or @aa:16

Immediate

#xx:8 or #xx:16

Program-counter relative

@(d:8, PC)

Memory indirect

@@aa:8

1. Register DirectRn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits 8 bits), and
DIVXU (16 bits 8 bits) instructions have 16-bit operands.
2. Register Indirect@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.

22

4. Register Indirect with Post-Increment or Pre-Decrement@Rn+ or @Rn:

Register indirect with post-increment@Rn+

The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address
of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B
or 2 for MOV.W, and the result of the addition is stored in the register. For MOV.W, the
original contents of the 16-bit general register must be even.

Register indirect with pre-decrement@Rn

The @Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.

5. Absolute Address@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate#xx:8 or #xx:16: The second byte (#xx:8) or the third and fourth bytes (#xx:16)
of the instruction code are used directly as the operand. Only MOV.W instructions can be used
with #xx:16.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address, and the PC
contents to be added are the start address of the next instruction, so that the possible branching
range is 126 to +128 bytes (63 to +64 words) from the branch instruction. The displacement
should be an even number.

23

8. Memory Indirect@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. This specifies an
operand in memory, and a branch is performed with the contents of this operand as the branch
address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2

Effective Address Calculation

Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit
position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct
addressing (1) to specify the bit position.

24

Table 2.2

Effective Address Calculation

No.

Addressing Mode and

Instruction Format

Register indirect, Rn

Effective Address
Calculation Method

Effective Address (EA)

3

rm
15

87

op

43

rm

Operand is contents of
registers indicated by rm/rn
15

0
Contents (16 bits) of
register indicated by rm

76 43

op
3

15

15

15

15

rm

Register indirect with

displacement, @(d:16, Rn)
15

rn

rn

Register indirect, @Rn

15

76 43

op

15

0
Contents (16 bits) of
register indicated by rm

rm

disp

disp
4

Register indirect with

post-increment, @Rn+
15

76 43

op

15

0
Contents (16 bits) of
register indicated by rm

rm
1 or 2

Register indirect with

pre-decrement, @Rn
15

76 43

op

rm

15

0
Contents (16 bits) of
register indicated by rm

Incremented or
decremented by 1 if
operand is byte size, 1 or 2
and by 2 if word size

25

Table 2.2
No.
5

Effective Address Calculation (cont)

Addressing Mode and

Instruction Format

Effective Address
Calculation Method

Effective Address (EA)

Absolute address
@aa:8
15

87

op

15

87

H'FF
0

abs

@aa:16
15

15

op
abs
6

Immediate
#xx:8
15

Operand is 1- or 2-byte
immediate data
87

op

IMM

#xx:16
15

op
IMM
7

Program-counter relative
@(d:8, PC)

15

87

op

26

disp

15

PC contents
15

Sign
extension

disp

Table 2.2

Effective Address Calculation (cont)

No.

Addressing Mode and

Instruction Format

Memory indirect, @@aa:8

15

87

op

Effective Address
Calculation Method

Effective Address (EA)

abs
15

87

H'00

abs
15

Memory contents
(16 bits)
Legend:
rm, rn: Register field
op:
Operation field
disp: Displacement
IMM: Immediate data
abs: Absolute address

27

2.5

Instruction Set

The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3

Instruction Set

Function

Instructions

Number
1

Data transfer

MOV, PUSH* , POP*

Arithmetic operations

ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,

SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG

14

Logic operations

AND, OR, XOR, NOT

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,

ROTXL, ROTXR

Bit manipulation

BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,

BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST

14

Branch

Bcc*2, JMP, BSR, JSR, RTS

System control

RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP

Block data transfer

EEPMOV

1
Total: 55

Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @SP.

POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is a conditional branch instruction. The same applies to machine language.

Tables 2.4 to 2.11 show the function of each instruction. The notation used is defined next.

28

Notation
Rd

General register (destination)

Rs

General register (source)

Rn

General register

(EAd), <Ead>

Destination operand

(EAs), <Eas>

Source operand

CCR

Condition code register

N (negative) flag of CCR

Z (zero) flag of CCR

V (overflow) flag of CCR

C (carry) flag of CCR

PC

Program counter

SP

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

Subtraction

Multiplication

Division

AND logical

OR logical

Exclusive OR logical

Move

Logical negation (logical complement)

:3

3-bit length

:8

8-bit length

:16

16-bit length

( ), < >

Contents of operand indicated by effective address

29

2.5.1

Data Transfer Instructions

Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4

Data Transfer Instructions

Instruction

Size*

Function

MOV

B/W

(EAs) Rd, Rs (EAd)

Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @Rn, and @Rn+
addressing modes are available for word data. The @aa:8 addressing
mode is available for byte data only.
The @R7 and @R7+ modes require a word-size specification.

POP

@SP+ Rn
Pops a general register from the stack. Equivalent to MOV.W @SP+,
Rn.

PUSH

Rn @SP
Pushes general register onto the stack. Equivalent to MOV.W Rn,
@SP.

Notes: * Size: Operand size

B:
Byte
W:
Word

Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.

30

15

op

rm

15

MOV
RmRn

op
15

rn

rm

rn

rm

rn

rm

rn

@RmRn

op

@(d:16, Rm)Rn

disp
15

op
15

op

rn

15

@Rm+Rn, or
Rn @Rm

abs
8

@aa:8Rn

op

rn

@aa:16Rn

abs
15

op

rn

15

IMM
8

#xx:8Rn

op

rn

#xx:16Rn

IMM
15

op

rn

PUSH, POP
@SP+ Rn, or
Rn @SP

Legend:
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data

Figure 2.5 Data Transfer Instruction Codes

31

2.5.2

Arithmetic Operations

Table 2.5 describes the arithmetic instructions.

Table 2.5

Arithmetic Instructions

Instruction

Size*

ADD

B/W

SUB

ADDX

Rd 1 Rd, Rd 2 Rd
Adds or subtracts 1 or 2 to or from a general register

DAS
MULXU

Rd 1 Rd
Increments or decrements a general register

SUBS
DAA

Rd Rs C Rd, Rd #IMM C Rd
Performs addition or subtraction with carry on data in two general
registers, or addition or subtraction with carry on immediate data and
data in a general register.

DEC
ADDS

Rd Rs Rd, Rd + #IMM Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.

SUBX

INC

Function

Rd decimal adjust Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR

Rd Rs Rd
Performs 8-bit 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result

DIVXU

Rd Rs Rd
Performs 16-bit 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder

CMP

B/W

Rd Rs, Rd #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the CCR.
Word data can be compared only between two general registers.

NEG

0 Rd Rd
Obtains the twos complement (arithmetic complement) of data in a
general register

Notes: * Size: Operand size

B:
Byte
W:
Word
32

2.5.3

Logic Operations

Table 2.6 describes the four instructions that perform logic operations.
Table 2.6

Logic Operation Instructions

Instruction

Size*

Function

AND

Rd Rs Rd, Rd #IMM Rd
Performs a logical AND operation on a general register and another
general register or immediate data

OR

Rd Rs Rd, Rd #IMM Rd
Performs a logical OR operation on a general register and another
general register or immediate data

XOR

Rd Rs Rd, Rd #IMM Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data

NOT

~ Rd Rd
Obtains the ones complement (logical complement) of general
register contents

Notes: * Size: Operand size

B:
Byte

2.5.4

Shift Operations

Table 2.7 describes the eight shift instructions.

Table 2.7

Shift Instructions

Instruction

Size*

SHAL

SHAR
SHLL

Rd shift Rd
Performs a logical shift operation on general register contents

ROTR
ROTXL

Rd shift Rd
Performs an arithmetic shift operation on general register contents

SHLR
ROTL

Function

Rd rotate Rd
Rotates general register contents

ROTXR

Rd rotate Rd
Rotates general register contents through the C (carry) bit

Notes: * Size: Operand size

B:
Byte
33

Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15

op

rm

15

op
15

rm
8

op

rn

op

rm
8

op

AND, OR, XOR (Rm)

0

IMM
8

op

rn

rn

15

ADD, ADDX, SUBX,

CMP (#XX:8)

IMM
8

15

MULXU, DIVXU
0

rn

15

ADDS, SUBS, INC, DEC,

DAA, DAS, NEG, NOT

rn

op
15

ADD, SUB, CMP,

ADDX, SUBX (Rm)

rn

AND, OR, XOR (#xx:8)

rn

SHAL, SHAR, SHLL, SHLR,

ROTL, ROTR, ROTXL, ROTXR

Legend:
op:
Operation field
rm, rn: Register field
IMM: Immediate data

Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes

34

2.5.5

Bit Manipulations

Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8

Bit-Manipulation Instructions

Instruction

Size*

BSET

Function
1 (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.

BCLR

0 (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.

BNOT

~ (<bit-No.> of <EAd>) (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory. The bit number
is specified by 3-bit immediate data or the lower three bits of a
general register.

BTST

~ (<bit-No.> of <EAd>) Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.

BAND

C (<bit-No.> of <EAd>) C
ANDs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.

BIAND

C [~ (<bit-No.> of <EAd>)] C
ANDs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.

BOR

C (<bit-No.> of <EAd>) C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.

BIOR

C [~ (<bit-No.> of <EAd>)] C
ORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.

Notes: * Size: Operand size

B:
Byte

35

Table 2.8

Bit-Manipulation Instructions (cont)

Instruction

Size*

Function

BXOR

C (<bit-No.> of <EAd>) C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.

BIXOR

C [~(<bit-No.> of <EAd>)] C
XORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.

BLD

(<bit-No.> of <EAd>) C
Copies a specified bit in a general register or memory to the C flag.

BILD

~ (<bit-No.> of <EAd>) C
Copies the inverse of a specified bit in a general register or memory
to the C flag.
The bit number is specified by 3-bit immediate data.

BST

C (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.

BIST

~ C (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.

Notes: * Size: Operand size

B:
Byte

Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for
details.

36

BSET, BCLR, BNOT, BTST

15

op

IMM

15

op

rm

15

op
8

Operand: register direct (Rn)

Bit No.: register direct (Rm)

rn

op

15

Operand: register direct (Rn)

Bit No.: immediate (#xx:3)

rn

rn

0 Operand: register indirect (@Rn)

IMM

0 Bit No.:

immediate (#xx:3)

op

rn

0 Operand: register indirect (@Rn)

op

rm

0 Bit No.:

15

op

abs

op

IMM

15

Operand: absolute (@aa:8)

0

0 Bit No.:

immediate (#xx:3)

op

abs

op

register direct (Rm)

rm

Operand: absolute (@aa:8)

0

0 Bit No.:

register direct (Rm)

BAND, BOR, BXOR, BLD, BST

15

op

IMM

15

op
op
15

Operand: register direct (Rn)

Bit No.: immediate (#xx:3)

rn
0

rn

0 Operand: register indirect (@Rn)

IMM

0 Bit No.:

op

abs

op

immediate (#xx:3)

IMM

Operand: absolute (@aa:8)

0

0 Bit No.:

immediate (#xx:3)

Legend:
Operation field
op:
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data

Figure 2.7 Bit Manipulation Instruction Codes

37

BIAND, BIOR, BIXOR, BILD, BIST

15

op

IMM

15

op
op
15

Operand: register direct (Rn)

Bit No.: immediate (#xx:3)

rn
0

rn

0 Operand: register indirect (@Rn)

IMM

0 Bit No.:

op

abs

op

immediate (#xx:3)

IMM

Operand: absolute (@aa:8)

0

0 Bit No.:

immediate (#xx:3)

Legend:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data

Figure 2.7 Bit Manipulation Instruction Codes (cont)

38

2.5.6

Branching Instructions

Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9

Branching Instructions

Instruction

Size*

Function

Bcc

Branches to the designated address if condition cc is true. The

branching conditions are given below.
Mnemonic

Description

Condition

BRA (BT)

Always (true)

Always

BRN (BF)

Never (false)

Never

BHI

High

CZ=0

BLS

Low or same

CZ=1

BCC (BHS)

Carry clear (high or same)

C=0

BCS (BLO)

Carry set (low)

C=1

BNE

Not equal

Z=0

BEQ

Equal

Z=1

BVC

Overflow clear

V=0

BVS

Overflow set

V=1

BPL

Plus

N=0

BMI

Minus

N=1

BGE

Greater or equal

NV=0

BLT

Less than

NV=1

BGT

Greater than

Z (N V) = 0

BLE

Less or equal

Z (N V) = 1

JMP

Branches unconditionally to a specified address

BSR

Branches to a subroutine at a specified address

JSR

Branches to a subroutine at a specified address

RTS

Returns from a subroutine

39

15

op

cc

15

disp
8

op

rm

15

Bcc

JMP (@Rm)

op
JMP (@aa:16)

abs
15

op

abs

15

JMP (@@aa:8)

op

disp

15

op

rm

15

BSR

JSR (@Rm)

op
JSR (@aa:16)

abs
15

op

abs

15

op
Legend:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address

Figure 2.8 Branching Instruction Codes

40

JSR (@@aa:8)
0

RTS

2.5.7

System Control Instructions

Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction

Size*

Function

RTE

Returns from an exception-handling routine

SLEEP

Causes a transition from active mode to a power-down mode. See

section 5, Power-Down Modes, for details.

LDC

Rs CCR, #IMM CCR

Moves immediate data or general register contents to the condition
code register

STC

CCR Rd
Copies the condition code register to a specified general register

ANDC

CCR #IMM CCR

Logically ANDs the condition code register with immediate data

ORC

CCR #IMM CCR

Logically ORs the condition code register with immediate data

XORC

CCR #IMM CCR

Logically exclusive-ORs the condition code register with immediate
data

NOP

PC + 2 PC
Only increments the program counter

Notes: * Size: Operand size

B:
Byte

41

15

op
15

RTE, SLEEP, NOP

7

op
15

rn
8

op

LDC, STC (Rn)

0

IMM

ANDC, ORC,
XORC, LDC (#xx:8)

Legend:
op: Operation field
rn: Register field
IMM: Immediate data

Figure 2.9 System Control Instruction Codes

2.5.8

Block Data Transfer Instruction

Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction

Size

Function

EEPMOV

If R4L 0 then
repeat @R5+ @R6+
R4L 1 R4L
until
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.

Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the
EEPMOV Instruction, for details.

42

15

op
op
Legend:
op: Operation field

Figure 2.10 Block Data Transfer Instruction Code

43

2.6

Basic Operational Timing

CPU operation is synchronized by a system clock () or a subclock (SUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of or SUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1

Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
T1 state

T2 state

or SUB

Internal address bus

Address

Internal read signal

Internal data bus
(read access)

Read data

Internal write signal

Internal data bus
(write access)

Write data

Figure 2.11 On-Chip Memory Access Cycle

44

2.6.2

Access to On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used.
Two-State Access to On-Chip Peripheral Modules: Figure 2.12 shows the operation timing in
the case of two-state access to an on-chip peripheral module.
Bus cycle
T1 state

T2 state

or SUB

Internal address bus

Address

Internal read signal

Internal data bus
(read access)

Read data

Internal write signal

Internal data bus
(write access)

Write data

Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)

45

Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in
the case of three-state access to an on-chip peripheral module.
Bus cycle
T1 state

T2 state

T3 state

or SUB

Internal
address bus

Address

Internal
read signal
Internal
data bus
(read access)

Read data

Internal
write signal
Internal
data bus
(write access)

Write data

Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)

2.7

CPU States

2.7.1

Overview

There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.

46

CPU state

Reset state
The CPU is initialized
Program
execution state

Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock

Program halt state

A state in which some
or all of the chip
functions are stopped
to conserve power

Low-power
modes

Sleep (high-speed)
mode
Sleep (medium-speed)
mode

Standby mode

Watch mode

Subsleep mode

Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.

Figure 2.14 CPU Operation States

47

Reset cleared
Reset state

Exception-handling state
Reset occurs

Reset
occurs

Reset
occurs

Interrupt
source

Program halt state

Exception- Exceptionhandling
handling
request
complete

Program execution state

SLEEP instruction executed

Figure 2.15 State Transitions

2.7.2

Program Execution State

In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3

Program Halt State

In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4

Exception-Handling State

The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.

48

2.8

Memory Map

Figure 2.16 shows a memory map of the H8/3644 Series.

H'0000
H'002F
H'0030
H'1FFF

H8/3640
Interrupt vectors

H8/3641

H8/3642

H8/3643

H8/3644

8 kbytes
12 kbytes
16 kbytes

H'2FFF
24 kbytes
H'3FFF

32 kbytes

On-chip ROM
H'5FFF

H'7FFF

Reserved

H'F770
H'F77F

Internal I/O registers

(16 bytes)
Reserved

H'FB80
H'FD7F
H'FD80
H'FF7F
H'FF80

On-chip RAM
512 bytes

512 bytes

512 bytes

1 kbyte

1 kbyte

Reserved
H'FF9F
H'FFA0
H'FFFF

Internal I/O registers

(128 bytes)

Figure 2.16 H8/3644 Series Memory Map

49

2.9

Application Notes

2.9.1

Notes on Data Access

1. Access to empty areas

The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by
an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Access to internal I/O registers
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of states
in which on-chip peripheral modules can be accessed.

50

Access
Word Byte States
H'0000
H'002F
H'0030

Interrupt vector area

(48 bytes)

2
On-chip ROM

H'7FFF

Reserved

Internal I/O registers

(16 bytes)

Reserved

H'F770
3*

H'F77F

H'FB80
On-chip RAM

1,024 bytes

H'FF7F
H'FF80
H'FF9F

Reserved

Internal I/O registers

(96 bytes)

H'FFA0
2 or 3*

H'FFFF
Notes: The H8/3644 is shown as an example.
* Internal I/O registers in areas assigned to timer X (H'F770 to H'F77F),
SCI3 (H'FFA8 to H'FFAD), and timer V (H'FFB8 to H'FFBD) are accessed in three
states.

Figure 2.17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
51

2.9.2

Notes on Bit Manipulation

The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation

Operation

Read

Read byte data at the designated address

Modify

Modify a designated bit in the read data

Write

Write the altered byte data to the designated address

Bit Manipulation in Two Registers Assigned to the Same Address

Example 1: timer load register and timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation

Operation

Read

Timer counter data is read (one byte)

Modify

The CPU modifies (sets or resets) the bit designated in the instruction

Write

The altered byte data is written to the timer load register

The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.

R
Count clock

Timer counter
R: Read
W: Write

Reload
W
Timer load register

Internal bus

Figure 2.18 Timer Configuration Example

52

Example 2: BSET instruction executed designating port 3

P3 7 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P3 6. The remaining pins, P35 to P30, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30 to high-level output.
[A: Prior to executing BSET]
P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

PCR3

PDR3

[B: BSET instruction executed]

BSET

#0

@PDR3

The BSET instruction is executed designating port 3.

[C: After executing BSET]

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

PCR3

PDR3

[D: Explanation of how BSET operates]

When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P3 5 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3 0 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
53

To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B
MOV. B
MOV. B

#80,
R0L,
R0L,

R0L
@RAM0
@PDR3

The PDR3 value (H'80) is written to a work area in

memory (RAM0) as well as to PDR3.

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

PCR3

PDR3

RAM0

[B: BSET instruction executed]

BSET

#0

@RAM0

The BSET instruction is executed designating the PDR3

work area (RAM0).

[C: After executing BSET]

MOV. B
MOV. B

@RAM0, R0L
R0L, @PDR3

The work area (RAM0) value is written to PDR3.

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

PCR3

PDR3

RAM0

54

Bit Manipulation in a Register Containing a Write-Only Bit

Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a
high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

PCR3

PDR3

[B: BCLR instruction executed]

BCLR

#0

@PCR3

The BCLR instruction is executed designating PCR3.

[C: After executing BCLR]

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Output

Output

Output

Output

Output

Output

Output

Input

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

PCR3

PDR3

[D: Explanation of how BCLR operates]

When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P3 0 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P3 7 and P36 change from input pins to output pins.
55

To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
[A: Prior to executing BCLR]
MOV. B
MOV. B
MOV. B

#3F,
R0L,
R0L,

R0L
@RAM0
@PCR3

The PCR3 value (H'3F) is written to a work area in

memory (RAM0) as well as to PCR3.

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

Low
level

PCR3

PDR3

RAM0

[B: BCLR instruction executed]

BCLR

#0

@RAM0

The BCLR instruction is executed designating the PCR3

work area (RAM0).

[C: After executing BCLR]

MOV. B
MOV. B

@RAM0, R0L
R0L, @PCR3

The work area (RAM0) value is written to PCR3.

P37

P36

P35

P34

P33

P32

P31

P30

Input/output

Input

Input

Output

Output

Output

Output

Output

Output

Pin state

Low
level

High
level

Low
level

Low
level

Low
level

Low
level

Low
level

High
level

PCR3

PDR3

RAM0

56

Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.
Table 2.12 Registers with Shared Addresses
Register Name

Abbreviation

Address

Output compare register AH and output compare register BH (timer X) OCRAH/OCRBH H'F774
Output compare register AL and output compare register BL (timer X)

OCRAL/OCRBL H'F775

Timer counter B1 and timer load register B1 (timer B1)

TCB1/TLB1

H'FFB3

Port data register 1*

PDR1

H'FFD4

Port data register 2*

PDR2

H'FFD5

Port data register 3*

PDR3

H'FFD6

Port data register 5*

PDR5

H'FFD8

Port data register 6*

PDR6

H'FFD9

Port data register 7*

PDR7

H'FFDA

Port data register 8*

PDR8

H'FFDB

Port data register 9*

PDR9

H'FFDC

Note: * Port data registers have the same addresses as input pins.

Table 2.13 Registers with Write-Only Bits

Register Name

Abbreviation

Address

Port control register 1

PCR1

H'FFE4

Port control register 2

PCR2

H'FFE5

Port control register 3

PCR3

H'FFE6

Port control register 5

PCR5

H'FFE8

Port control register 6

PCR6

H'FFE9

Port control register 7

PCR7

H'FFEA

Port control register 8

PCR8

H'FFEB

Port control register 9

PCR9

H'FFEC

PWM control register

PWCR

H'FFD0

PWM data register U

PWDRU

H'FFD1

PWM data register L

PWDRL

H'FFD2

57

2.9.3

Notes on Use of the EEPMOV Instruction

The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5

R6

R5 + R4L

R6 + R4L

When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5

R5 + R4L

58

R6

H'FFFF
Not allowed

R6 + R4L

Section 3 Exception Handling

3.1

Overview

Exception handling is performed in the H8/3644 Series when a reset or interrupt occurs. Table 3.1
shows the priorities of these two types of exception handling.
Table 3.1

Exception Handling Types and Priorities

Priority

Exception Source

Time of Start of Exception Handling

High

Reset

Exception handling starts as soon as the reset state is cleared

Interrupt

When an interrupt is requested, exception handling starts after

execution of the present instruction or the exception handling
in progress is completed

Low

3.2

Reset

3.2.1

Overview

A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2

Reset Sequence

Reset by RES Pin: As soon as the RES pin goes low, all processing is stopped and the chip enters
the reset state.
To make sure the chip is reset properly, observe the following precautions.
At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling begins when the RES pin is held low for a given period, then returned to
the high level.
Reset exception handling takes place as follows.
The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
59

When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.

Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES

Internal
address bus

(1)

(2)

Internal read
signal
Internal write
signal
Internal data
bus (16-bit)

(2)

(3)

(1) Reset exception handling vector address (H'0000)

(2) Program start address
(3) First instruction of program

Figure 3.1 Reset Sequence

Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the
WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows,
the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set
to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see 9.1.1, Watchdog Timer.

60

3.2.3

Interrupt Immediately after Reset

After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.W #xx: 16, SP).

3.3

Interrupts

3.3.1

Overview

The interrupt sources include 12 external interrupts (IRQ3 to IRQ0, INT 7 to INT0) and 21 internal
interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the
highest priority is processed.
The interrupts have the following features:
Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
IRQ3 to IRQ0 and INT7 to INT0 can be set independently to either rising edge sensing or falling
edge sensing.

61

Table 3.2

Interrupt Sources and Their Priorities

Interrupt Source

Interrupt

Vector Number

Vector Address

Priority

RES

Reset

H'0000 to H'0001

High

IRQ0

IRQ0

H'0008 to H'0009

IRQ1

IRQ1

H'000A to H'000B

IRQ2

IRQ2

H'000C to H'000D

IRQ3

IRQ3

H'000E to H'000F

INT0

INT0

H'0010 to H'0011

INT1

INT1

INT2

INT2

INT3

INT3

INT4

INT4

INT5

INT5

INT6

INT6

INT7

INT7

Timer A

Timer A overflow

10

H'0014 to H'0015

Timer B1

Timer B1 overflow

11

H'0016 to H'0017

Timer X input capture A

16

H'0020 to H'0021

17

H'0022 to H'0023

Timer X

Timer X input capture B

Timer X input capture C
Timer X input capture D
Timer X compare match A
Timer X compare match B
Timer X overflow
Timer V

Timer V compare match A

Timer V compare match B
Timer V overflow

SCI1

SCI1 transfer complete

19

H'0026 to H'0027

SCI3

SCI3 transmit end

21

H'002A to H'002B

SCI3 transmit data empty

SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
A/D

A/D conversion end

22

H'002C to H'002D

(SLEEP instruction
executed)

Direct transfer

23

H'002E to H'002F Low

Note: Vector addresses H'0002 to H'0007, H'0012 to H'0013, H'0018 to H'001F, H'0024 to
H'0025, H'0028 to H'0029 are reserved and cannot be used.
62

3.3.2

Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.

Table 3.3

Interrupt Control Registers

Name

Abbreviation

R/W

Initial Value

Address

Interrupt edge select register 1

IEGR1

R/W

H'70

H'FFF2

Interrupt edge select register 2

IEGR2

R/W

H'00

H'FFF3

Interrupt enable register 1

IENR1

R/W

H'10

H'FFF4

Interrupt enable register 2

IENR2

R/W

H'00

H'FFF5

Interrupt enable register 3

IENR3

R/W

H'00

H'FFF6

Interrupt request register 1

IRR1

R/W*

H'10

H'FFF7

Interrupt request register 2

IRR2

R/W*

H'00

H'FFF8

Interrupt request register 3

IRR3

R/W*

H'00

H'FFF9

Note: * Write is enabled only for writing of 0 to clear a flag.

Interrupt Edge Select Register 1 (IEGR1)

Bit

IEG3

IEG2

IEG1

IEG0

Initial value

Read/Write

R/W

R/W

R/W

R/W

IEGR1 is an 8-bit read/write register used to designate whether pins IRQ3 to IRQ0 are set to rising
edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.
Bit 7Reserved Bit: Bit 7 is reserved: it is always read as 0 and cannot be modified.
Bits 6 to 4Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bit 3IRQ3 Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ3.
Bit 3: IEG3

Description

Falling edge of IRQ3 pin input is detected

Rising edge of IRQ3 pin input is detected

(initial value)

63

Bit 2IRQ2 Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ2.
Bit 2: IEG2

Description

Falling edge of IRQ2 pin input is detected

Rising edge of IRQ2 pin input is detected

(initial value)

Bit 1IRQ1 Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1.
Bit 1: IEG1

Description

Falling edge of IRQ1 pin input is detected

Rising edge of IRQ1 pin input is detected

(initial value)

Bit 0IRQ0 Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ0.
Bit 0: IEG0

Description

Falling edge of IRQ0 pin input is detected

Rising edge of IRQ0 pin input is detected

64

(initial value)

Interrupt Edge Select Register 2 (IEGR2)

Bit

INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

IEGR2 is an 8-bit read/write register, used to designate whether pins INT 7 to INT 0, TMIY, and
TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to
H'00.
Bit 7INT7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT7 pin and TMIY
pin.
Bit 7: INTEG7

Description

Falling edge of INT7 and TMIY pin input is detected

Rising edge of INT7 and TMIY pin input is detected

(initial value)

Bit 6INT6 Edge Select (INTEG6): Bit 6 selects the input sensing of the INT6 pin and TMIB
pin.
Bit 6: INTEG6

Description

Falling edge of INT6 and TMIB pin input is detected

Rising edge of INT6 and TMIB pin input is detected

(initial value)

Bit 5INT5 Edge Select (INTEG5): Bit 5 selects the input sensing of the INT5 pin and ADTRG
pin.
Bit 5: INTEG5

Description

Falling edge of INT5 and ADTRG pin input is detected

Rising edge of INT5 and ADTRG pin input is detected

(initial value)

Bits 4 to 0INT4 to INT0 Edge Select (INTEG4 to INTEG0): Bits 4 to 0 select the input
sensing of pins INT4 to INT 0.
Bit n: INTEGn

Description

Falling edge of INTn pin input is detected

Rising edge of INTn pin input is detected

(initial value)

(n = 4 to 0)

65

Interrupt Enable Register 1 (IENR1)

Bit

IENTB1

IENTA

IEN3

IEN2

IEN1

IEN0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1
is initialized to H'10.
Bit 7Timer B1 Interrupt Enable (IENTB1): Bit 7 enables or disables timer B1 overflow
interrupt requests.
Bit 7: IENTB1

Description

Disables timer B1 interrupt requests

Enables timer B1 interrupt requests

(initial value)

Bit 6Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt
requests.
Bit 6: IENTA

Description

Disables timer A interrupt requests

Enables timer A interrupt requests

(initial value)

Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable IRQ3
to IRQ0 interrupt requests.
Bit n: IENn

Description

Disables interrupt requests from pin IRQn

Enables interrupt requests from pin IRQn

(initial value)

(n = 3 to 0)

66

Interrupt Enable Register 2 (IENR2)

Bit

IENDT

IENAD

IENS1

Initial value

Read/Write

R/W

R/W

R/W

IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2
is initialized to H'00.
Bit 7Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT

Description

Disables direct transfer interrupt requests

Enables direct transfer interrupt requests

(initial value)

Bit 6A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD

Description

Disables A/D converter interrupt requests

Enables A/D converter interrupt requests

(initial value)

Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete
interrupt requests.
Bit 4: IENS1

Description

Disables SCI1 interrupt requests

Enables SCI1 interrupt requests

(initial value)

Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.

67

Interrupt Enable Register 3 (IENR3)

Bit

INTEN7

INTEN6

INTEN5

INTEN4

INTEN3

INTEN2

INTEN1

INTEN0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

IENR3 is an 8-bit read/write register that enables or disables INT7 to INT0 interrupt requests. Upon
reset, IENR3 is initialized to H'00.
Bits 7 to 0INT7 to INT0 Interrupt Enable (INTEN7 to INTEN0): Bits 7 to 0 enable or
disable INT7 to INT0 interrupt requests.
Bit n: INTENn

Description

Disables interrupt requests from pin INTn

Enables interrupt requests from pin INTn

(initial value)

(n = 7 to 0)

68

Interrupt Request Register 1 (IRR1)

Bit

IRRTB1

IRRTA

IRRI3

IRRI2

IRRI1

IRRI0

Initial value

Read/Write

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

Note: * Only a write of 0 for flag clearing is possible.

IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1,
timer A, timer Y, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is
initialized to H'10.
Bit 7Timer B1 Interrupt Request Flag (IRRTB1)
Bit 7: IRRTB1

Description

Clearing conditions:
When IRRTB1 = 1, it is cleared by writing 0

Setting conditions:
When the timer B1 counter value overflows from H'FF to H'00

(initial value)

Bit 6Timer A Interrupt Request Flag (IRRTA)

Bit 6: IRRTA

Description

Clearing conditions:
When IRRTA = 1, it is cleared by writing 0

Setting conditions:
When the timer A counter value overflows from H'FF to H'00

(initial value)

Bit 5Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0IRQ3 to IRQ0 Interrupt Request Flags (IRRI3 to IRRI0)
Bit n: IRRIn

Description

Clearing conditions:
When IRRIn = 1, it is cleared by writing 0

Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge
is input

(initial value)

(n = 3 to 0)
69

Interrupt Request Register 2 (IRR2)

Bit

IRRDT

IRRAD

IRRS1

Initial value

Read/Write

R/W*

R/W*

R/W*

Note: * Only a write of 0 for flag clearing is possible.

IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is
initialized to H'00.
Bit 7Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT

Description

Clearing conditions:
When IRRDT = 1, it is cleared by writing 0

Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2

(initial value)

Bit 6A/D Converter Interrupt Request Flag (IRRAD)

Bit 6: IRRAD

Description

Clearing conditions:
When IRRAD = 1, it is cleared by writing 0

Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR

(initial value)

Bit 5Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4SCI1 Interrupt Request Flag (IRRS1)
Bit 4: IRRS1

Description

Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0

Setting conditions:
When an SCI1 transfer is completed

(initial value)

Bits 3 to 0Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
70

Interrupt Request Register 3 (IRR3)

Bit

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

Initial value

Read/Write

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

Note: * Only a write of 0 for flag clearing is possible.

IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin
INT 7 to INT 0. The flags are not cleared automatically when an interrupt is accepted. It is necessary
to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00.
Bits 7 to 0INT7 to INT0 Interrupt Request Flags (INTF7 to INTF0)
Bit n: INTFn

Description

Clearing conditions:
When INTFn = 1, it is cleared by writing 0

Setting conditions:
When the designated signal edge is input at pin INTn

(initial value)

(n = 7 to 0)

71

3.3.3

External Interrupts

There are 12 external interrupts: IRQ 3 to IRQ0 and INT7 to INT0.

Interrupts IRQ3 to IRQ0: Interrupts IRQ 3 to IRQ0 are requested by input signals to pins IRQ3 to
IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG3 to IEG0 in IEGR1.
When these pins are designated as pins IRQ3 to IRQ0 in port mode register 1 and the designated
edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of
these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1.
These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ 3 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 7 to 4 are assigned to interrupts IRQ3 to IRQ0. The order of priority is from IRQ0 (high)
to IRQ3 (low). Table 3.2 gives details.
INT Interrupts: INT interrupts are requested by input signals to pins INT 7 to INT 0. These
interrupts are detected by either rising edge sensing or falling edge sensing, depending on the
settings of bits INTEG7 to INTEG0 in IEGR2.
When the designated edge is input at pins INT 7 to INT 0, the corresponding bit in IRR3 is set to 1,
requesting an interrupt. Recognition of these interrupt requests can be disabled individually by
clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the
I bit to 1 in CCR.
When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is
assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupthandling routine must discriminate the interrupt source.
Note: Pins INT 7 to INT 0 are multiplexed with port 5. Even in port usage of these pins, whenever
the designated edge is input or output, the corresponding bit INTFn is set to 1.
3.3.4

Internal Interrupts

There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2 to 0. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are
assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.

72

3.3.5

Interrupt Operations

Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.

Priority decision logic

Interrupt controller

External or
internal
interrupts

Interrupt
request

External
interrupts or
internal
interrupt
enable
signals

CCR (CPU)

Figure 3.2 Block Diagram of Interrupt Controller

Interrupt operation is described as follows.
If an interrupt occurs while the interrupt enable register bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is
accepted; if the I bit is 1, the interrupt request is held pending.
If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
73

 The I bit of CCR is set to 1, masking further interrupts.

The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.

74

Program execution state

IRRIO = 1

No

Yes
No

IENO = 1
Yes

IRRI1 = 1

No

Yes
IEN1 = 1
Yes

No

IRRI2 = 1

No

Yes
IEN2 = 1

No

Yes
IRRDT = 1

No

Yes
IENDT = 1

No

Yes
No

I=0
Yes
PC contents saved
CCR contents saved
I1
Branch to interrupt
handling routine

Legend:
PC: Program counter
CCR: Condition code register
I:
I bit of CCR

Figure 3.3 Flow up to Interrupt Acceptance

75

SP 4

SP (R7)

CCR

SP 3

SP + 1

CCR

SP 2

SP + 2

PCH

SP 1

SP + 3

PCL

SP (R7)

SP + 4

Even address

Stack area

Prior to start of interrupt

exception handling

PC and CCR
saved to stack

After completion of interrupt

exception handling

Legend:
PCH: Upper 8 bits of program counter (PC)
PCL: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word access, starting from
an even-numbered address.

Figure 3.4 Stack State after Completion of Interrupt Exception Handling

Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.

76

Interrupt is
accepted
Interrupt level
decision and wait for
end of instruction

Instruction
prefetch

Internal
processing

Stack access

Prefetch instruction of
Internal
interrupt-handling routine
processing

Vector fetch

Interrupt
request signal

Figure 3.5 Interrupt Sequence

Internal
address bus

(1)

(3)

(5)

(6)

(8)

(9)

Internal read
signal
Internal write
signal
Internal data bus
(16 bits)

(2)

(4)

(1)

(7)

(9)

(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP 2
(6) SP 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine

(10)

77

3.3.6

Interrupt Response Time

Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4

Interrupt Wait States

Item

States

Waiting time for completion of executing instruction*

1 to 13

Saving of PC and CCR to stack

Vector fetch

Instruction fetch

Internal processing

Total

15 to 27

Note: * Not including EEPMOV instruction.

78

3.4

Application Notes

3.4.1

Notes on Stack Area Use

When word data is accessed in the H8/3644 Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.

SP

SP

PCH
PC L

R1L
PC L

SP

H'FEFC
H'FEFD
H'FEFF

BSR instruction
SP set to H'FEFF

MOV. B R1L, @R7

Stack accessed beyond SP

Contents of PCH are lost

Legend:
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer

Figure 3.6 Operation when Odd Address is Set in SP

When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.

79

3.4.2

Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ3 to IRQ1, the interrupt request flag may be set to 1 at the time the pin function is
switched, even if no valid interrupt is input at the pin. Table 3.5 shows the conditions under which
interrupt request flags are set to 1 in this way.
Table 3.5

Conditions under which Interrupt Request Flag is Set to 1

Interrupt Request
Flags Set to 1
IRR1

IRRI3

Conditions
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR
bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR
bit IEG3 = 1.

IRRI2

When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR
bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR
bit IEG2 = 1.

IRRI1

When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR
bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR
bit IEG1 = 1.

Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.

80

CCR I bit 1

Interrupts masked. (Another possibility

is to disable the relevant interrupt in
interrupt enable register 1.)

Set port mode register bit

Execute NOP instruction

After setting the port mode register bit,

first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0

Clear interrupt request flag to 0

CCR I bit 0

Interrupt mask cleared

Figure 3.7 Port Mode Register Setting and Interrupt Request Flag
Clearing Procedure

81

Section 4 Clock Pulse Generators

4.1

Overview

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1

Block Diagram

Figure 4.1 shows a block diagram of the clock pulse generators.

OSC 1
OSC 2

System clock
oscillator

OSC
(f OSC)

OSC/2
System clock
divider (1/2)

OSC/128
System clock
OSC/64
divider

(1/64, 1/32, OSC/32

1/16, 1/8) OSC/16

Prescaler S
(13 bits)

System clock pulse generator

X1
X2

Subclock
oscillator

W
(f W )

Subclock
divider
(1/2, 1/4, 1/8)

Subclock pulse generator

W /2
W /4
W /8

/2
to
/8192

SUB

Prescaler W
(5 bits)

W /2
W /4
W /8
to
W /128

Figure 4.1 Block Diagram of Clock Pulse Generators

4.1.2

System Clock and Subclock

The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. Four of
the clock signals have names: is the system clock, SUB is the subclock, OSC is the oscillator
clock, and W is the watch clock.
The clock signals available for use by peripheral modules are /2, /4, /8, /16, /32, /64, /128,
/256, /512, /1024, /2048, /4096, /8192, W /2, W /4, W /8, W /16, W /32, W /64, and W /128.
The clock requirements differ from one module to another.

83

4.2

System Clock Generator

Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting a crystal
oscillator.
C1
OSC 1
Rf

R f = 1 M 20%
C1 = C 2 = 12 pF 20%

OSC 2
C2

Figure 4.2 Typical Connection to Crystal Oscillator

Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4.1 should be used.
CS
LS

RS

OSC 1

OSC 2

C0

Figure 4.3 Equivalent Circuit of Crystal Oscillator

Table 4.1

Crystal Oscillator Parameters

Frequency

2 MHz

4 MHz

8 MHz

10 MHz

RS (max)

500

100

50

30

C0 (max)

7 pF

7 pF

7 pF

7 pF

84

Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic
oscillator.
C1
OSC 1
Rf
OSC 2
C2

R f = 1 M 20%
C1 = 30 pF 10%
C2 = 30 pF 10%
Ceramic oscillator: Murata

Figure 4.4 Typical Connection to Ceramic Oscillator

Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic
oscillator, pay careful attention to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.

To be avoided

Signal A Signal B

C2
OSC 1

OSC 2
C1

Figure 4.5 Board Design of Oscillator Circuit

85

External Clock Input Method: Connect an external clock signal to pin OSC1, and leave pin
OSC2 open. Figure 4.6 shows a typical connection.

OSC 1

External clock input

OSC 2

Open

Figure 4.6 External Clock Input (Example)

Frequency

Oscillator Clock (OSC)

Duty cycle

45% to 55%

86

4.3

Subclock Generator

Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock
divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Follow the same
precautions as noted under 4.2 Notes on Board Design.
C1
X1
X2
C2

C1 = C 2 = 15 pF (typ.)

Figure 4.7 Typical Connection to 32.768-kHz Crystal Oscillator

Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator.
CS
LS

RS

X1

X2

C0

C0 = 1.5 pF (typ.)
RS = 14 k (typ.)
f W = 32.768 kHz
Crystal oscillator: MX38T
(Nihon Denpa Kogyo)

Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator

Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X1 to
VCC and leave pin X2 open, as shown in figure 4.9.
VCC
X1
X2

Open

Figure 4.9 Pin Connection when not Using Subclock

87

4.4

Prescalers

The H8/3644 Series is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock () as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (W/4) as its input clock. Its
prescaled outputs are used by timer A as a time base for timekeeping.
Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock () as its input clock. It
is incremented once per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is determined by the division factor
designated by MA1 and MA0 in SYSCR1.
Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 ( W /4)
as its input clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.

4.5

Note on Oscillators

Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
88

Section 5 Power-Down Modes

5.1

Overview

The H8/3644 Series has eight modes of operation after a reset. These include seven power-down
modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight
operating modes.
Table 5.1

Operating Modes

Operating Mode

Description

Active (high-speed) mode

The CPU and all on-chip peripheral functions are operable on

the system clock

Active (medium-speed) mode

The CPU and all on-chip peripheral functions are operable on

the system clock, but at 1/64, 1/32, 1/6, or 1/8* the speed in
active (high-speed) mode

Subactive mode

The CPU, and the time-base function of timer A are operable

on the subclock

Sleep (high-speed) mode

The CPU halts. On-chip peripheral functions except PWM are

operable on the system clock

Sleep (medium-speed) mode

The CPU halts. On-chip peripheral functions except PWM are

operable on the system clock, but at 1/64, 1/32, 1/6, or 1/8* the
speed in active (high-speed) mode

Subsleep mode

The CPU halts. The time-base function of timer A are operable

on the subclock

Watch mode

The CPU halts. The time-base function of timer A is operable

on the subclock

Standby mode

The CPU and all on-chip peripheral functions halt

Note: * Determined by the value set in bits MA1 and MA0 of system control register 1 (SYSCR1).

Of these eight operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode, and the two sleep modes (high-speed and medium speed) will be referred to
collectively as sleep mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.

89

Program
execution state

Reset state

*1

SLEEP
instruction*e

Watch
mode

Subactive
mode

*1

P *
EE tion
L
c
S ru
st
inin SL
st E
ru EP
ct
io
n *b
SLEEP
instruction*b
*3

Sleep
(medium-speed)
mode

ins SLEE
tru P
cti
on *j
S
ins LE
tru EP
ctio
n *i

*e
EP on
E
i
t
SL ruc
st
in

SLEEP
instruction*i

Active
(medium-speed)
mode
SLEEP
instruction*h

ins SLEE
tr u
ctio P
n *e

*4

SLEEP
instruction*g

SL
instr EEP
uctio *d
n

*1

Sleep
(high-speed)
mode

*3
a

SLEEP
instruction*f

Standby
mode

SLEEP
instruction*a

Active
(high-speed)
mode

P *d
EE n
SL uctio
tr
ins *4

Program
halt state

Program
halt state

SLEEP
instruction*c

Subsleep
mode

*2

Power-down modes
Mode Transition Conditions (1)

Mode Transition Conditions (2)

LSON MSON SSBY TMA3 DTON

a
b
c
d
e
f
g
h
i
J

0
0
1
0

*
0
0
0
1
0

0
1

*
*
*
0
1
1

*
0

0
0
0
1
1
0
0
1
1
1

*
*
1
0
1

*
*
1
1
1

0
0
0
0
0
1
1
1
1
1

Interrupt Sources
1

Timer A interrupt, IRQ0 interrupt

Timer a interrupt, IRQ3 to IRQ0 interrupts,

INT interrupt

All interrupts

IRQ1 or IRQ0 interrupt

* Dont care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5.2 through 5.8.

Figure 5.1 Mode Transition Diagram

90

Table 5.2

Internal State in Each Operating Mode

Active Mode

Sleep Mode

Function

HighSpeed

MediumSpeed

HighSpeed

MediumSpeed

Watch
Mode

Subactive Subsleep
Mode
Mode

Standby
Mode

System clock oscillator

Functions

Functions

Functions

Functions

Halted

Halted

Halted

Halted

Subclock oscillator

Functions

Functions

Functions

Functions

Functions

Functions

Functions

Functions

CPU
operations

Functions

Functions

Halted

Halted

Halted

Functions

Halted

Halted

Retained

Retained

Retained

Retained

Retained

Instructions
Registers
RAM

Retained*1

I/O ports
External
interrupts

IRQ0

Functions

Functions

Functions

Functions

Functions

Functions

Functions

Functions

Retained*2

IRQ1

Retained*2

IRQ2
IRQ3
INT0

Functions

Functions

Functions

Functions

Retained*2 Functions

Functions

Functions

Functions

Functions

Functions*3 Functions*3 Functions*3 Retained

Functions

Retained*2

INT1
INT2
INT3
INT4
INT5
INT6
INT7
Peripheral
functions

Timer A
Timer B1

Retained

Retained

Retained

Timer V

Reset

Reset

Reset

Reset

Retained

Retained

Retained

Retained

Timer X
Watchdog
timer
SCI1
SCI3
PWM

Retained

Retained

A/D
converter

Functions

Functions

Reset

Reset

Reset

Reset

Retained

Retained

Retained

Retained

Notes: 1. Register contents are retained, but output is high-impedance state.

2. External interrupt requests are ignored. Interrupt request register contents are not
altered.
3. Functions if timekeeping time-base function is selected.

5.1.1

System Control Registers

The operation mode is selected using the system control registers described in table 5.3.
91

Table 5.3

System Control Registers

Name

Abbreviation

R/W

Initial Value

Address

System control register 1

SYSCR1

R/W

H'07

H'FFF0

System control register 2

SYSCR2

R/W

H'E0

H'FFF1

System Control Register 1 (SYSCR1)

Bit

SSBY

STS2

STS1

STS0

LSON

MA1

MA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SYSCR1 is an 8-bit read/write register for control of the power-down modes.

Upon reset, SYSCR1 is initialized to H'07.
Bit 7Software Standby (SSBY): This bit designates transition to standby mode or watch mode.
Bit 7: SSBY

Description

When a SLEEP instruction is executed in active mode, a transition is made

to sleep mode

When a SLEEP instruction is executed in subactive mode, a transition is

made to subsleep mode
(initial value)

When a SLEEP instruction is executed in active mode, a transition is made

to standby mode or watch mode

When a SLEEP instruction is executed in subactive mode, a transition is

made to watch mode

92

Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from standby mode or
watch mode to active mode due to an interrupt. The designation should be made according to the
clock frequency so that the waiting time is at least 10 ms.
Bit 6: STS2

Bit 5: STS1

Bit 4: STS0

Description

Wait time = 8,192 states

Wait time = 16,384 states

Wait time = 32,768 states

Wait time = 65,536 states

Wait time = 131,072 states

(initial value)

Note: * Dont care

Bit 3Low Speed on Flag (LSON): This bit chooses the system clock () or subclock (SUB ) as
the CPU operating clock when watch mode is cleared. The resulting operation mode depends on
the combination of other control bits and interrupt input.
Bit 3: LSON

Description

The CPU operates on the system clock ()

The CPU operates on the subclock ( SUB)

(initial value)

Bits 2Reserved Bits: Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0Active (Medium-Speed) Mode Clock Select (MA1, MA0): Bits 1 and 0 choose
osc/128, osc/64, osc/32, or osc/16 as the operating clock in active (medium-speed) mode and sleep
(medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive
mode.
Bit 1: MA1

Bit 0: MA0

Description

osc/16

osc/32

osc/64

osc/128

(initial value)

93

System Control Register 2 (SYSCR2)

Bit

NESEL

DTON

MSON

SA1

SA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

SYSCR2 is an 8-bit read/write register for power-down mode control.

Upon reset, SYSCR2 is initialized to H'E0.
Bits 7 to 5Reserved Bits: These bits are reserved; they are always read as 1, and cannot be
modified.
Bit 4Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal ( W ) generated by the subclock pulse generator is sampled, in
relation to the oscillator clock (OSC) generated by the system clock pulse generator. When OSC = 2
to 10 MHz, clear NESEL to 0.
Bit 4: NESEL

Description

Sampling rate is OSC/16

Sampling rate is OSC/4

(initial value)

Bit 3Direct Transfer on Flag (DTON): This bit designates whether or not to make direct
transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP
instruction is executed. The mode to which the transition is made after the SLEEP instruction is
executed depends on a combination of this and other control bits.

94

Bit 3: DTON

Description

When a SLEEP instruction is executed in active mode, a transition is made

to standby mode, watch mode, or sleep mode

When a SLEEP instruction is executed in subactive mode, a transition is

made to watch mode or subsleep mode
(initial value)

When a SLEEP instruction is executed in active (high-speed) mode, a

direct transition is made to active (medium-speed) mode if SSBY = 0,
MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1,
and LSON = 1

When a SLEEP instruction is executed in active (medium-speed) mode, a

direct transition is made to active (high-speed) mode if SSBY = 0, MSON =
0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON
=1

When a SLEEP instruction is executed in subactive mode, a direct

transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1,
TMA3 = 1, LSON = 0, and MSON = 1

Bit 2Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed), active (medium-speed), or sleep (medium-speed) mode.
Bit 2: MSON

Description

After standby, watch, or sleep mode is cleared, operation is in active (highspeed) mode

When a SLEEP instruction is executed in active mode, a transition is made

to sleep (high-speed) mode
(initial value)

After standby, watch, or sleep mode is cleared, operation is in active

(medium-speed) mode

When a SLEEP instruction is executed in active mode, a transition is made

to sleep (medium-speed) mode

Bits 1 and 0 Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock
rate (W /2, W /4, or W /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
Bit 1: SA1

Bit 0: SA0

Description

W/8

W/4

W/2

(initial value)

Note: * Dont care

95

5.2

Sleep Mode

5.2.1

Transition to Sleep Mode

Transition to Sleep (High-Speed) Mode: The system goes from active mode to sleep (highspeed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1
and the MSON and DTON bits in SYSCR2 are all cleared to 0. In sleep (high-speed) mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. CPU
register contents are retained.
Transition to Sleep (Medium-Speed) Mode: The system goes from active mode to sleep
(medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in
SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is
cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is
halted but the on-chip peripheral functions other than PWM are operational. The clock frequency
in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
5.2.2

Clearing Sleep Mode

Sleep mode is cleared by any interrupt (timer A, timer B1, timer X, timer V, IRQ 3 to IRQ0, INT 7 to
INT 0, SCI 3, SCI 1, or A/D converter), or by input at the RES pin.
Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3

Clock Frequency in Sleep (Medium-Speed) Mode

Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.

96

5.3

Standby Mode

5.3.1

Transition to Standby Mode

The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2

Clearing Standby Mode

Standby mode is cleared by an interrupt (IRQ1 or IRQ0) or by input at the RES pin.
Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire
chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in
active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON
= 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.

97

5.3.3

Oscillator Settling Time after Standby Mode is Cleared

Bits STS2 to STS0 in SYSCR1 should be set as follows.

When a crystal oscillator is used
The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time of at least 10 ms.
Table 5.4

Clock Frequency and Settling Time (times are in ms)

STS2

STS1

STS0

Waiting Time

5 MHz

4 MHz

2 MHz

1 MHz

0.5 MHz

8,192 states

1.6

2.0

4.1

8.2

16.4

16,384 states

3.2

4.1

8.2

16.4

32.8

32,768 states

6.6

8.2

16.4

32.8

65.5

65,536 states

13.1

16.4

32.8

65.5

131.1

131,072 states

26.2

32.8

65.5

131.1

262.1

Note: * Dont care

When an external clock is used

Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.

98

5.4

Watch Mode

5.4.1

Transition to Watch Mode

The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a
minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some
registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before
the transition.
5.4.2

Clearing Watch Mode

Watch mode is cleared by an interrupt (timer A or IRQ0) or by input at the RES pin.
Clearing by interrupt
When watch mode is cleared by a timer A interrupt or IRQ0 interrupt, the mode to which a
transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If
both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0
and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to
subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2
to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared,
and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1
or the particular interrupt is disabled in the interrupt enable register.
Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
5.4.3

Oscillator Settling Time after Watch Mode is Cleared

The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.

99

5.5

Subsleep Mode

5.5.1

Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A is
halted. As long as a minimum required voltage is applied, the contents of CPU registers, the onchip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the
same states as before the transition.
5.5.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (timer A, IRQ 3 to IRQ0, INT 7 to INT0) or by input at the
RES pin.
Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.

100

5.6

Subactive Mode

5.6.1

Transition to Subactive Mode

Subactive mode is entered from watch mode if a timer A or IRQ0 interrupt is requested while the
LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A,
IRQ3 to IRQ0, or INT7 to INT0 interrupt is requested. A transition to subactive mode does not take
place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable
register.
5.6.2

Clearing Subactive Mode

Subactive mode is cleared by a SLEEP instruction or by input at the RES pin.

Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer,
below.
Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
5.6.3

Operating Frequency in Subactive Mode

The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are W /2, W /4, and W /8.

101

5.7

Active (Medium-Speed) Mode

5.7.1

Transition to Active (Medium-Speed) Mode

If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ0 or IRQ1 interrupts in standby mode, timer A or
IRQ0 interrupts in watch mode, or any interrupt in sleep (medium-speed) mode. A transition to
active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
5.7.2

Clearing Active (Medium-Speed) Mode

Active (medium-speed) mode is cleared by a SLEEP instruction or by input at the RES pin.
Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep (high-speed) mode is entered if MSON is cleared to 0 in SYSCR2, and sleep (mediumspeed) mode is entered if MSON is set to 1. Direct transfer to active (high-speed) mode or to
subactive mode is also possible. See 5.8, Direct Transfer, below for details.
Clearing by RES pin
When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is
cleared.
5.7.3

Operating Frequency in Active (Medium-Speed) Mode

Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.

102

5.8

Direct Transfer

The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead
to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is
set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting
mode by means of an interrupt.
Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits
STS2 to STS0 has elapsed.
Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is
set to 1, a transition is made to subactive mode via watch mode.
103

 Direct transfer from subactive mode to active (medium-speed) mode

When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.

104

Section 6 ROM
6.1

Overview

The H8/3644 has 32 kbytes of on-chip mask ROM, PROM or flash memory. The H8/3643 has 24
kbytes of mask ROM or flash memory. The H8/3642 has 16 kbytes of mask ROM or flash
memory. The H8/3641 has 12 kbytes of on-chip ROM. H8/3640 has 8 kbytes of ROM. The ROM
is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte
data and word data.
In the PROM version (H8/3644 ZTAT) and flash memory versions (H8/3644 F-ZTAT, H8/3643
F-ZTAT, H8/3642 AF-ZTAT), programs can be written and erased with a general-purpose PROM
programmer. In the on-chip flash memory versions, programs can be written and erased on-board.
6.1.1

Block Diagram

Figure 6.1 shows a block diagram of the on-chip ROM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'0000

H'0000

H'0001

H'0002

H'0002

H'0003

On-chip ROM
H'7FFE

H'7FFE

H'7FFF

Even-numbered
address

Odd-numbered
address

Figure 6.1 ROM Block Diagram (H8/3644)

105

6.2

PROM Mode

6.2.1

Setting to PROM Mode

If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C256 EPROM. Table 6.1 shows how to set the chip to PROM mode.
Table 6.1

Setting to PROM Mode

Pin Name

Setting

TEST

High level

PB4/AN4

Low level

PB5/AN5
PB6/AN6

6.2.2

High level

Socket Adapter Pin Arrangement and Memory Map

A general-purpose PROM programmer can be used to program the PROM. A socket adapter is
required for conversion to 28 pins, as listed in table 6.2.
Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
Table 6.2

Socket Adapter

Package

Socket Adapter

64-pin QFP (FP-64A)

Under development

64-pin SDIP (DP-64S)

Under development

80-pin TQFP (TFP-80C)

Under development

106

H8/3644
HN27C256 (28-pin)

Pin #
Pin name
FP-64A

DP-64S

TFP-80C

10
17
18
19
20
21
22
23
24
46
45
44
43
42
41
40
39
55
16
57
34
35
36
37
38
56
33
58
4
6
60
47
48
7
3
62
61
52

18
25
26
27
28
29
30
31
32
54
53
52
51
50
49
48
47
63
24
1
42
43
44
45
46
64
41
2
12
14
4
55
56
15
11
6
5
60

12
22
23
24
25
26
27
28
29
57
56
55
54
52
51
50
49
69
19
71
43
44
45
46
47
70
42
72
5
7
74
58
59
8, 11
4
76
75
66

RES
P60
P61
P62
P63
P64
P65
P66
P67
P87
P86
P85
P84
P83
P82
P81
P80
P15
IRQ 0
P17
P73
P74
P75
P76
P77
P16
VCC
AVCC
TEST
X1
PB6
P20
P21
VSS
AVSS
PB4
PB5
P3 0

Pin name

Pin #

VPP
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
CE
OE
VCC

1
11
12
13
15
16
17
18
19
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
28

VSS

14

Note: Pins not indicated in the figure should be left open.

Figure 6.2 Socket Adapter Pin Correspondence (ZTAT)

107

Address in
MCU mode

Address in
PROM mode

H'0000

H'0000

On-chip PROM

H'7FFF

H'7FFF

Figure 6.3 H8/3644 Memory Map in PROM Mode

When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'7FFF.

6.3

Programming

The H8/3644 write, verify, and other modes are selected as shown in table 6.3 in PROM mode.
Table 6.3

Mode Selection in PROM Mode (H8/3644)

Pin

Mode

CE

OE

VPP

VCC

EO7 to EO0

EA 14 to EA0

Write

VPP

VCC

Data input

Address input

Verify

VPP

VCC

Data output

Address input

Programming
disabled

VPP

VCC

High impedance

Address input

Notation:
L: Low level
H: High level
VPP : VPP level
VCC: VCC level

The specifications for writing and reading are identical to those for the standard HN27C256
EPROM.

108

6.3.1

Writing and Verifying

An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. Data in unused address areas has a value of H'FF. The basic flow of
this high-speed, high-reliability programming method is shown in figure 6.4.

Start

Set write/verify mode

VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V
Address = 0
n=0
n+1 n
No

Yes
n < 25

Write time t PW = 0.2 ms 5%

No Go

Address + 1 address

Verify
Go

Write time tOPW = 3n ms

Last address?

No

Yes
Set read mode
VCC = 5.0 V 0.5 V, VPP = VCC
No Go
Error

Read all
addresses?
Go
End

Figure 6.4 High-Speed, High-Reliability Programming Flow Chart

109

Table 6.4 and table 6.5 give the electrical characteristics in programming mode.
Table 6.4

DC Characteristics

(Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item

Symbol

Min

Typ

Max

Unit

Test
Condition

Input highlevel voltage

EO7 to EO 0, EA14 to EA 0
OE, CE

VIH

2.4

VCC + 0.3

Input lowlevel voltage

EO7 to EO 0, EA14 to EA 0
OE, CE

VIL

0.3

0.8

Output highlevel voltage

EO7 to EO 0

VOH

2.4

I OH = 200 A

Output lowlevel voltage

EO7 to EO 0

VOL

0.45

I OL = 0.8 mA

Input leakage EO7 to EO 0, EA14 to EA 0

current
OE, CE

|ILI|

Vin = 5.25 V/
0.5 V

VCC current

I CC

40

mA

VPP current

I PP

40

mA

110

Table 6.5

AC Characteristics

(Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Address setup time

t AS

Figure 6.5*1

OE setup time

t OES

Data setup time

t DS

Address hold time

t AH

Data hold time

t DH

Data output disable time

t DF *

130

ns

VPP setup time

t VPS

Programming pulse width

t PW

0.95

1.0

1.05

ms

CE pulse width for overwrite

programming

t OPW*

2.85

78.7

ms

VCC setup time

t VCS

Data output delay time

t OE

500

ns

Notes: 1. Input pulse level: 0.8 V to 2.2 V

Input rise time/fall time 20 ns
Timing reference levels: Input: 1.0 V, 2.0 V
Output: 0.8 V, 2.0 V
2. t DF is defined at the point at which the output is floating and the output level cannot be
read.
3. t OPW is defined by the value given in figure 6.4, High-Speed, High-Reliability
Programming Flow Chart.

111

Figure 6.5 shows a PROM write/verify timing diagram.

Write

Verify

Address
tAH

tAS
Data

Input data
tDS

VPP

VCC

Output data
tDH

tDF

VPP
VCC

tVPS

VCC+1
VCC

tVCS

CE
tPW
OE

tOES

tOE

tOPW*

Note: * tOPW is defined by the value given in figure 6.4, High-Speed, High-Reliability Programming
Flow Chart.

Figure 6.5 PROM Write/Verify Timing

6.3.2

Programming Precautions

Use the specified programming voltage and timing.

The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C256 will result in
correct VPP of 12.5 V.
Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
112

6.3.3

Reliability of Programmed Data

A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6.6 shows the recommended screening procedure.

Program chip and

verify programmed data

Bake chip for 24 to 48 hours

at 125C to 150C
with power off

Read and check program

Install

Figure 6.6 Recommended Screening Procedure

If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects, using a
microcomputer with on-chip EPROM in a windowed package, etc. Please inform Hitachi of any
abnormal conditions noted during or after programming or in screening of program data after
high-temperature baking.

6.4

Flash Memory Overview

6.4.1

Principle of Flash Memory Operation

Table 6.6 illustrates the principle of operation of the on-chip flash memory in the H8/3644F,
H8/3643F, and H8/3642AF.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws
hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
113

floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like
an EPROM cell, by driving the gate to a high level and detecting the drain current, which depends
on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased,
its threshold voltage may become negative, causing the cell to operate incorrectly.
Section 6.7.6, Erase Flowcharts and Sample Programs, shows optimal erase control flowcharts and
sample programs.
Table 6.6

Principle of Memory Cell Operation

Program

Memory
cell

Erase
Vg = VPP

Read

Vs = VPP

Vg = VCC

Open

Vd

Memory
array

6.4.2

Vd

Vd

0V

Open

Vd

Open

0V

VPP

0V

VCC

0V

VPP

0V

0V

0V

0V

Mode Pin Settings and ROM Space

The H8/3644F has 32 kbytes of on-chip flash memory, the H8/3643F has 24 kbytes, and the
H8/3642AF has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU
accesses flash memory in two states for both byte-size and word-size instructions.
The flash memory is allocated to addresses H'0000 to H'7FFF in the H8/3644F, to addresses
H'0000 to H'5FFF in the H8/3643F, and to addresses H'0000 to H'3FFF in the H8/3642AF.

114

6.4.3

Features

The features of the flash memory are summarized below.

Five flash memory operating modes
There are five flash memory operating modes: program mode, program-verify mode, erase
mode, erase-verify mode, and prewrite-verify mode.
Erase block specification
Blocks to be erased in the flash memory space can be specified by setting the corresponding
register bits. The address space includes a large block area (four blocks with sizes from 4
kbytes to 8 kbytes) and a small block area (eight blocks with sizes from 128 bytes to 1 kbyte).
Programming/erase times
The flash memory programming time is 50 s (typ.) per byte, and the erase time is 1 s (typ.).
Erase-program cycles
Flash memory contents can be erased and reprogrammed up to 100 times.
On-board programming modes
There are two modes in which flash memory can be programmed, erased, and verified onboard: boot mode and user program mode.
Automatic bit rate adjustment
For data transfer in boot mode, the chips bit rate can be automatically adjusted to match the
transfer bit rate of the host (max. 9600 bps).
PROM mode
Flash memory can be programmed and erased in PROM mode, using a general-purpose PROM
programmer, as well as in on-board programming mode. The specifications for programming,
erasing, verifying, etc., are the same as for standard HN28F101 flash memory.

115

6.4.4

Block Diagram

Figure 6.7 shows a block diagram of the flash memory.

8
Internal data bus (upper)
8
Internal data bus (lower)

FLMCR

Bus interface/control section

Operating
mode

EBR1
EBR2

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

On-chip flash memory (32 kbytes)

H'7FFC

H'7FFD

H'7FFE

H'7FFF

Upper byte
(even address)

Lower byte
(odd address)

Legend:
FLMCR: Flash memory control register
EBR1: Erase block register 1
EBR2: Erase block register 2

Figure 6.7 Block Diagram of Flash Memory (Example of the H8/3644F)

116

TEST

6.4.5

Pin Configuration

The flash memory is controlled by means of the pins shown in table 6.7.
Table 6.7

Flash Memory Pins

Pin Name

Abbreviation

Input/Output

Function

Programming power

FV PP

Power supply

Apply 12.0 V

Mode pin

TEST

Input

Sets H8/3644F operating mode

Transmit data

TXD

Output

SCI3 transmit data output

Receive data

RXD

Input

SCI3 receive data input

The transmit data pin and receive data pin are used in boot mode.
6.4.6

Register Configuration

The registers used to control the on-chip flash memory are shown in table 6.8.
Table 6.8

Flash Memory Registers

Register Name

Abbreviation

R/W

Initial Value

Address

Flash memory control register

FLMCR

R/W

H'00

H'FF80

Erase block register 1

EBR1

R/W

H'F0

H'FF82

Erase block register 2

EBR2

R/W

H'00

H'FF83

The FLMCR, EBR1, and EBR2 registers are valid only when programming and erasing flash
memory, and can only be accessed when 12 V is applied to the FV PP pin. When 12 V is not
applied to the FVPP pin, addresses H'FF80 to H'FF83 cannot be modified and are always read as
H'FF.

117

6.5

Flash Memory Register Descriptions

6.5.1

Flash Memory Control Register (FLMCR)

FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program
mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this
register. FLMCR is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and
standby mode, and when 12 V is not applied to FV PP . When 12 V is applied to FVPP , a reset
initializes FLMCR to H'80.
Bit

VPP

EV

PV

Initial value

Read/Write

R/W*

R/W*

R/W*

R/W*

Note: * For information on access to this register, see note 11 in section 6.9, Flash Memory
Programming and Erasing Precautions.

Bit 7Programming Power (VPP): Bit 7 is a status flag that indicates that 12 V is applied to the
FVPP pin. For further information, see note 5 in section 6.9, Flash Memory Programming and
Erasing Precautions.
Bit 7: VPP

Description

Clearing conditions:
When 12 V is not applied to the FVPP pin

Setting conditions:
When 12 V is applied to the FVPP pin

(initial value)

Bit 3Erase-Verify Mode (EV)*1: Bit 3 selects transition to or exit from erase-verify mode.
Bit 3: EV

Description

Exit from erase-verify mode

Transition to erase-verify mode

118

(initial value)

Bit 2Program-Verify Mode (PV)* 1: Bit 2 selects transition to or exit from program-verify
mode.
Bit 2: PV

Description

Exit from program-verify mode

Transition to program-verify mode

(initial value)

Bit 1Erase Mode (E)*1 *2: Bit 1 selects transition to or exit from erase mode.
Bit 1: E

Description

Exit from erase mode

Transition to erase mode

(initial value)

Bit 0Program Mode (P)*1 *2: Bit 0 selects transition to or exit from program mode.
Bit 0: P

Description

Exit from program mode

Transition to program mode

(initial value)

Notes: 1. Do not set multiple bits simultaneously.

Do not release or cut the VCC or V PP power supply while a bit is set.
2. P bit and E bit setting should be carried out in accordance with the program/erase
algorithms shown in section 6.7, Programming and Erasing Flash Memory.
A watchdog timer setting should be made beforehand to prevent the P or E bit from
being set for longer than the specified time.
See section 6.9, Flash Memory Programming and Erasing Precautions, for more
information on the use of these bits.

119

6.5.2

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure.
EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FVPP . When a bit in EBR1 is set to 1, the corresponding
block is selected and can be programmed and erased. The erase block map is shown in figure 6.8,
and the correspondence between bits and erase blocks is shown in table 6.9.
Bit

LB3

LB2

LB1

LB0

Initial value

Read/Write

R/W*

R/W*

R/W*

R/W*

Note: * Word access cannot be used on this register; byte access must be used. For information on
access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing
Precautions. LB3 is invalid in the H8/3643F, and LB3 and LB2 are invalid in the H8/3642AF.

Bits 7 to 4Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bits 3 to 0Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be
programmed and erased.
Bits 3 to 0:
LB3 to LB0

Description

Block LB3 to LB0 is not selected

Block LB3 to LB0 is selected

120

(initial value)

6.5.3

Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure.
EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FVPP . When a bit in EBR2 is set to 1, the corresponding
block is selected and can be programmed and erased. The erase block map is shown in figure 6.8,
and the correspondence between bits and erase blocks is shown in table 6.9.
Bit

SB7

SB6

SB5

SB4

SB3

SB2

SB1

SB0

Initial value

Read/Write

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

R/W*

Note: * Word access cannot be used on this register; byte access must be used. For information on
access to this register, see note 11 in section 6.9, Flash Memory Programming and Erasing
Precautions. LB3 is invalid in the H8/3643F, and LB3 and LB2 are invalid in the H8/3642AF.

Bits 7 to 0Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0:
SB7 to SB0

Description

Block SB7 to SB0 is not selected

Block SB7 to SB0 is selected

(initial value)

121

H'0000

Small block
area
(4 kbytes)

H'0000
SB7 to SB0
(4 kbytes)

H'0FFF
H'1000

Large block
area
(H8/3644F:
28 kbytes)

SB0
SB1
SB2
H'01FF SB3
H'0200

LB0
(4 kbytes)
H'1FFF
H'2000
(H8/3642AF:
12 kbytes)

SB4
(512 bytes)
H'03FF
H'0400

LB1
(8 kbytes)
H'3FFF
H'4000

(H8/3643F:
20 kbytes)

(128 bytes)
(128 bytes)
(128 bytes)
(128 bytes)

SB5
(1 kbyte)
H'07FF
H'0800

LB2
(8 kbytes)
H'5FFF
H'6000

SB6
(1 kbyte)
H'0BFF
H'0C00

LB3
(8 kbytes)
H'7FFF

SB7
(1 kbyte)
H'0FFF

Figure 6.8 Erase Block Map

Table 6.9

Correspondence between Erase Blocks and EBR1/EBR2 Bits

Register

Bit

Block

Addresses

Size

EBR1

LB0

H'1000 to H'1FFF

4 kbytes

LB1

H'2000 to H'3FFF

8 kbytes

LB2

H'4000 to H'5FFF

8 kbytes

LB3

H'6000 to H'7FFF

8 kbytes

Register

Bit

Block

Addresses

Size

EBR2

SB0

H'0000 to H'007F

128 bytes

SB1

H'0080 to H'00FF

128 bytes

SB2

H'0100 to H'017F

128 bytes

SB3

H'0180 to H'01FF

128 bytes

SB4

H'0200 to H'03FF

512 bytes

SB5

H'0400 to H'07FF

1 kbyte

SB6

H'0800 to H'0BFF

1 kbyte

SB7

H'0C00 to H'0FFF

1 kbyte

122

6.6

On-Board Programming Modes

When an on-board programming mode is selected, on-chip flash memory programming, erasing,
and verifying can be carried out. There are two on-board programming modesboot mode and
user program modeset by the mode pin (TEST) and the FVPP pin. Table 6.10 shows how to
select the on-board programming modes. For information on turning VPP on and off, see note 5 in
section 6.9, Flash Memory Programming and Erasing Precautions.
Table 6.10 On-Board Programming Mode Selection
Mode Setting

FV PP

TEST

Boot mode

12 V*

12 V*

User program mode

Notes

VSS

Note: * See notes 6 to 8 in section 6.6.1, Notes on Use of Boot Mode, for the timing of 12 V
application.

6.6.1

Boot Mode

When boot mode is used, a user program for flash memory programming and erasing must be
prepared beforehand in the host machine (which may be a personal computer). SCI3 is used in
asynchronous mode (see figure 6.8). When the H8/3644F, H8/3643F, or H8/3642AF is set to boot
mode, after reset release a built-in boot program is activated, the low period of the data sent from
the host is first measured, and the bit rate register (BRR) value determined. The chips on-chip
serial communication interface (SCI3) can then be used to download the user program from the
host machine. The downloaded user program is written into RAM.
After the program has been stored, execution branches to the start address (H'FBE0) of the on-chip
RAM, the program stored in RAM is executed, and flash memory programming/erasing can be
carried out. Figure 6.10 shows the boot mode execution procedure.

Reception of programming data

HOST
Transmission of verify data

H8/3644F,
H8/3643F, or
H8/3642AF
RXD
SCI3
TXD

Figure 6.9 Boot Mode System Configuration

123

Boot Mode Execution Procedure: The boot mode execution procedure is shown below.
Start

1. Set the chip to boot mode and execute a reset-start.

2. Set the host to the prescribed bit rate (2400/4800/9600)
and have it transmit H'00 data continuously using a
transfer data format of 8-bit data plus 1 stop bit.

Set pins to boot mode for chip

and execute reset-start

Host transmits H'00 data continuously

at prescribed bit rate
Chip measures low period of H'00 data
transmitted by host

3
Chip calculates bit rate and sets value
in bit rate register

3. The chip repeatedly measures the low period at the

RXD pin and calculates the asynchronous
communication bit rate used by the host.
4. After SCI3 bit rate adjustment is completed, the chip
transmits one H'00 data byte to indicate the end of
adjustment.

After bit rate adjustment, chip transmits

one H'00 data byte to host to indicate
end of adjustment

5. On receiving the one-byte data indicating completion of

bit rate adjustment, the host should confirm normal
reception of this indication and transmit one H'55 data
byte.

Host confirms normal reception of bit rate

adjustment end indication, and transmits
one H'55 data byte

6. After receiving H'55, the chip transfers part of the boot

program to RAM areas H'FB80 to H'FBDF and H'FC00
to H'FF2F.

After receiving H'55, chip transfers part

of boot program to RAM
Chip branches to RAM boot area
(H'FC00 to H'FF2F), then checks flash
memory user area data

All data = H'FF?

YES

No
Erase all flash
memory blocks*3

8. The chip transmits one H'AA byte. The host then

transmits the number of user program bytes to be
transferred to the chip. The number of bytes should be
sent as two bytes, upper byte followed by lower byte.
The host should then transmit sequentially the program
set by the user.
The chip transmits the received byte count and user
program sequentially to the host, one byte at a time, as
verify data (echo-back).

After confirming that all flash memory

data is H'FF, chip transmits
one H'AA byte to host

9. The chip writes the received user program sequentially to

on-chip RAM area H'FBE0 to H'FF6D (910 bytes).

Chip receives, as 2 bytes, number

of program bytes (N) to be transferred
to on-chip RAM*1

10. The chip transmits one H'AA byte, then branches to on

-chip RAM address H'FBE0 and executes the user
program written in area H'FBE0 to H'FF6D.

Chip transfers user program to RAM*2

7. The chip branches to the RAM boot program area

(H'FC00H'FF2F) and checks for the presence of data
written in the flash memory. If data has been written in
the flash memory, the chip erases all blocks.

Chip calculates remaining

bytes to be transferred (N = N 1)*2
Transfer
No
end byte count
N = 0?
Yes
Chip transfers user program to RAM,
then transmits one H'AA byte to host

10
Chip branches to RAM area
address H'FBE0 and executes user
program transferred to RAM

Notes: 1. The size of the RAM area available to the user is

910 bytes. The number of bytes to be
transferred must not exceed 910 bytes. The
transfer byte count must be sent as two bytes,
upper byte followed by lower byte.
Example of transfer byte count: for 256 bytes
(H'0100), upper byte = H'01, lower byte = H'00
2. The part of the user program that controls the
flash memory should be set in the program in
accordance with the flash memory program/
erase algorithms described later in this section.
3. If a memory cell does not operate normally and
cannot be erased, the chip transmits one H'FF
byte as an erase error indication and halts the
erase operation and subsequent operations.

Figure 6.10 Boot Mode Operation Flowchart

124

Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or
H8/3642AF measures the low period of the asynchronous SCI communication data transmitted
continuously from the host (figure 6.11). The data format should be set as 8-bit data, 1 stop bit, no
parity. The chip calculates the bit rate of the transmission from the host from the measured low
period (9 bits), and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
The host should confirm that this adjustment end indication has been received normally, and
transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode
again (reset), and repeat the above operations. Depending on the hosts transmission bit rate and
the chips system clock oscillation frequency (fOSC), there will be a discrepancy between the bit
rates of the host and the chip. To insure correct SCI operation, the hosts transfer bit rate should be
set to 2400, 4800, or 9600 bps*1. Table 6.11 shows typical host transfer bit rates and system clock
oscillation frequency for which automatic adjustment of the chips bit rate is possible. Boot mode
should be used within this system clock oscillation frequency range*2.
Notes: 1. Only use a host bit rate setting of 2400, 4800, or 9600 bps. No other bit rate setting
should be used.
2. Although the chip may also perform automatic bit rate adjustment with bit rate and
system clock oscillation frequency combinations other than those shown in table 6.11,
a degree of error will arise between the bit rates of the host and the chip, and
subsequent transfer will not be performed normally. Therefore, only a combination of
bit rate and system clock oscillation frequency within one of the ranges shown in table
6.11 can be used for boot mode execution.

Start
bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop
bit

Low period (9 bits) measured (H'00 data)

High period
(1 or more
bits)

Figure 6.11 Measurement of Low Period in Transmit Data from Host

125

Table 6.11 System Clock Oscillation Frequencies Permitting Automatic Adjustment of

Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate
Host Bit Rate*

System Clock Oscillation Frequencies (f OSC) Permitting Automatic

Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate

9600 bps

8 MHz to 16 MHz

4800 bps

4 MHz to 16 MHz

2400 bps

2 MHz to 16 MHz

Note: * Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be used.

RAM Area Allocation in Boot Mode: In boot mode, the 96-byte area from H'FB80 to H'FBDF
and the 18-byte area from H'FF6E to H'FF7F are reserved for boot program use, as shown in
figure 6.12. The area to which the user program is transferred is H'FBE0 to H'FF6D (910 bytes).
The boot program area becomes available when a transition is made to the execution state for the
user program transferred to RAM. A stack area should be set within the user program as required.

H'FB80

Boot program
area*
(96 bytes)

H'FBE0

User program
transfer area
(910 bytes)

H'FF6E
H'FF7F

Boot program
area*
(18 bytes)

Note: * These areas cannot be used until a transition is made to the execution state for the user
program transferred to RAM (i.e. a branch is made to RAM address H'FBE0). Note also
that the boot program remains in the boot program area in RAM (H'FB80 to H'FBDF,
H'FF6E to H'FF7F) even after control branches to the user program. When an interrupt
handling routine is executed in the boot program, the 16 bytes from H'FB80 to H'FB8F in
this area cannot be used. For details see section 6.7.9, Interrupt Handling during Flash
Memory Programming/Erasing.

Figure 6.12 RAM Areas in Boot Mode

126

Notes on Use of Boot Mode:

1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it
measures the low period of the input at the SCI3s RXD pin. The reset should end with RXD
high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low
period of the RXD input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD and TXD lines should be pulled up on the board.
5. Before branching to the user program (RAM address H'FBE0), the chip terminates transmit
and receive operations by its on-chip SCI3 (by clearing the RE and TE bits to 0 in the serial
control register (SCR)), but the adjusted bit rate value remains set in the bit rate register
(BRR). The transmit data output pin, TXD, goes to the high-level output state (PCR22 = 1 in
the port 2 control register, P22 = 1 in the port 2 data register).
The contents of the CPUs internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
6.

Boot mode can be entered by applying 12 V to the TEST pin and FVPP pin in accordance with
the mode setting conditions shown in table 6.10, and then executing a reset-start. Care must
be taken with turn-on of the VPP power supply at this time.
On reset release (a low-to-high transition), the chip determines whether 12 V is being applied
to the TEST pin and FVPP pin, and on detecting that boot mode has been set, retains that state
internally. As the applied voltage criterion level (threshold level) at this time is the range of
approximately VCC +2 V to 11.4 V, a transition will be made to boot mode even if a voltage
sufficient for executing programming and erasing (11.4 V to 12.6 V) is not being applied.
Therefore, when executing the boot program, the VPP power supply must be stabilized within
the range of 11.4 V to 12.6 V before a branch is made to the RAM area, as shown in figure
6.24.
Insure that the program voltage VPP does not exceed 12.6 V when a transition is made to boot
mode (when reset is released), and does not exceed the range 12 V 0.6 V during boot mode
operation. If these values are exceeded, boot mode execution will not be performed correctly.
127

Also, do not release or cut V PP during boot mode execution or when programming or erasing
flash memory*.
Boot mode can be exited by driving the reset pin low, then releasing 12 V application to the
TEST pin and FVPP pin at least 10 system clock cycles later, and setting the TEST pin to VSS to
release the reset.
However, external pin settings must not be changed during boot mode execution.
Note that the boot mode state is not maintained if 12 V application to the TEST pin is released
while in boot mode.
Also, if a watchdog timer reset occurs in this boot mode state, the built-in boot program will be
restarted without clearing the MCUs internal mode state.
7. If the TEST pin input level is changed (e.g. from 0 V to 5 V to 12 V) during a reset (while a
low level is being input at the RES pin), port states will change as a result of the change of
MCU operating mode. Therefore, care must be taken to make pin settings to prevent these pins
from becoming output signal pins during a reset, and to prevent collision with signals outside
the MCU.
8. Regarding 12 V application to the FVPP and TEST pins, insure that peak overshoot does not
exceed the maximum rating of 13 V.
Also, be sure to connect bypass capacitors to the FVPP and TEST pins.
Note: * For further information on V PP application, release, and cut-off, see note 5 in section 6.9,
Flash Memory Programming and Erasing Precautions.
6.6.2

User Program Mode

When set to user program mode, the H8/3644F, H8/3643F, or H8/3642AF can program and erase
its flash memory by executing a user program. Therefore, on-board reprogramming of the on-chip
flash memory can be carried out by providing on-board means of supplying VPP and programming
data, and storing an on-board reprogramming program in part of the program area.
User program mode is selected by applying 12 V to the FVPP pin when flash memory is not being
accessed, during a reset or after confirming that a reset has been performed properly (after the
reset is released).
The flash memory cannot be read while being programmed or erased, so the on-board
reprogramming program or flash memory reprogramming routine should be transferred to the
RAM area, and on-board reprogramming executed in that area.

128

User Program Mode Execution Procedure*1: The procedure for user program execution in
RAM is shown below.

Reset-start (TEST = VSS)

Branch to flash memory on-board

reprogramming program

Transfer flash memory

reprogramming routine to RAM

Branch to flash memory

reprogramming routine in RAM area

Procedure:
An on-board reprogramming program must be written into
flash memory by the user beforehand.
1. Set the TEST pin to VSS and execute a reset-start.
2. Branch to the on-board reprogramming program written to
flash memory.
3. Transfer the flash memory reprogramming routine to the
RAM area.
4. Branch to the flash memory reprogramming routine
transferred to the RAM area.
5. Apply 12 V to the FVPP pin. (Transition to user program
mode)

FVPP = 12 V
(user program mode)

Execute flash memory

reprogramming routine in RAM area
(flash memory reprogramming)

Release FVPP
(exit user program mode)

Branch to flash memory application

program*2

6. Execute the flash memory reprogramming routine in the

RAM area, an perform on-board reprogramming of the
flash memory.
7. Switch the FVPP pin from 12 V to VCC, and exit user
program mode.
8. After on-board reprogramming of the flash memory ends,
branch to the flash memory application program.

Notes: 1. Do not apply 12 V to the FVPP pin during normal operation. To prevent inadvertent programming or
erasing due to program runaway, etc., apply 12 V to the FVPP pin only when the flash memory is
being programmed or erased . Memory cells may not operate normally if overprogrammed or
overerased due to program runaway, etc. Also, while 12 V is applied to the FVPP pin, the watchdog
timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
For further information on FVPP application, release, and cut-off, see note 5 in section 6.9, Flash
Memory Programming and Erasing Precautions.
2. When the application of 12 V to the FVPP pin is released after programming is completed, the flash
memory read setup time (tFRS) must elapse before executing a program in flash memory. This
specifies the setup time from the point at which the FVPP voltage reaches the VCC + 2 V level after
12 V application is released until the flash memory is read.

Figure 6.13 Example of User Program Mode Operation

129

6.7

Programming and Erasing Flash Memory

The on-chip flash memory of the H8/3644F, H8/3643F, and H8/3642AF is programmed and
erased by software, using the CPU. There are five flash memory operating modes: program mode,
erase mode, program-verify mode, erase-verify mode, and prewrite-verify mode. Transitions to
these modes can be made by setting the P, E, PV, and EV bits in the flash memory control register
(FLMCR).
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming and erasing should be located and executed in on-chip RAM
or external memory. A description of each mode is given below, with recommended flowcharts
and sample programs for programming and erasing.
See section 6.9, Flash Memory Programming and Erasing Precautions, for additional notes on
programming and erasing.
6.7.1

Program Mode

To write data into the flash memory, follow the programming algorithm shown in figure 6.14. This
programming algorithm enables data to be written without subjecting the device to voltage stress
or impairing the reliability of the programmed data.
To write data, first set the blocks to be programmed with erase block registers 1 and 2 (EBR1,
EBR2), and write the data to the address to be programmed, as in writing to RAM. The flash
memory latches the programming address and programming data in an address latch and data
latch. Next set the P bit in FLMCR, selecting program mode. The programming time is the time
during which the P bit is set. Make a setting so that the total programming time does not exceed 1
ms. Programming for too long a time, due to program runaway for example, can damage the
device. Before selecting program mode, set up the watchdog timer so as to prevent
overprogramming.
For details of the programming procedure, see section 6.7.3, Programming Flowchart and Sample
Program.

130

6.7.2

Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the programming time, exit programming mode (clear the P bit to 0) and select
program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is
applied to the memory cells at the latched address. If the flash memory is read in this state, the
data at the latched address will be read. After selecting program-verify mode, wait at least 4 s
before reading, then compare the programmed data with the verify data. If they agree, exit
program-verify mode and program the next address. If they do not agree, select program mode
again and repeat the same program and program-verify sequence. Do not repeat the program and
program-verify sequence more than six times* for the same bit.
Note: * When a bit is programmed repeatedly, set a loop counter so that the total programming
time will not exceed 1 ms.

131

6.7.3

Programming Flowchart and Sample Program

Flowchart for Programming One Byte

Start
Set erase block register
(set bit for block to be programmed to 1)
Write data to flash memory
(flash memory latches write address
and data) *1
n=1
Enable watchdog timer *2

Select program mode

(P bit = 1 in FLMCR)
Wait (x) s *4
Clear P bit

End of programming

Disable watchdog timer

Select program-verify mode
(PV bit = 1 in FLMCR)

Notes: 1. Write the data to be programmed using a byte

transfer instruction.
2. For the timer overflow interval, set the timer
counter value (TCW) to H'FE.
3. Read the memory data to be verified using a
byte transfer instruction.
4. Programming time x is successively
incremented to initial set value 2n1 (n = 1 to
6). The initial value should therefore be set to
15.8 s or less to make the total programming
time 1 ms or less.
5. tvs1: 4 s or more
N: 6 (set N so that total programming time
does not exceed 1 ms)

Wait (tvs1) s *5
Verify *3
(read memory)

NG

OK
Clear PV bit

Clear PV bit

Clear erase block register

(clear bit for programmed block to 0)

n N? *5

End (1-byte data programmed)

End of verify

No
n+1n

Yes
Programming error

Double the programming time

(x 2 x)

Figure 6.14 Programming Flowchart

132

Sample Program for Programming One Byte

This program uses the following registers:
R0H:
R1H:
R1L:
R3:
R4:

Used for erase block specification.

Stores programming data.
Stores read data.
Stores the programming address. Valid address specifications are H'0000 to H'EF7F.
Used for program and program-verify loop counter value setting. Also stores register set
values.
R5:
Used for program loop counter value setting.
R6L: Used for the program-verify fail count.
Arbitrary data can be programmed at an arbitrary address by setting the R3 (programming address)
and R1H (programming data) values.
The values of #a and #b depend on the operating frequency. They should be set as indicated in
table 6.12.
FLMCR:
EBR1:
EBR2:
TCSRW:
TCW:
PRGM:

PRGMS:

LOOP1:

.EQU
.EQU
.EQU
.EQU
.EQU
.ALIGN
MOV.B
MOV.B

H'FF80
H'FF82
H'FF83
H'FFBE
H'FFBF
2
#H'**,
R0H,

MOV.B
MOV.W
MOV.B
INC
MOV.W
MOV.B
MOV.B
MOV.B
MOV.B
MOV.W
BSET
SUBS
MOV.W
BNE
BCLR
MOV.B
MOV.B
MOV.B
BSET

R0H
@EBR*:8

;
; Set EBR *

#H'00,
#H'a,
R1H,
R6L
#H'FE5A,
R4L,
R4H,
#H'36,
R4L,
R5,
#0,
#1,
R4,
LOOP1
#0,
#H'50,
R4L,

R6L
R5
@R3

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

#H'b,
#2,

R4H
; Set program-verify fail counter
@FLMCR:8 ; Set PV bit

R4
@TCSRW:8
@TCW:8
R4L
@TCSRW:8
R4
@FLMCR:8
R4
R4
@FLMCR:8
R4L
@TCSRW:8

Program-verify fail count

Set program loop counter
Dummy write
Program-verify fail counter + 1 R6L

Start watchdog timer

Set program loop counter
Set P bit

Wait loop
Clear P bit
Stop watchdog timer

133

LOOP2:

PVOK:

DEC
BNE
MOV.B
CMP.B
BEQ
BCLR

R4H
LOOP2
@R3,
R1H,
PVOK
#2,

;
;
R1L
;
R1L
;
;
@FLMCR:8 ;

CMP.B
BEQ
ADD.W
BRA

#H'06,
NGEND
R5,
PRGMS

R6L

BCLR
MOV.B
MOV.B

#2,
#H'00,
R6L,

One byte programmed

NGEND:

134

Programming error

R5

;
;
;
;

Wait loop
Read programmed data
Compare programmed data with read data
Program-verify decision
Clear PV bit
Program-verify executed 6 times?
If program-verify executed 6 times, branch to NGEND
Double programming time
Program again

@FLMCR:8 ; Clear PV bit

R6L
;
@EBR*:8 ; Clear EBR*

6.7.4

Erase Mode

To erase the flash memory, follow the erasing algorithm shown in figure 6.15. This erasing
algorithm enables data to be erased without subjecting the device to voltage stress or impairing the
reliability of the programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be
erased in the programmed state (program all memory data to H'00). If all memory data is not in the
programmed state, follow the sequence described later to program the memory data to zero. Select
the flash memory areas to be programmed with erase block registers 1 and 2 (EBR1, EBR2). Next
set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the E bit is
set. To prevent overerasing, use a software timer to divide the time for one erasure, and insure that
the total time does not exceed 30 s. See section 6.7.6, Erase Flowcharts and Sample Programs, for
the time for one erasure. Overerasing, due to program runaway for example, can give memory
cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase
mode, set up the watchdog timer so as to prevent overerasing.
6.7.5

Erase-Verify Mode

In erase-verify mode, after data has been erased, it is read to check that it has been erased
correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0), and select eraseverify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy
data to the address to be read. This dummy write applies an erase-verify voltage to the memory
cells at the latched address. If the flash memory is read in this state, the data at the latched address
will be read. After the dummy write, wait at least 2 s before reading. Also, wait at least 4 s
before performing the first dummy write after selecting erase-verify mode. If the read data has
been successfully erased, perform the erase-verify sequence (dummy write, wait of at least 2 s,
read) on the next address. If the read data has not been erased, select erase mode again and repeat
the same erase and erase-verify sequence through the last address, until all memory data has been
erased to 1. Do not repeat the erase and erase-verify sequence more than 602 times, however.

135

6.7.6

Erase Flowcharts and Sample Programs

Flowchart for Erasing One Block

Start
Set erase block register
(set bit for block to be erased to 1)
Write 0 data in all addresses to be erased
(prewrite)*1
n=1
Enable watchdog timer *2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms *5
Clear E bit

Erasing halts

Disable watchdog timer

Set block start address as
verify address
Select erase-verify mode
(EV bit = 1)
Wait (tvs1) s *6
Dummy write to verify address *3
(flash memory latches
address)

Notes: 1. Program all addresses to be erased by

following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the initial value shown in table 6.13.
3. For the erase-verify dummy write, write H'FF
using a byte transfer instruction.
4. For the erase-verify operation, read the data
using a byte transfer instruction. When
erasing multiple blocks, clear the erase block
register bits for erased blocks and perform
additional erasing only for unerased blocks.
5. Erase time x is successively incremented to
initial set value x 2n-1 (n = 1 to 4), and is fixed
from the 4th time onward. An initial value of
6.25 ms or less should be set, and the time
for one erasure should be 50 ms or less.
6. tvs1: 4 s or more
tvs2: 2 s or more
N:
602 (set N so that the total erase time
does not exceed 30 s)

Wait (tvs2) s *6
Verify *4
(read data H'FF?)

NG

OK
No

Last address?
Yes
Clear EV bit

Address + 1 address
Clear EV bit

n N? *6

Clear erase block register

(clear bit for erased block to 0)
End of erase

Yes

Erase error

End of erase-verify

No
n+1n

n > 4?
No
Double the erase time
(x 2 x)

Figure 6.15 Erase Flowchart

136

Yes

Prewrite Flowchart

Start
Set erase block register
(set bit for block to be programmed to 1)
Set start address *6
n=1
Write H'00 to flash memory
(flash memory latches programmed address
and data) *1

Notes: 1. Write using a byte transfer instruction.

2. For the timer overflow interval, set the
timer counter value (TCW) to H'FE.
3. In prewrite-verify mode, P, E, PV, and EV
are all cleared to 0, and 12 V is applied to
the VPP pin. Read using a byte transfer
4. Programming time x is successively
incremented to initial set value 2n1
(n = 1 to 6). The initial value should
therefore be set to 15.8 s or less to make
the total programming time 1 ms or less.
5. tvs1: 4 s or more
N: 6 (set N so that the total programming
time does not exceed 1 ms)
End of programming
6. The start address and last address are the
start address and last address of the block
to be erased.

Enable watchdog timer *2

Select program mode

(P bit = 1 in FLMCR)
Wait (x) s *4
Clear P bit
Disable watchdog timer
Wait (tvs1) s *5

Double the programming time

(x 2 x)

NG

Prewrite verify *3
(read data H'00?)

n+1n
n N? *5

OK

No

Yes
*6

Last address?

Programming error

Address + 1 address

No

Yes
Clear erase block register
(clear bit for programmed block to 0)

End of prewrite

Figure 6.16 Prewrite Flowchart

137

Sample Program for Erasing One Block

This program uses the following registers:
R0:
R1H:
R2:
R3:
R4:

Used for erase block specification. Also stores address used in prewrite and erase-verify.
Stores read data. Also used in dummy write.
Stores last address of block to be erased.
Stores address used in prewrite and erase-verify.
Used for prewrite, prewrite-verify, erase, and erase-verify loop counter value setting. Also
stores register set values.
R5:
Used for prewrite and erase loop counter value setting.
R6L: Used for prewrite-verify and erase-verify fail count.
The values of #a, #b, #c, #d, and #e in the program depend on the operating frequency. They
should be set as indicated in tables 6.12 and 6.13. Erase block register (EBR1, EBR2) settings
should be made as indicated in sections 6.5.2 and 6.5.3 in section 6.5, Flash Memory Register
Descriptions. For #BLKSTR and #BLKEND, the start address and end address corresponding to
the set erase block register should be set as indicated in table 6.8.
FLMCR:
EBR1:
EBR2:
TCSRW:
TCW:

.EQU
.EQU
.EQU
.EQU
.EQU

H'FF80
H'FF82
H'FF83
H'FFBE
H'FFBF

.ALIGN
MOV.B #H'**,
MOV.B R0H,

2
R0H
@EBR*:8

;
; Set EBR *

; #BLKSTR is start address of block to be erased

; #BLKEND is last address of block to be erased
MOV.W #BLKSTR,
R0
; Start address of block to be erased
MOV.W #BLKEND,
R2
; Last address of block to be erased
ADDS
#1,
R2
; Last address of block to be erased + 1 R2

; Execute prewrite
MOV.W
PREWRT: MOV.B
MOV.W
PREWRS: INC
MOV.B
MOV.B
MOV.W
MOV.B
MOV.B
MOV.B
138

R0,
#H'00,
#H'a,
R6L
#H'00,
R1H,
#H'FE5A,
R4L,
R4H,
#H'36,

R3
R6L
R5

;
;
;
;
R1H
;
@R3
;
R4
;
@TCSRW:8 ;
@TCW:8
;
R4L
;

Start address of block to be erased

Prewrite verify fail counter
Set prewrite loop counter
Prewrite-vector fail counter + 1 R6L
Write H'00

LOOPR1:

LOOPR2:

MOV.B
MOV.W
BSET
SUBS
MOV.W
BNE
BCLR
MOV.B
MOV.B
MOV.B
DEC
BNE
MOV.B
BEQ
CMP.B
BEQ
ADD.W
BRA

R4L,
R5,
#0,
#1,
R4,
LOOPR1
#0,
#H'50,
R4L,
#H'c,
R4H
LOOPR2
@R3,
PWVFOK
#H'06,
ABEND1
R5,
PREWRS

ABEND1:

Write error

PWVFOK:

ADDS
CMP.W
BNE

; Execute erase
ERASES: MOV.W
MOV.W
ERASE:
ADDS
MOV.W
MOV.B
MOV.B
MOV.B
MOV.B
MOV.W
BSET
LOOPE:
NOP
NOP
NOP
NOP
SUBS
MOV.W
BNE
BCLR
MOV.B
MOV.B

@TCSRW:8
R4
@FLMCR:8
R4
R4

;
;
;
;
;
;
@FLMCR:8 ;
R4L
;
@TCSRW:8 ;
R4H
;
;
;
R1H
;
;
R6L
;
;
R5
;
;

Start watchdog timer

Set prewrite loop counter
Set P bit

Wait loop
Clear P bit
Stop watchdog timer
Set prewrite-verify fail counter
Wait loop
Read data = H'00?
If read data = H'00, branch to PWVFOK
Prewrite-verify executed 6 times?
If prewrite-verify executed 6 times, branch to ABEND1
Double the programming time
Prewrite again

#1,
R2,
PREWRT

R3
R3

; Address + 1 R3
; Last address?
; If not last address, prewrite next address

#H'0000,
#H'd,
#1,
#H'e5A,
R4L,
R4H,
#H'36,
R4L,
R5,
#1,

R6
R5
R6
R4
@TCSRW:8
@TCW:8
R4L
@TCSRW:8
R4
@FLMCR:8

;
;
;
;
;
;
;
;
;
;

#1,
R4,
LOOPE
#1,
#H'50,
R4L,

R4
R4

; Execute erase-verify
MOV.W R0,
MOV.B #H'b,
BSET
#3,

Erase-verify fail counter

Set erase loop counter
Erase-verify fail counter + 1 R6

Start watchdog timer

Set erase loop counter
Set E bit

;
;
; Wait loop
@FLMCR:8 ; Clear E bit
R4L
;
@TCSRW:8 ; Stop watchdog timer

R3
; Start address of block to be erased
R4H
; Set erase-verify loop counter
@FLMCR:8 ; Set EV bit
139

LOOPEV:

DEC
BNE
MOV.B
MOV.B
MOV.B
DEC
BNE
MOV.B
CMP.B
BNE
CMP.W
BNE
BRA

R4H
LOOPEV
#H'FF,
R1H,
#H'c,
R4H
LOOPDW
@R3+,
#H'FF,
RERASE
R2,
EVR2
OKEND

BCLR
SUBS
MOV.W
CMP.W
BPL
ADD.W

#3,
#1,
#H'0004,
R4,
BRER
R5,

@FLMCR:8
R3
R4
R6

BRER:

MOV.W
CMP.W
BNE
BRA

#H'025A,
R4,
ERASE
ABEND2

R4
R6

OKEND:

BCLR
MOV.B
MOV.B

#3,
#H'00,
R6L,

@FLMCR:8 ; Clear EV bit

R6L
;
@EBR*:8 ; Clear EBR*

EVR2:

LOOPDW:

RERASE:

One block erased

ABEND2:

140

Erase error

R1H
@R3
R4H

R1H
R1H
R3

R5

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

Wait loop
Dummy write
Set erase-verify loop counter
Wait loop
Read
Read data = H'FF?
If read data H'FF, branch to RERASE
Last address in block?

Clear EV bit
Erase-verify address 1 R3
Erase-verify fail count = 4?
If R6 4. branch to BRER (branch until R6 = 4602)
If R6 < 4, double erase time (executed only for R6 = 1, 2, 3)

;
; Erase-verify executed 602 times?
; If erase-verify not executed 602 times, erase again
; If erase-verify executed 602 times, branch to ABEND2

Flowchart for Erasing Multiple Blocks

Start
Set erase block register
(set bit for block to be erased to 1)
Write 0 data in all addresses to be
erased (prewrite)*1
n=1
Enable watchdog timer *2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms *5
Clear E bit

Erasing halts

Disable watchdog timer

Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tvs1) s *6
Erase-verify
next block

Set block start address as

verify address
Dummy write to verify address *3
(flash memory latches
address)

Notes: 1. Program all addresses to be erased by

following the prewrite flowchart.
2. Set the timer overflow interval to the initial
value shown in table 6.13.
3. For the erase-verify dummy write, write
H'FF using a byte transfer instruction.
4. For the erase-verify operation, read the
data using a byte transfer instruction.
When erasing multiple blocks, clear the
erase block register bits for erased blocks
and perform additional erasing only for
unerased blocks.
5. Erase time x is successively incremented
to initial set value 2n1 (n = 1 to 4), and is
fixed from the 4th time onward. An initial
value of 6.25 ms or less should be set, and
the time for one erasure should be 50 ms
or less.
6. tvs1: 4 s or more
tvs2: 2 s or more
N:
602 (set N so that the total erase
time does not exceed 30 s)

Wait (tvs2) s *6
Verify *4
(read data H'FF?)
Address + 1 address
No

Erase-verify next block

NG
Erase-verify
completed for all erase
blocks?

OK
Last address
of block?

No

Yes

Yes
Clear EBR bit for erase
block
n+1n
No

Erase-verify
completed for all erase
blocks?

n 4?

Yes

Yes
No

Clear EV bit
All erase
blocks erased?
(EBR1 = EBR2 = 0?)
Yes
End of erase

Double the erase time

(x 2 x)
No
n N? *6

No

Yes
Erase error

Figure 6.17 Multiple-Block Erase Flowchart

141

Sample Program for Erasing Multiple Blocks

This program uses the following registers:
R0:

Used for erase block specification (set as explained below). Also stores address used in
prewrite and erase-verify.
R1H: Used to test bits 8 to 11 of R0. Stores read data; used in dummy write.
R1L: Used to test bits 0 to 11 of R0.
R2:
Specifies address where address used in prewrite and erase-verify is stored.
R3:
Stores address used in prewrite and erase-verify.
R4:
Stores last address of block to be erased.
R5:
Used for prewrite and erase loop counter value setting.
R6L: Used for prewrite-verify and erase-verify fail count.
Arbitrary blocks can be erased by setting bits in R0. R0 settings should be made by writing with a
word transfer instruction.
A bit map of R0 and a sample setting for erasing specific blocks are shown below.
Bit:

15

14

13

12

R0

11

10

LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Corresponds to EBR1

Corresponds to EBR2

Note: Bits 15 to 12 should be cleared to 0.

Example: To erase blocks LB2, SB7, and SB0

Bit:

15

14

13

12

R0

11

10

Corresponds to EBR2
0

R0 is set as follows:
MOV.W
MOV.B
MOV.B

#H'0481, R0
R0H,
@EBR1
R0L,
@EBR2

The values of #a, #b, #c, #d, and #e in the program depend on the operating frequency. They
should be set as indicated in tables 6.12 and 6.13.

142

LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Corresponds to EBR1
0

Notes: 1. In this sample program, the stack pointer (SP) is set to address H'FF80. On-chip RAM
addresses H'FF7E and H'FF7F are used as a stack area. Therefore addresses H'FF7E
and H'FF7F should not be used when this program is executed, and on-chip RAM
should not be disabled.
2. It is assumed that this program, written in the ROM area, is transferred to the RAM
area and executed there. For #RAMSTR in the program, substitute the start address of
the RAM area to which the program is transferred. The value set for #RAMSTR must
be an even number.
FLMCR:
EBR1:
EBR2:
TCSRW:
TCW:
STACK:

.EQU
.EQU
.EQU
.EQU
.EQU
.EQU

H'FF80
H'FF82
H'FF83
H'FFBE
H'FFBF
H'FF80

START:

.ALIGN 2
MOV.W #STACK,

SP

; Set stack pointer

; Set R0 value as explained on previous page. This sample program erases

; all blocks.
MOV.W #H'0FFF,
R0
; Select blocks to be erased (R0: EBR1/EBR2)
MOV.B R0H,
@EBR1
; Set EBR1
MOV.B R0L,
@EBR2
; Set EBR2
; #RAMSTR is start address of RAM area to which program is transferred
; Set #RAMSTR to even number
MOV.W #RAMSTR, R2
; Transfer destination start address (RAM)
MOV.W #ERVADR, R3
;
ADD.W R3,
R2
; #RAMSTR + #ERVADR R2
MOV.W #START,
R3
;
SUB.W R3,
R2
; Address of data area used in RAM

PRETST:

EBR2PW:
PWADD1:

MOV.B
CMP.B
BEQ
CMP.B
BMI
MOV.B
SUBX
BTST
BNE
BRA
BTST
BNE
INC
MOV.W
BRA

#H'00,
#H'0C,
ERASES
#H'08,
EBR2PW
R1L,
#H'08,
R1H,
PREWRT
R1L,
PREWRT
R1L
@R2+,
PRETST

R1L
R1L
R1L
R1H
R1H
R0H
PWADD1
R0L

R3

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

Used to test bit R1L in R0

R1L = H'0C?
If finished checking all R0 bits, branch to ERASES
If R1L 8, EBR1 test; if R1L < 8, EBR2 test
R1L 8 R1H
Test bit R1H in EBR1 (R0H)
If bit R1H in EBR1 (R0H) is 1, branch to PREWRT
If bit R1H in EBR1 (R0H) is 0, branch to PWADD1
Test bit R1L in EBR2 (R0L)
If bit R1L in EBR2 (R0L) is 1, branch to PREWRT
R1L + 1 R1L
Dummy-increment R2

143

; Execute prewrite
PREWRT: MOV.W @R2+,
PREW:
MOV.B #H'00,
MOV.W #H'a,
PREWRS: INC
R6L
MOV.B #H'00
MOV.B R1H,
MOV.W #H'FE5A,
MOV.B R4L,
MOV.B R4H,
MOV.B #H'36,
MOV.B R4L,
MOV.W R5,
BSET
#0,
LOOPR1:

LOOPR2:

SUBS
MOV.W
BNE
BCLR
MOV.B
MOV.B
MOV.B

#1,
R4,
LOOPR1
#0,
#H'50,
R4L,
#H'c,

DEC
BNE
MOV.B
BEQ
CMP.B
BEQ
ADD.W
BRA

R4H
LOOPR2
@R3,
PWVFOK
#H'06,
ABEND1
R5,
PREWRS

ABEND1:

Write error

PWVFOK:

ADDS
MOV.W
CMP.W
BNE
INC
BRA

PWADD2:

; Execute erase
ERASES: MOV.W
MOV.W
ERASE:
ADDS
MOV.W
MOV.B
MOV.B
MOV.B
MOV.B
MOV.W
144

R3
R6L
R5

;
;
;
;
R1H
;
@R3
;
R4
;
@TCSRW:8 ;
@TCW:8
;
R4L
;
@TCSRW:8 ;
R4
;
@FLMCR:8 ;
;
;
;
@FLMCR:8 ;
R4L
;
@TCSRW:8 ;
R4H
;

Prewrite start address

Prewrite-verify fail counter
Set prewrite loop counter
Prewrite-verify fail counter + 1 R6H
Write H'00

Start watchdog timer

Set prewrite loop counter
Set P bit

R4
R4

R1H
R6L
R5

Wait loop
Clear P bit
Stop watchdog timer
Set prewrite-verify loop counter

;
;
;
;
;
;
;
;

Wait loop
Read data = H'00?
If read data = H'00, branch to PWVFOK
Prewrite-verify executed 6 times?
If prewrite-verify executed 6 times, branch to ABEND1
Double the programming time
Prewrite again

#1,
@R2,
R4,
PREW
R1L
PRETST

R3
R4
R3

;
;
;
;
;
;

Address + 1 R3
Start address of next block
Last address?
If not last address, prewrite next address
Used to test bit R1L+1 in R0
Branch to PRETST

#H'0000,
#H'd,
#1,
#H'e5A,
R4L,
R4H,
#H'36,
R4L,
R5,

R6
R5
R6
R4
@TCSRW:8
@TCW:8
R4L
@TCSRW:8
R4

;
;
;
;
;
;
;
;
;

Erase-verify fail counter

Set erase loop counter
Erase-verify fail counter + 1 R6

Start watchdog timer

Set erase loop counter

LOOPE:

BSET
NOP
NOP
NOP
NOP
SUBS
MOV.W
BNE
BCLR
MOV.B
MOV.B

#1,

@FLMCR:8 ; Set E bit

#1,
R4,
LOOPE
#1,
#H'50,
R4L,

R4
R4

;
;
; Wait loop
@FLMCR:8 ; Clear E bit
R4L
;
@TCSRW:8 ; Stop watchdog timer

; Execute erase-verify
EVR:
MOV.W #RAMSTR, R2
MOV.W #ERVADR, R3
ADD.W R3,
R2
MOV.W #START,
R3
SUB.W R3,
R2
MOV.B
MOV.B
BSET
DEC
BNE
CMP.B
BEQ
CMP.B
BMI
MOV.B
SUBX
BTST
BNE
BRA
BTST
BNE
INC
MOV.W
BRA

#H'00,
#H'b,
#3,
R4H
LOOPEV
#H'0C,
HANTEI
#H'08,
EBR2EV
R1L,
#H'08,
R1H,
ERSEVF
ADD01
R1L,
ERSEVF
R1L
@R2+,
EBRTST

ERASE1:

BRA

ERASE

ERSEVF:
EVR2:

MOV.W
MOV.B
MOV.B
MOV.B
DEC
BNE
MOV.B
CMP.B
BNE
MOV.W

@R2+,
#H'FF,
R1H,
#H'c,
R4H
LOOPEP
@R3+,
#H'FF,
BLKAD
@R2,

LOOPEV:
EBRTST:

EBR2EV:
ADD01:

LOOPEP:

; Transfer destination start address (RAM)

;
; #RAMSTR + #ERVADR R2
;
; Address of data area used in RAM

R1L
; Used to test bit R1L in R0
R4H
; Set erase-verify loop counter
@FLMCR:8 ; Set EV bit
;
; Wait loop
R1L
; R1L = H'0C?
; If finished checking all R0 bits, branch to HANTEI
R1L
;
; If R1L 8, EBR1 test; if R1L < 8, EBR2 test
R1H
;
R1H
; R1L 8 R1H
R0H
; Test bit R1H in EBR1 (R0H)
; If bit R1H in EBR1 (R0H) is 1, branch to ERSEVF
; If bit R1H in EBR1 (R0H) is 0, branch to ADD01
R0L
; Test bit R1L in EBR2 (R0L)
; If bit R1L in EBR2 (R0L) is 1, branch to ERSEVF
; R1L + 1 R1L
R3
; Dummy-increment R2
;
; Branch to ERASE via ERASE1
R3
R1H
@R3
R4H

R1H
R1H
R4

;
;
;
;
;
;
;
;
;
;

Start address of block to be erase-verified

Dummy write
Set erase-verify loop counter
Wait loop
Read
Read data = H'FF?
If read data H'FF, branch to BLKAD
Start address of next block

145

SBCLR:
BLKAD:

HANTEI:

BRER:

CMP.W
BNE

R4,
EVR2

R3

; Last address in block?

;

CMP.B
BMI
MOV.B
SUBX
BCLR
BRA
BCLR
INC
BRA

#H'08,
SBCLR
R1L,
#H'08,
R1H,
BLKAD
R1L,
R1L
EBRTST

R1L

;
;
;
;
;
;
;
;
;

BCLR
MOV.B
MOV.B
MOV.W
BEQ
MOV.W
CMP.W
BPL
ADD.W

#3,
R0H,
R0L,
R0,
EOWARI
#H'0004,
R4,
BRER
R5,

MOV.W
CMP.W
BNE
BRA

#H'025A,
R4,
ERASE1
ABEND2

R1H
R1H
R0H
R0L

@FLMCR:8
@EBR1:8
@EBR2:8
R4
R4
R6
R5
R4
R6

;
;
;
;
;
;
;
;
;

If R1L 8, EBR1 test; if R1L < 8, EBR2 test

R1L 8 R1H
Clear bit R1H in EBR1 (R0H)
Clear bit R1L in EBR2 (R0L)
R1L + 1 R1L

Clear EV bit

If EBR1/EBR2 = all 0s, normal end of erase

Erase-verify fail count = 4?
If R6 4. branch to BRER (branch until R6 = 4602)
If R6 < 4, double erase time (executed only for R6 = 1, 2, 3)

;
; Erase-verify executed 602 times?
; If erase-verify not executed 602 times, erase again
; If erase-verify executed 602 times, branch to ABEND2

;**** < Block address table used in erase-verify > ****

.ALIGN
2
ERVADR: .DATA.W H'0000
;
SB0
.DATA.W H'0080
;
SB1
.DATA.W H'0100
;
SB2
.DATA.W H'0180
;
SB3
.DATA.W H'0200
;
SB4
.DATA.W H'0400
;
SB5
.DATA.W H'0800
;
SB6
.DATA.W H'0C00
;
SB7
.DATA.W H'1000
;
LB0
.DATA.W H'2000
;
LB1
.DATA.W H'4000
;
LB2
.DATA.W H'6000
;
LB3
.DATA.W H'8000
;
FLASH END
EOWARI:
ABEND2:

146

; End of erase
; Erase error

Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of
#a, #b, #c, #d, and #e in the program examples depend on the clock frequency. Sample loop
counter settings for typical operating frequencies are shown in table 6.12. The value of #e should
be set as indicated in table 6.13.
As software loops are used, there is intrinsic error, and the calculated value and actual time may
not be the same. Therefore, initial values should be set so that the total write time does not exceed
1 ms, and the total erase time does not exceed 30 s.
The maximum number of writes in the program examples is set as N = 6.
Write and erase operations as shown in the flowcharts are achieved by setting the values of #a, #b,
#c, and #d in the program examples as indicated in table 6.12. Use the settings shown in table 6.13
for the value of #e.
In these sample programs, wait state insertion is disabled. If wait states are used, the setting should
be made after the end of the program.
The set value for the watchdog timer (WDT) overflow time is calculated on the basis of the
number of instructions including the write time and erase time from the time the watchdog timer is
started until it stops. Therefore, no other instructions should be added between starting and
stopping of the watchdog timer in these programs.
Table 6.12 Set Values of #a, #b, #c, and #d for Typical Operating Frequencies when
Sample Program is Executed in On-Chip Memory (RAM)
Oscillation Frequency
fOSC = 16 MHz fOSC = 10 MHz fOSC = 8 MHz

fOSC = 2 MHz

Operating Frequency
= 8 MHz

= 5 MHz

= 4 MHz

= 1 MHz

Meaning of Variable

Set Time

Counter Set Counter Set Counter Set Counter Set

Value
Value
Value
Value

a ()

Programming time
(initial set value)

15.8 s

H'000F

H'0009

H'0007

H'0001

b ()

tvs1

4 s

H'06

H'04

H'03

H'01

c ()

tvs2

2 s

H'03

H'02

H'01

H'01

d ()

Erase time (initial

set value)

6.25 ms

H'0C34

H'07A1

H'061A

H'0186

147

Formula:
If an operating frequency other than those shown in table 6.12 is used, the values can be calculated
using the formula shown below. The calculation is based on an operating frequency () of 5 MHz.
For a () and d (), after decimal calculation, round down the first decimal place and convert to
hexadecimal so that a () and d () are 15.8 s or less and 6.25 ms or less, respectively.
For b () and c (), after decimal calculation, round up the first decimal place and convert to
hexadecimal so that b () and c () are 4 s or more and 2 s or more, respectively.
a () to d () =

Operating frequency [MHz]

5

a ( = 5) to d ( = 5)

Examples:
Sample calculations when executing a program in on-chip memory (RAM) at an operating
frequency of 6 MHz
a () =

6
5

9 = 10.8 10 = H'000A

b () =

6
5

4.8

= H'05

c () =

6
5

2.4

= H'03

d () =

6
5

1953 = 2343.6 2343 = H'0927

Table 6.13 Watchdog Timer Overflow Interval Settings (Set Value of #e for Operating
Frequencies)
Oscillation Frequency
fOSC = 16 MHz

fOSC = 10 MHz

fOSC = 8 MHz

fOSC = 2 MHz

Operating Frequency
Variable

= 8 MHz

= 5 MHz

= 4 MHz

= 1 MHz

e ()

H'9B

H'DF

H'E5

H'F7

148

6.7.7

Prewrite-Verify Mode

Prewrite-verify mode is a verify mode used to all bits to equalize their threshold voltages before
erasure.
To program all bits, write H'00 in accordance with the prewrite algorithm shown in figure 6.16.
Use this procedure to set all data in the flash memory to H'00 after programming. After the
necessary programming time has elapsed, exit program mode (by clearing the P bit to 0) and select
prewrite-verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a
prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is
read in this state, the data at the read address will be read. After selecting prewrite-verify mode,
wait at least 4 s before reading.
Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing
program.
6.7.8

Protect Modes

There are two modes for flash memory program/erase protection: hardware protection and
software protection. These two protection modes are described below.
Software Protection: With software protection, setting the P or E bit in the flash memory control
register (FLMCR) does not cause a transition to program mode or erase mode.
Details of software protection are given below.
Functions
Item

Description

Program

Erase

Verify*

Block
protect

Programming and erase protection can be

set for individual blocks by settings in the
erase block registers (EBR1 and EBR2).

Disabled

Disabled

Enabled

Setting EBR1 to H'F0 and EBR2 to H'00

places all blocks in the program/eraseprotected state.
Note: * Three modes: program-verify, erase-verify, and prewrite-verify.

149

Hardware Protection: Hardware protection refers to a state in which programming/erasing of

flash memory is forcibly suspended or disabled. At this time, the flash memory control register
(FLMCR) and erase block register (EBR1 and EBR2) settings are cleared.
Details of the hardware protection states are given below.
Functions
Erase

Verify*1

When 12 V is not being applied to the Disabled

FV PP pin, FLMCR, EBR1, and EBR2
are initialized, and the program/eraseprotected state is entered. To obtain
this protection, the VPP voltage should
not exceed the V CC power supply
voltage.*3

Disabled*2

Disabled

In a reset, (including a watchdog timer Disabled

reset), and in sleep, subsleep, watch,
and standby mode, FLMCR, EBR1,
and EBR2 are initialized, and the
program/erase-protected state is
entered. In a reset via the RES pin, the
reset state is not reliably entered
unless the RES pin is held low for at
least 20 ms (oscillation settling time)*4
after powering on. In the case of a
reset during operation, the RES pin
must be held low for a minimum of 10
system clock cycles (10).

Disabled*2

Disabled

Item

Description

Programming
voltage (FVPP )
protect

Reset/standby
protect

Notes: 1.
2.
3.
4.

6.7.9

Program

Three modes: program-verify, erase-verify, and prewrite-verify.

All blocks are erase-disabled, and individual block specification is not possible.
For details, see section 6.9, Flash Memory Programming and Erasing Precautions.
For details, see AC Characteristics in section 13, Electrical Characteristics.

Interrupt Handling during Flash Memory Programming/Erasing

If an interrupt is generated while the flash memory is being programmed or erased (while the P or
E bit is set in FLMCR), an operating state may be entered in which the vector will not be read
correctly in the exception handling sequence, resulting in program runaway. All interrupt sources
should therefore be masked to prevent interrupt generation while programming or erasing the flash
memory.

150

6.8

Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF)

6.8.1

PROM Mode Setting

The H8/3644F, H8/3643F, and H8/3642AF, in which the on-chip ROM is flash memory, have a
PROM mode as well as the on-board programming modes for programming and erasing flash
memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose
PROM programmer.
6.8.2

Socket Adapter and Memory Map

For program writing and verification, a special-purpose 100-to-32-pin adapter is mounted on the
PROM programmer. Socket adapter product codes are listed in table 6.14.
Figure 6.18 shows the memory map in PROM mode. Figure 6.19 shows the socket adapter pin
interconnections.
Table 6.14 Socket Adapter Product Codes
MCU Product Code

Package

Socket Adapter Product Code

HD64F3644H

64-pin QFP (FP-64A)

Under development

HD64F3644P

64-pin SDIP (DP-64S)

Under development

HD64F3644W

80-pin TQFP (TFP-80C)

Under development

HD64F3643H

64-pin QFP (FP-64A)

Under development

HD64F3643P

64-pin SDIP (DP-64S)

Under development

HD64F3643W

80-pin TQFP (TFP-80C)

Under development

HD64F3642AH

64-pin QFP (FP-64A)

Under development

HD64F3642AP

64-pin SDIP (DP-64S)

Under development

HD64F3642AW

80-pin TQFP (TFP-80C)

Under development

151

MPU mode

H8/3644F

H'0000

PROM mode
H'0000

On-chip ROM area

H'7FFF*

H'7FFF*

1 output

H'1FFFF
Note: * This example applies to the H8/3644F. This address
is H'5FFF in the H8/3643F, and H'3FFF in the H8/3642AF.

Figure 6.18 Memory Map in PROM Mode

152

H8/3644F, H8/3643F, H8/3642AF

HN28F101 (32-pin)

Pin #
Pin name
TFP-80C

FP-64A

DP-64S

13
19
65
66
64
31
32
33
34
35
36
37
38
57
56
55
54
52
51
50
49
69
70
71
43
44
45
46
47
22, 23, 24,
25, 26, 27,
28, 29,
76, 74, 5

11
16
51
52
50
25
26
27
28
29
30
31
32
46
45
44
43
42
41
40
39
55
56
57
34
35
36
37
38
19, 20, 21,
22, 23, 24,
62, 60,
4, 17, 18

19
24
59
60
58
33
34
35
36
37
38
39
40
54
53
52
51
50
49
48
47
63
64
1
42
43
44
45
46
25, 26, 27,
28, 29, 30,
31, 32,
4, 6, 12

75, 7
72
42
4
8, 11
12
9, 10

61, 6
58
33
3
7
10
8, 9
Other pins

5, 14
2
41
11
15
18
16, 17

Socket adapter
FVPP
IRQ0
P31
P30
P32
P50
P51
P52
P53
P54
P55
P56
P57
P87
P86
P85
P84
P83
P82
P81
P80
P15
P16
P17
P73
P74
P75
P76
P77
P60, P61,
P62, P63,
P64, P65,
P66, P67,
PB4, PB6,
TEST
PB5, X1
AVCC
VCC
AVSS
VSS
RES
OSC1, OSC2
NC (OPEN)

Pin name
VPP
FA9
FA16
FA15
WE
FO0
FO1
FO2
FO3
FO4
FO5
FO6
FO7
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
OE
FA10
FA11
FA12
FA13
FA14
CE
VCC
VSS

Pin #
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16

Legend:
FVPP/VPP:

Power-on reset circuit

Oscillator circuit

Programming power
supply
FO7 to FO0: Data input/output
FA16 to FA0: Address input
OE:
Output enable
CE:
Chip enable
WE:
Write enable

Figure 6.19 Socket Adapter Pin Correspondence (F-ZTAT)

153

6.8.3

Operation in PROM Mode

The program/erase/verify specifications in PROM mode are the same as for the standard
HN28F101 flash memory. The H8/3644F, H8/3643F, and H8/3642AF do not have a device
recognition code, so the programmer cannot read the device name automatically. Table 6.15 shows
how the different operating modes are selected when using PROM mode.
Table 6.15 Operating Mode Selection In PROM Mode
Pins
FVPP

VCC

CE

OE

WE

D7 to D0

A16 to A0

Read

VCC*

VCC

Data output

Address input

Output disable

VCC*

VCC

High impedance

Standby

VCC*

VCC

High impedance

Read

VPP

VCC

Data output

Output disable

VPP

VCC

High impedance

Standby

VPP

VCC

High impedance

Write

VPP

VCC

Data input

Mode
Read

Command
write

Note: * In these states, the FVPP pin must be set to VCC.

Legend:
L: Low level
H: High level
VPP : VPP level
VCC: VCC level
X: Dont care

VH: 11, 5 V VH 12.5 V

154

Table 6.16 PROM Mode Commands

1st Cycle

2nd Cycle

Command

Cycles

Mode

Address

Data

Mode

Address

Data

Memory read

Write

H'00

Read

RA

Dout

Erase setup/erase

Write

H'20

Write

H'20

Erase-verify

Write

EA

H'A0

Read

EVD

Auto-erase setup/
auto-erase

Write

H'30

Write

H'30

Program setup/
program

Write

H'40

Write

PA

PD

Program-verify

Write

H'C0

Read

PVD

Reset

Write

H'FF

Write

H'FF

PA:
EA:
RA:
PD:
PVD:
EVD:

Program address
Erase-verify address
Read address
Program data
Program-verify output data
Erase-verify output data

155

High-Speed, High-Reliability Programming: Unused areas of the flash memory in the

H8/3644F, H8/3643F, or H8/3642AF contain H'FF data (initial value). The flash memory uses a
high-speed, high-reliability programming procedure. This procedure provides higher programming
speed without subjecting the device to voltage stress and without sacrificing the reliability of the
programmed data.
Figure 6.20 shows the basic high-speed, high-reliability programming flowchart. Tables 6.17 and
6.18 list the electrical characteristics during programming.

Start
Set VPP = 12.0 V 0.6 V
Address = 0
n=0
n+1n
Program setup command
Program command
Wait (25 s)
Program-verify command
Wait (6 s)
Address + 1 address
Verification?
OK
No

Last address?

No good

n = 20?
Yes

Yes
Set VPP = VCC

End

Error

Figure 6.20 High-Speed, High-Reliability Programming

156

No

High-Speed, High-Reliability Erasing: The flash memory in the H8/3644F, H8/3643F, and
H8/3642AF uses a high-speed, high-reliability erasing procedure. This procedure provides higher
erasing speed without subjecting the device to voltage stress and without sacrificing the reliability
of data reliability.
Figure 6.21 shows the basic high-speed, high-reliability erasing flowchart. Tables 6.17 and 6.18
list the electrical characteristics during erasing.

Start
Program all bits to 0*
Address = 0
n=0
n+1n
Erase setup/erase command
Wait (10 ms)
Erase-verify command
Wait (6 s)
Address + 1 address
Verification?
OK
No

No good
n = 3000?

No

Yes

Last address?
Yes
End

Error

Note: * Follow the high-speed, high-reliability programming flowchart in programming all bits.
If 0 has already been written, perform programming for unprogrammed bits.

Figure 6.21 High-Speed, High-Reliability Erasing

157

Table 6.17 DC Characteristics in PROM Mode

(Conditions: VCC = 5.0 V 10%, VPP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C)
Item

Symbol Min

Typ

Max

Unit

Input high
voltage

FO7 to FO0, FA 16 to FA0, VIH

OE, CE, WE

2.2

VCC + 0.3 V

Input low
voltage

FO7 to FO0, FA 16 to FA0, VIL

OE, CE, WE

0.3

0.8

Test Conditions

Output high FO7 to FO0

voltage

VOH

2.4

I OH = 200 A

Output low
voltage

FO7 to FO0

VOL

0.45

I OL = 1.6 mA

Input
leakage
current

FO7 to FO0, FA 16 to FA0, | ILI |

OE, CE, WE

Vin = 0 to VCC

VCC
current

Read

I CC

40

80

mA

Program

I CC

40

80

mA

Erase

I CC

40

80

mA

Read

I PP

10

VPP = 2.7 to 5.5 V

10

20

mA

VPP = 12.6 V

FV PP
current

158

Program

I PP

20

40

mA

VPP = 12.6 V

Erase

I PP

20

40

mA

VPP = 12.6 V

Table 6.18 AC Characteristics in PROM Mode

(Conditions: VCC = 5.0 V 10%, VPP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C)
Item

Symbol

Min

Typ

Max

Unit

Test
Conditions

Command write cycle

t CWC

120

ns

Figure 6.21

Address setup time

t AS

ns

Figure 6.22*

Address hold time

t AH

60

ns

Figure 6.23

Data setup time

t DS

50

ns

Data hold time

t DH

10

ns

CE setup time

t CES

ns

CE hold time

t CEH

ns

VPP setup time

t VPS

100

ns

VPP hold time

t VPH

100

ns

WE programming pulse width

t WEP

70

ns

WE programming pulse high time

t WEH

40

ns

OE setup time before command write

t OEWS

ns

OE setup time before verify

t OERS

Verify access time

t VA

500

ns

OE setup time before status polling

t OEPS

120

ns

Status polling access time

t SPA

120

ns

Program wait time

t PPW

25

Erase wait time

t ET

11

ms

Output disable time

t DF

40

ns

Total auto-erase time

t AET

0.5

30

Note: The CE, OE, and WE pins should be driven high during transitions of VPP from 5 V to 12 V
and from 12 V to 5 V.
* Input pulse level: 0.45 V to 2.4 V
Input rise time and fall time 10 ns
Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output

159

Auto-erase
and status polling

Auto-erase setup
VCC
VPP

5.0 V
12 V
5.0 V

tVPS

tVPH

Address
CE
tCEH
tCES

OE

tCWC
tWEP

tOEWS

tCEH

tOEPS
tWEP

tAET

tWEH

WE
tDS
I/O7

tCES

tCES

tDH
Command
input

tDF
tDS

tDH

tSPA

Command
input

Status polling
I/O0 to I/O6

Command
input

Command
input

Figure 6.22 Auto-Erase Timing

160

Program setup
VCC
VPP

Program

Program-verify

5.0 V
12 V
5.0 V

tVPS
tVPH

Address

Valid address

tAH

tAS
CE

tCEH
tCES

OE

tWEP
tOEWS

tCWC
tCEH

tCES
tPPW

tCES t
WEP

tCEH

tWEP

tOERS

tWEH

WE

tDH

tDS

tVA
tDH

tDS

tDH

tDS

tDF

I/O7

Command
input

Command
input

Command
input

Valid data
output

I/O0 to I/O6

Command
input

Command
input

Command
input

Valid data
output

Note: Program-verify data output values maybe intermediate between 1 and 0 if programming is
insufficient.

Figure 6.23 High-Speed, High-Reliability Programming Timing

161

Erase setup
VCC
VPP

Erase

Erase -verify

5.0 V
12 V
5.0 V

tVPS
tVPH
Valid address
tAS
tAH

Address

CE

OE

tOEWS
tCES

tCWC
tWEP

WE

tCEH
tDS

I/O0 to I/O7

tCEH
tCES

tDH

Command
input

tCES

tWEP

tET

tCEH
tOERS

tWEP

tWEH

tVA
tDS

tDH

Command
input

tDS

tDH

Command
input

tDF
Valid data
output

Note: Erase -verify data output values maybe intermediate between 1 and 0 if erasing is insufficient.

Figure 6.24 Erase Timing

162

6.9

Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming modes and PROM mode are
summarized below.
1. Program with the specified voltages and timing.
The rated programming voltage (VPP ) of the flash memory is 12.0 V.
If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V.
Applied voltages in excess of the rating can permanently damage the device. In particular,
insure that the peak overshoot of the PROM programmer does not exceed the maximum rating
of 13 V.
2. Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
3. Do not touch the socket adapter or chip while programming. Touching either of these can
cause contact faults and write errors.
4. Set H'FF as the PROM programmer buffer data for the following addresses:
H8/3644F: H'8000 to H'1FFFF
H8/3643F: H'6000 to H'1FFFF
H8/3642AF: H'4000 to H'1FFFF
The size of the PROM area is 32 kbytes in the H8/3644F, 24 kbytes in the H8/3643F, and 16
kbytes in the H8/3642AF. The addresses shown above always read H'FF, so if H'FF is not
specified as programmer data, a block error will occur.
5. Precautions in applying, releasing, and cutting*1 the programming voltage (VPP )
a. Apply the programming voltage (V PP ) after VCC has stabilized, and release VPP before
cutting VCC.
To avoid programming or erasing flash memory by mistake, VPP should only be applied,
released, and cut when the MCU is in a stable operating condition as described below.
MCU stable operating condition
The VCC voltage must be within the rated voltage range (VCC = 2.7 V to 5.5 V).
If the VPP voltage is applied, released, or cut while VCC is not within its rated voltage
range (VCC = 2.7 V to 5.5 V), since the MCU is unstable, the flash memory may be
programmed or erased by mistake. This can occur even if V CC = 0 V. Adequate
power supply measures should be taken, such as the insertion of a bypass capacitor,
to prevent fluctuation of the VCC power supply when VPP is applied.
163

 Oscillation must have stabilized (following the elapse of the oscillation settling
time) or be stopped.
When the VCC power is turned on, hold the RES pin low for the duration of the
oscillation settling time*2 (t rc = 20 ms) before applying VPP.
The MCU must be in the reset state, or in a state in which reset has ended normally
(reset has been released) and flash memory is not being accessed.
Apply or release VPP either in the reset state, or when the CPU is not accessing flash
memory (when a program in on-chip RAM or external memory is executing). Flash
memory data cannot be read normally at the instant when VPP is applied or released,
so do not read flash memory while V PP is being applied or released.
For a reset during operation, apply or release VPP only after the RES pin has been
held low for at least 10 system clock cycles (10).
The P and E bits must be cleared in the flash memory control register (FLMCR).
When applying or releasing V PP , make sure that the P or E bit is not set by mistake.
There must be no program runaway.
When V PP is applied, program execution must be supervised, e.g. by the watchdog
timer.
These power-on and power-off timing requirements for VCC and VPP should also be
satisfied in the event of a power failure and in recovery from a power failure. If these
requirements are not satisfied, overprogramming or overerasing may occur due to
program runaway, etc., which could cause memory cells to malfunction.
b. The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP
pin. The threshold level is approximately in the range from VCC +2 V to 11.4 V.
When this flag is set, it becomes possible to write to the flash memory control register
(FLMCR) and the erase block registers (EBR1 and EBR2), even though the VPP voltage
may not yet have reached the programming voltage range of 12.0 V 0.6 V.
Do not actually program or erase the flash memory until VPP has reached the programming
voltage range.
The programming voltage range for programming and erasing flash memory is 12.0 V 0.6
V (11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this
range. When not programming or erasing the flash memory, insure that the VPP voltage
does not exceed the VCC voltage. This will prevent unintentional programming and erasing.
Notes: 1. Definitions of V PP application, release, and cut-off are as follows:
Application: Raising the voltage from VCC to 12.0 V 0.6 V
Release:
Dropping the voltage from 12.0 V 0.6 V to VCC
Cut-off:
Halting voltage application (floating state)
2. The time depends on the resonator used; refer to the electrical characteristics.

164

tOSC1

3.0 to 5.5 V
VCC

0 s min.

0 s min.

12 0.6 V
VCC + 2 V to 11.4 V
0 s min.
Timing of boot
program branch
to RAM space

VCCV
VPP
(boot mode)

0 to VCCV

12 0.6 V

VCCV
VPP
(user program
mode)

0 to VCCV

RES

Period during which flash memory access

is prohibited and VPP flag set/clear period

Min. 10 cycles
(When RES is low)

Figure 6.25 VPP Power-On and Cut-Off Timing

6. Do not apply 12 V to the FVPP pin during normal operation.
To prevent erroneous programming or erasing due to program runaway, etc., apply 12 V to the
FVPP pin only when programming or erasing flash memory. If overprogramming or
overerasing occurs due to program runaway, etc., the memory cells may not operate normally.
A system configuration in which a high level is constantly applied to the FVPP pin should be
avoided. Also, while a high level is applied to the FVPP pin, the watchdog timer should be
activated to prevent overprogramming or overerasing due to program runaway, etc.

165

7. Design a current margin into the programming voltage (V PP ) power supply.

Insure that VPP remains within the range 12.0 V 0.6 V (11.4 V to 12.6 V) during
programming and erasing. Programming and erasing may become impossible outside this
range.
8. Insure that peak overshoot at the FV PP and TEST pins does not exceed the maximum rating.
Connect bypass capacitors as close as possible to the FVPP and TEST pins.
In boot mode start-up, also, bypass capacitors should be connected to the TEST pin in the same
way.

12 V

FVPP
H8/3644F
1.0 F

0.01 F

Figure 6.26 Example of VPP Power Supply Circuit Design

9. Use the recommended algorithms when programming and erasing flash memory.
The recommended algorithms enable programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
program (P) or erase (E) bit in the flash memory control register (FLMCR), the watchdog
timer should be set beforehand to prevent the specified time from being exceeded.
10. For comments on interrupt handling while flash memory is being programmed or erased, see
section 6.7.9, Interrupt Handling during Flash Memory Programming/Erasing.
11. Notes on accessing flash memory control registers
a. Flash memory control register access state in each operating mode
The H8/3644F, H8/3643F, and H8/3642AF have flash memory control registers located at
addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can
only be accessed when 12 V is applied to the flash memory programming power supply
pin, FV PP .

166

b. To check for 12 V application/non-application in user mode

When address H'FF80 is accessed in user mode, if 12 V is being applied to FVPP, FLMCR
is read/written to, and its initial value after reset is H'80. When 12 V is not being applied to
FVPP , FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit
7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether or not 12 V is
applied to FVPP , application or release of 12 V to FVPP cannot be determined simply from
the 0 or 1 status of this bit. A byte data comparison is necessary to check whether 12V is
being applied. The relevant coding is shown below.

LABEL1:

.
.
MOV.B
CMP.B
BEQ
.
.
.

@H'FF80, R1L
#H'FF, R1L
LABEL1

Sample program for detection of 12 V application to FVPP (user mode)

Table 6.19 Flash Memory DC Characteristics

VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVREF = 3.0 V to AVCC, VSS = AVSS = 0 V,
VPP = 12.0 V 0.6 V
Ta = 20C to +75C (regular specifications), Ta = 40C to +85C (wide-range specifications)
Item

Symbol

Min

Typ

Max

Unit

Test Conditions

High voltage (12 V)

application criterion
level*

FV PP , TEST

VH

VCC + 2

11.4

FV PP current

Read

I PP

10

VPP = 2.7 to 5.5 V

10

20

mA

VPP = 12.6 V

Program

20

40

mA

Erase

20

40

mA

Note: * The high voltage application criterion level is as shown in the table above, but a setting of
12.0 V 0.6 V should be made in boot mode and when programming and erasing flash
memory.

167

Table 6.20 Flash Memory AC Characteristics

VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVREF = 3.0 V to AV CC, VSS = AVSS = 0 V,
VPP = 12.0 V 0.6 V
Ta = 20C to +75C (regular specifications), Ta = 40C to +85C (wide-range specifications)
Item
1,

Programming time* *
1,

Erase time* *

Reprogramming capability
Verify setup time 1*

Verify setup time 2*

1
4

Flash memory read setup time*

Symbol

Min

Typ

Max

Unit

tP

50

1000

tE

30

NWEC

100

Times

t VS1

t VS2

t FRS

50

100

Test Conditions

VCC 4.5 V
VCC 4.5 V

Notes: 1. Follow the program/erase algorithms shown in section 6 when making the settings.
2. Indicates the programming time per byte (the time during which the P bit is set in the
flash memory control register (FLMCR)). Does not include the program-verify time.
3. Indicates the time to erase all blocks (32 kB) (the time during which the E bit is set in
FLMCR). Does not include the prewrite time before erasing of the erase-verify time.
4. After powering on when using an external clock, when the programming voltage (V PP ) is
switched from 12 V to VCC, an interval at least equal to the read setup time must be
allowed to elapse before reading the flash memory.
When VPP is released, this specifies the setup time from the point at which the VPP
voltage reaches the VCC + 2 V level until the flash memory is read.

168

Section 7 RAM
7.1

Overview

The H8/3644 Series has 1 kbyte and 512 byte of high-speed static RAM on-chip. The RAM is
connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data
and word data.
7.1.1

Block Diagram

Figure 7-1 shows a block diagram of the on-chip RAM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'FB80

H'FB80

H'FB81

H'FB82

H'FB82

H'FB83

On-chip RAM
H'FF7E

H'FF7E

H'FF7F

Even-numbered
address

Odd-numbered
address

Figure 7-1 RAM Block Diagram

169

Section 8 I/O Ports

8.1

Overview

The H8/3644 Series is provided with three 8-bit I/O ports, three 5-bit I/O ports, two 3-bit I/O
ports, and one 8-bit input-only port. Table 8.1 indicates the functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions
to write data in PCR or PDR.
Block diagrams of each port are given in Appendix C I/O Port Block Diagrams.
Table 8.1

Port Functions

Port

Description

Port 1

Port 2

Port 3

Port 5

Pins

Other Functions

5-bit I/O port

P17/IRQ3/TRGV

Input pull-up MOS

selectable

P16 to P1 5/
IRQ2 to IRQ1

External interrupt 3, timer V trigger

input

Function
Switching
Register
PMR1

External interrupts 2 and 1

P14/PWM

14-bit PWM output

PMR1

P10/TMOW

Timer A clock output

PMR1

P22/TxD

SCI3 data output

PMR7

P21/RxD

SCI3 data input

SCR3

P20/SCK1

SCI3 clock input/output

SCR3,
SMR

3-bit I/O port

P32/SO 1

PMR3

Input pull-up MOS

selectable

P31/SI1

SCI1 data output (SO1), data input

(SI1), clock input/output (SCK1)

8-bit I/O port

P57 /INT7

INT interrupt 7

Input pull-up MOS

P56 /INT6

INT interrupt 6

TMIB

Timer B event input

P55/INT5/
ADTRG

INT interrupt 5

P54 to P5 0/
INT4 to INT0

INT interrupts 4 to 0

3-bit I/O port

P30/SCK1

A/D converter external trigger input

171

Table 8.1

Port Functions (cont)

Other Functions

Function
Switching
Register

P76/TMOV

Timer V compare-match output

TCSRV

P75/TMCIV

Timer V clock input

P74/TMRIV

Timer V reset input

Port

Description

Pins

Port 6

8-bit I/O port

P67 to P6 0

High-current
port
Port 7

5-bit I/O port

P77

P73
Port 8

8-bit I/O port

P87
P86/FTID

Timer X input capture D input

P85/FTIC

Timer X input capture C input

P84/FTIB

Timer X input capture B input

P83/FTIA

Timer X input capture A input

P82/FTOB

Timer X output compare B output

TOCR

P81/FTOA

Timer X output compare A output

TOCR

P80/FTCI

Timer X clock input

Port 9

5-bit I/O port

P90* to P94

Port B

8-bit input port

PB7 to PB 0/
AN 7 to AN0

A/D converter analog input

(AN7 to AN0)

Note: * There is no P9 0 function in the flash memory version since P9 0 is used as the FVPP pin.

172

8.2

Port 1

8.2.1

Overview

Port 1 is a 5-bit I/O port. Figure 8.1 shows its pin configuration.

P1 7 /IRQ 3 /TRGV
P1 6 /IRQ 2
P1 5 /IRQ 1

Port 1

P1 4 /PWM
P1 0 /TMOW

Figure 8.1 Port 1 Pin Configuration

8.2.2

Register Configuration and Description

Table 8.2 shows the port 1 register configuration.

Table 8.2

Port 1 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port data register 1

PDR1

R/W

H'00

H'FFD4

Port control register 1

PCR1

H'00

H'FFE4

Port pull-up control register 1

PUCR1

R/W

H'00

H'FFED

Port mode register 1

PMR1

R/W

H'04

H'FFFC

173

Port Data Register 1 (PDR1)

Bit

P17

P16

P15

P14

P10

Initial value

0*

0*

0*

Read/Write

R/W

R/W

R/W

R/W

R/W

Note: * Bits 3 to 1 are reserved; they are always read as 0 and cannot be modified.

PDR1 is an 8-bit register that stores data for port 1 pins P17 through P14 and P10. If port 1 is read
while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states.
If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Upon reset, PDR1 is initialized to H'00.
Port Control Register 1 (PCR1)
Bit

PCR17

PCR16

PCR15

PCR14

PCR10

Initial value

Read/Write

PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 through P1 4 and P10
functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in
PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR1 is initialized to H'00.
PCR1 is a write-only register, which is always read as all 1s.
Port Pull-Up Control Register 1 (PUCR1)
Bit

PUCR17 PUCR16 PUCR15 PUCR14

PUCR10

Initial value

0*

0*

0*

Read/Write

R/W

R/W

R/W

R/W

R/W

Note: * Bits 3 to 1 are reserved; they are always read as 0 and cannot be modified.

174

PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 through P14 and P10 is on
or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the
MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR1 is initialized to H'00.
Port Mode Register 1 (PMR1)
Bit

IRQ3

IRQ2

IRQ1

PWM

TMOW

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Upon reset, PMR1 is initialized to H'04.
Bit 7P17/IRQ3/TRGV Pin Function Switch (IRQ3): This bit selects whether pin
P1 7/IRQ3/TRGV is used as P17 or as IRQ3/TRGV.
Bit 7: IRQ3

Description

Functions as P1 7 I/O pin

Functions as IRQ3/TRGV input pin

(initial value)

Note: Rising or falling edge sensing can be designated for IRQ3. Rising, falling, or both edge
sensing can be designated for TRGV. For details on TRGV settings, see 9.4.2, Register
Descriptions.

Bit 6P16/IRQ2 Pin Function Switch (IRQ2): This bit selects whether pin P16/IRQ2 is used as
P1 6 or as IRQ2.
Bit 6: IRQ2

Description

Functions as P1 6 I/O pin

Functions as IRQ2 input pin

(initial value)

Note: Rising or falling edge sensing can be designated for IRQ2.

175

Bit 5P15/IRQ1 Pin Function Switch (IRQ1): This bit selects whether pin P15/IRQ1 is used as
P1 5 or as IRQ1.
Bit 5: IRQ1

Description

Functions as P1 5 I/O pin

Functions as IRQ1 input pin

(initial value)

Note: Rising or falling edge sensing can be designated for IRQ1.

Bit 4P14/PWM Pin Function Switch (PWM): This bit selects whether pin P14/PWM is used as
P1 4 or as PWM.
Bit 4: PWM

Description

Functions as P1 4 I/O pin

Functions as PWM output pin

(initial value)

Bit 3Reserved Bit: Bit 3 is reserved: it is always read as 0 and cannot be modified.
Bit 2Reserved Bit: Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bit 1Reserved Bit: Bit 1 is reserved: it is always read as 0 and cannot be modified.
Bit 0P10/TMOW Pin Function Switch (TMOW): This bit selects whether pin P10/TMOW is
used as P10 or as TMOW.
Bit 0: TMOW

Description

Functions as P1 0 I/O pin

Functions as TMOW output pin

176

(initial value)

8.2.3

Pin Functions

Table 8.3 shows the port 1 pin functions.

Table 8.3

Port 1 Pin Functions

Pin

Pin Functions and Selection Method

P17/IRQ3/TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR17 in PCR1.
IRQ3
PCR17
Pin function
P16/IRQ2/
P15/IRQ1

P17 input pin

P17 output pin

IRQ3/TRGV input pin

The pin function depends on bits IRQ2 and IRQ1 in PMR1 and bit PCR1 n in
PCR1.
(m = n 4, n = 6, 5)
IRQm
PCR1n
Pin function

P14/PWM

0
0

P1n input pin

P1n output pin

IRQm input pin

The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1.
PWM
PCR14
Pin function

P10/TMOW

P14 input pin

P14 output pin

PWM output pin

The pin function depends on bit TMOW in PMR1 and bit PCR1 0 in PCR1.
TMOW
PCR10
Pin function

P10 input pin

P10 output pin

TMOW output pin

Note: * Dont care

177

8.2.4

Pin States

Table 8.4 shows the port 1 pin states in each operating mode.
Table 8.4

Port 1 Pin States

Pins

Reset

Sleep

Subsleep Standby

Retains Retains
P17/IRQ3/TRGV Highimpedance
previous previous
P16/IRQ2
state
state
P15/IRQ1

Watch

Subactive Active

HighRetains Functional Functional

impedance* previous
state

P14/PWM
P10/TMOW
Note: * A high-level signal is output when the MOS pull-up is in the on state.

8.2.5

MOS Input Pull-Up

Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1
bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for
that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
PUCR1n
MOS input pull-up
Note: * Dont care
n = 7 to 4, 0

178

Off

On

Off

8.3

Port 2

8.3.1

Overview

Port 2 is a 3-bit I/O port, configured as shown in figure 8.2.

P2 2 /TXD
P2 1 /RXD

Port 2

P2 0 /SCK3

Figure 8.2 Port 2 Pin Configuration

8.3.2

Register Configuration and Description

Table 8.5 shows the port 2 register configuration.

Table 8.5

Port 2 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port data register 2

PDR2

R/W

H'00

H'FFD5

Port control register 2

PCR2

H'00

H'FFE5

Port Data Register 2 (PDR2)

Bit

P22

P21

P20

Initial value

0*

0*

0*

0*

0*

Read/Write

R/W

R/W

R/W

Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.

PDR2 is an 8-bit register that stores data for port 2 pins P22 to P20. If port 2 is read while PCR2
bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is
read while PCR2 bits are cleared to 0, the pin states are read.
Upon reset, PDR2 is initialized to H'00.

179

Port Control Register 2 (PCR2)

Bit

PCR22

PCR21

PCR20

Initial value

Read/Write

PCR2 is an 8-bit register for controlling whether each of the port 1 pins P22 to P20 functions as an
input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only
when the corresponding pin is designated in SCR3 as a general I/O pin.
Upon reset, PCR2 is initialized to H'00.
PCR2 is a write-only register, which is always read as all 1s.

180

8.3.3

Pin Functions

Table 8.6 shows the port 2 pin functions.

Table 8.6

Port 2 Pin Functions

Pin

Pin Functions and Selection Method

P22/TXD

The pin function depends on bit TXD in PMR7 and bit PCR22 in PCR2.
TXD

PCR22
Pin function
P21/RXD

P22 input pin

P22 output pin

TXD output pin

The pin function depends on bit RE in SCR3 and bit PCR2 1 in PCR2.
RE

PCR21
Pin function
P20/SCK3

P21 input pin

P21 output pin

RXD input pin

The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR,
and bit PCR2 0 in PCR2.
CKE1

CKE0

COM

PCR20

Pin function

P20 input pin

1
1

P20 output pin SCK 3 output

pin

*
SCK 3 input pin

Note: * Dont care

8.3.4

Pin States

Table 8.7 shows the port 2 pin states in each operating mode.
Table 8.7

Port 2 Pin States

Pins

Reset

Sleep

Subsleep

Standby

Watch

P22/TXD

Highimpedance

Retains
previous
state

Retains
previous
state

Highimpedance

Retains Functional Functional

previous
state

P21/RXD

Subactive Active

P20/SCK3

181

8.4

Port 3

8.4.1

Overview

Port 3 is a 8-bit I/O port, configured as shown in figure 8.3.

P3 2 /SO 1
P3 1 /SI1

Port 3

P3 0 /SCK1

Figure 8.3 Port 3 Pin Configuration

8.4.2

Register Configuration and Description

Table 8.8 shows the port 3 register configuration.

Table 8.8

Port 3 Registers

Name

Abbrev.

R/W

Initial Value

Address

Port data register 3

PDR3

R/W

H'00

H'FFD6

Port control register 3

PCR3

H'00

H'FFE6

Port pull-up control register 3

PUCR3

R/W

H'00

H'FFEE

Port mode register 3

PMR3

R/W

H'00

H'FFFD

Port mode register 7

PMR7

R/W

H'F8

H'FFFF

Port Data Register 3 (PDR3)

Bit

P32

P31

P30

Initial value

0*

0*

0*

0*

0*

Read/Write

R/W

R/W

R/W

Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.

182

PDR3 is an 8-bit register that stores data for port 3 pins P32 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
Port Control Register 3 (PCR3)
Bit

PCR32

PCR31

PCR30

Initial value

Read/Write

PCR3 is an 8-bit register for controlling whether each of the port 3 pins P32 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
Port Pull-Up Control Register 3 (PUCR3)
Bit

Initial value

0*

0*

0*

0*

0*

Read/Write

R/W

R/W

R/W

PUCR32 PUCR31 PUCR30

Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified.

PUCR3 controls whether the MOS pull-up of each of the port 3 pins P32 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.

183

Port Mode Register 3 (PMR3)

Bit

SO1

SI1

SCK1

Initial value

Read/Write

R/W

R/W

R/W

PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Upon reset, PMR3 is initialized to H'00.
Bits 7 to 3Reserved Bits: Bits 7 to 3 are reserved: they are always read as 0 and cannot be
modified.
Bit 2P32/SO1 Pin Function Switch (SO1): This bit selects whether pin P32/SO1 is used as P32
or as SO1.
Bit 2: SO1

Description

Functions as P3 2 I/O pin

Functions as SO 1 output pin

(initial value)

Bit 1P31/SI1 Pin Function Switch (SI1): This bit selects whether pin P31/SI1 is used as P31 or
as SI1.
Bit 1: SI1

Description

Functions as P3 1 I/O pin

Functions as SI1 input pin

(initial value)

Bit 0P30/SCK1 Pin Function Switch (SCK1): This bit selects whether pin P30/SCK1 is used as
P3 0 or as SCK 1.
Bit 0: SCK1

Description

Functions as P3 0 I/O pin

Functions as SCK1 I/O pin

184

(initial value)

Port Mode Register 7 (PMR7)

Bit

TXD

POF1

Initial value

Read/Write

R/W

R/W

PMR7 is an 8-bit read/write register that turns the PMOS transistors of pins and P32/SO1 on and
off.
Upon reset, PMR7 is initialized to H'F8.
Bits 7 to 3Reserved Bits: Bits 7 to 3 are reserved; they are always read as 1, and cannot be
modified.
Bit 2P22/TXD Pin Function Switch (TXD): Bit 2 selects whether pin P22/TXD is used as P22
or as TXD.
Bit 2: TXD

Description

Functions as P2 2 I/O pin

Functions as TXD output pin

(initial value)

Bit 1Reserved Bit: Bit 1 is reserved: it is always read as 0 and cannot be modified.
Bit 0P32/SO1 pin PMOS control (POF1): This bit controls the PMOS transistor in the P32/SO 1
pin output buffer.
Bit 0: POF1

Description

CMOS output

NMOS open-drain output

(initial value)

185

8.4.3

Pin Functions

Table 8.9 shows the port 3 pin functions.

Table 8.9

Port 3 Pin Functions

Pin

Pin Functions and Selection Method

P32/SO 1

The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3.
SO1
PCR32
Pin function

P31/SI1

0
0

P32 input pin

P32 output pin

SO1 output pin

The pin function depends on bit SI1 in PMR3 and bit PCR3 1 in PCR3.
SI1
PCR31
Pin function

P30/SCK1

P31 input pin

P31 output pin

SI 1 input pin

SCK1

CKS3

Pin function

186

The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit
PCR30 in PCR3.

PCR30

Note: * Dont care

0
P30 input pin

P30 output pin SCK 1 output

pin

SCK 1 input pin

8.4.4

Pin States

Table 8.10 shows the port 3 pin states in each operating mode.
Table 8.10 Port 3 Pin States
Pins

Reset

Sleep

Subsleep

Standby

P32/SO 1

Highimpedance

Retains
previous
state

Retains
previous
state

HighRetains Functional Functional

impedance* previous
state

P31/SI1
P30/SCK1

Watch

Subactive Active

Note: * A high-level signal is output when the MOS pull-up is in the on state.

8.4.5

MOS Input Pull-Up

Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3
bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR3n
PUCR3n
MOS input pull-up

Off

On

Off

Note: * Dont care

(n = 2 to 0)

187

8.5

Port 5

8.5.1

Overview

Port 5 is an 8-bit I/O port, configured as shown in figure 8.4.

P57/INT7
P56/INT6/TMIB
P55/INT5/ADTRG
P54/INT4

Port 5

P53/INT3
P52/INT2
P51/INT1
P50/INT0

Figure 8.4 Port 5 Pin Configuration

8.5.2

Register Configuration and Description

Table 8.11 shows the port 5 register configuration.

Table 8.11 Port 5 Registers
Name

Abbrev.

R/W

Initial Value

Address

Port data register 5

PDR5

R/W

H'00

H'FFD8

Port control register 5

PCR5

H'00

H'FFE8

Port pull-up control register 5

PUCR5

R/W

H'00

H'FFEF

188

Port Data Register 5 (PDR5)

Bit

P57

P56

P55

P54

P53

P52

P51

P50

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
Port Control Register 5 (PCR5)
Bit

PCR57

PCR56

PCR55

PCR54

PCR53

PCR52

PCR51

PCR50

Initial value

Read/Write

PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
Port Pull-Up Control Register 5 (PUCR5)
Bit

PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is
cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the
corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.

189

8.5.3

Pin Functions

Table 8.12 shows the port 5 pin functions.

Table 8.12 Port 5 Pin Functions
Pin

Pin Functions and Selection Method

P57/INT7

The pin function depends on bit PCR57 in PCR5.

PCR57
Pin function

P57 input pin

P57 output pin

INT7 input pin

P56/INT6/TMIB

The pin function depends on bit PCR56 in PCR5.

PCR56
Pin function

P56 input pin

P56 output pin

INT6 input pin and TMIB input pin

P55/INT5/

The pin function depends on bit PCR55 in PCR5.

ADTRG

PCR55
Pin function

P55 input pin

P55 output pin

INT5 input pin and ADTRG input pin

P54/INT4 to
P50/INT0

The pin function depends on bit PCR5n in PCR5.

(n = 4 to 0)
PCR5n
Pin function

P5n input pin

P5n output pin

INTn input pin

190

8.5.4

Pin States

Table 8.13 shows the port 5 pin states in each operating mode.
Table 8.13 Port 5 Pin States
Pins

Reset

Sleep

P57/INT7 to
P50/INT0

HighRetains
impedance previous
state

Subsleep

Standby

Watch

Subactive Active

Retains
previous
state

HighRetains Functional Functional

impedance* previous
state

Note: * A high-level signal is output when the MOS pull-up is in the on state.

8.5.5

MOS Input Pull-Up

Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5
bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR5n
PUCR5n
MOS input pull-up

Off

On

Off

Note: * Dont care

(n = 7 to 0)

191

8.6

Port 6

8.6.1

Overview

Port 6 is an 8-bit large-current I/O port, with a maximum sink current of 10 mA. The port 6 pin
configuration is shown in figure 8.5.

P67
P66
P65
P64

Port 6

P63
P62
P61
P60

Figure 8.5 Port 6 Pin Configuration

8.6.2

Register Configuration and Description

Table 8.14 shows the port 6 register configuration.

Table 8.14 Port 6 Registers
Name

Abbrev.

R/W

Initial Value

Address

Port data register 6

PDR6

R/W

H'00

H'FFD9

Port control register 6

PCR6

H'00

H'FFE9

Port Data Register 6 (PDR6)

Bit

P67

P66

P65

P64

P63

P62

P61

P60

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.

192

When a bit in PCR6 is set to 1, if port 6 is read the value of the corresponding PDR6 bit is
returned directly regardless of the pin state. When a bit in PCR6 is cleared to 0, if port 6 is read
the corresponding pin state is read.
Upon reset, PDR6 is initialized to H'00.
Port Control Register 6 (PCR6)
Bit

PCR67

PCR66

PCR65

PCR64

PCR63

PCR62

PCR61

PCR60

Initial value

Read/Write

PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
When a bit in PCR6 is set to 1, the corresponding pin of P67 to P60 becomes an output pin.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which always reads all 1s.
8.6.3

Pin Functions

Table 8.15 shows the port 6 pin functions.

Table 8.15 Port 6 Pin Functions
Pin

Pin Functions and Selection Method

P67 to P6 0

The pin function depends on bit PCR6n in PCR6

(n = 7 to 0)
PCR6n
Pin function

P6n input pin

P6n output pin

193

8.6.4 Pin States

Table 8.16 shows the port 6 pin states in each operating mode.
Table 8.16 Port 6 Pin States
Pins

Reset

Sleep

Subsleep Standby

P67 toP60

HighRetains Retains
impedance previous previous
state
state

Watch

HighRetains Functional Functional

impedance* previous
state

Note: * A high-level signal is output when the MOS pull-up is in the on state.

194

Subactive Active

8.7

Port 7

8.7.1

Overview

Port 7 is a 8-bit I/O port, configured as shown in figure 8.6.

P77
P76/TMOV
Port 7

P75/TMCIV
P74/TMRIV
P73

Figure 8.6 Port 7 Pin Configuration

8.7.2

Register Configuration and Description

Table 8.17 shows the port 7 register configuration.

Table 8.17 Port 7 Registers
Name

Abbrev.

R/W

Initial Value

Address

Port data register 7

PDR7

R/W

H'00

H'FFDA

Port control register 7

PCR7

H'00

H'FFEA

195

Port Data Register 7 (PDR7)

Bit

P77

P76

P75

P74

P73

Initial value

0*

0*

0*

Read/Write

R/W

R/W

R/W

R/W

R/W

Note: * Bits 2 to 0 are reserved; they are always read as 0 and cannot be modified.

PDR7 is an 8-bit register that stores data for port 7 pins P77 to P73. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
Port Control Register 7 (PCR7)
Bit

PCR77

PCR76

PCR75

PCR74

PCR73

Initial value

Read/Write

PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P73 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which always reads as all 1s.

196

8.7.3

Pin Functions

Table 8.18 shows the port 7 pin functions.

Table 8.18 Port 7 Pin Functions
Pin

Pin Functions and Selection Method

P77, P73

The pin function depends on bit PCR7n in PCR7.

(n = 7 or 3)
PCR7n
Pin function

P76/TMOV

P7n input pin

P7n output pin

The pin function depends on bit PCR76 in PCR7 and bits OS3 to OS0 in TCSRV.
OS3 to OS0
PCR76
Pin function

P75/TMCIV

0000

Not 0000

P76 input pin

P76 output pin

TMOV output pin

The pin function depends on bit PCR75 in PCR7.

PCR75
Pin function

P75 input pin

P75 output pin

TMCIV input pin

P74/TMRIV

The pin function depends on bit PCR74 in PCR7.

PCR74
Pin function

P74 input pin

P74 output pin

TMRIV input pin

Note: * Dont care

8.7.4

Pin States

Table 8.19 shows the port 7 pin states in each operating mode.
Table 8.19 Port 7 Pin States
Pins

Reset

Sleep

Subsleep Standby

P77 to P7 3

HighRetains Retains
impedance previous previous
state
state

Highimpedance

Watch

Subactive Active

Retains Functional Functional

previous
state

197

8.8

Port 8

8.8.1

Overview

Port 8 is an 8-bit I/O port configured as shown in figure 8.7.

P87
P86/FTID
P85/FTIC
P84/FTIB

Port 8

P83//FTIA
P82/FTOB
P81/FTOA
P80/FTCI

Figure 8.7 Port 8 Pin Configuration

8.8.2

Register Configuration and Description

Table 8.20 shows the port 8 register configuration.

Table 8.20 Port 8 Registers
Name

Abbrev.

R/W

Initial Value

Address

Port data register 8

PDR8

R/W

H'00

H'FFDB

Port control register 8

PCR8

H'00

H'FFEB

198

Port Data Register 8 (PDR8)

Bit

P87

P86

P85

P84

P83

P82

P81

P80

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
Port Control Register 8 (PCR8)
Bit

PCR87

PCR86

PCR85

PCR84

PCR83

PCR82

PCR81

PCR80

Initial value

Read/Write

PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an
input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.

199

8.8.3

Pin Functions

Table 8.21 shows the port 8 pin functions.

Table 8.21 Port 8 Pin Functions
Pin

Pin Functions and Selection Method

P87

The pin function depends on bit PCR87 in PCR8.

PCR87
Pin function

P86/FTID

P87 input pin

P87 output pin

The pin function depends on bit PCR86 in PCR8.

PCR86
Pin function

P86 input pin

P86 output pin

FTID input pin

P85/FTIC

The pin function depends on bit PCR85 in PCR8.

PCR85
Pin function

P85 input pin

P85 output pin

FTIC input pin

P84/FTIB

The pin function depends on bit PCR84 in PCR8.

PCR84
Pin function

P84 input pin

P84 output pin

FTIB input pin

P83/FTIA

The pin function depends on bit PCR83 in PCR8.

PCR83
Pin function

P83 input pin

P83 output pin

FTIA input pin

P82/FTOB

The pin function depends on bit PCR82 in PCR8 and bit OEB in TOCR.
OEB
PCR82
Pin function

Note: * Dont care

200

P82 input pin

P82 output pin

FTOB output pin

Table 8.21 Port 8 Pin Functions (cont)

Pin

Pin Functions and Selection Method

P81/FTOA

The pin function depends on bit PCR81 in PCR8 and bit OEA in TOCR.
OEA

PCR81
Pin function
P80/FTCI

P81 input pin

P81 output pin

FTOA output pin

The pin function depends on bit PCR80 in PCR8.

PCR80
Pin function

P80 input pin

P80 output pin

FTCI input pin

Note: * Dont care

8.8.4

Pin States

Table 8.22 shows the port 8 pin states in each operating mode.
Table 8.22
Pins

Port 8 Pin States

Reset

Sleep

Subsleep Standby

Retains Retains
P87 to P8 0/FTCI Highimpedance previous previous
state
state

Highimpedance

Watch

Subactive Active

Retains Functional Functional

previous
state

201

8.9

Port 9

8.9.1

Overview

Port 9 is a 5-bit I/O port, configured as shown in figure 8.8.

P9 4
P9 3
P9 2

Port 9

P9 1
P9 0 *

Note: * There is no P90 function in the flash memory version since P90 is used as the FVPP pin.

Figure 8.8 Port 9 Pin Configuration

8.9.2

Register Configuration and Description

Table 8.23 shows the port 9 register configuration.

Table 8.23 Port 9 Registers
Name

Abbrev.

R/W

Initial Value

Address

Port data register 9

PDR9

R/W

H'C0

H'FFDC

Port control register 9

PCR9

H'C0

H'FFEC

202

Port Data Register 9 (PDR9)

Bit

P94

P93

P92

P91

P90*3

Initial value

1*1

1*1

0*2

Read/Write

R/W

R/W

R/W

R/W

R/W

Notes: 1. Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified.
2. Bit 5 is reserved; it is always read as 0 and cannot be modified.
3. In the on-chip flash memory version, this bit is always read as 0 and cannot be
modified.

PDR9 is an 8-bit register that stores data for port 9 pins P94 to P90. If port 9 is read while PCR9
bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.
Upon reset, PDR9 is initialized to H'C0.
Port Control Register 9 (PCR9)
Bit

PCR94

PCR93

PCR92

PCR91

PCR90

Initial value

Read/Write

PCR9 controls whether each of the port 9 pins P94 to P90 functions as an input pin or output pin.
Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin.
Upon reset, PCR9 is initialized to H'C0.
PCR9 is a write-only register, which is always reads as all 1.

203

8.9.3

Pin Functions

Table 8.24 shows the port 9 pin functions.

Table 8.24 Port 9 Pin Functions
Pin

Pin Functions and Selection Method

P9n

The pin function depends on bit PCR9n in PCR9.

(n = 4 to 0)
PCR9n
Pin function

8.9.4

P9n input pin

P9n output pin

Pin States

Table 8.25 shows the port 9 pin states in each operating mode.
Table 8.25 Port 9 Pin States
Pins

Reset

P94 to P9 0

HighRetains Retains
impedance previous previous
state
state

204

Sleep

Subsleep Standby
Highimpedance

Watch

Subactive Active

Retains Functional Functional

previous
state

8.10

Port B

8.10.1

Overview

Port B is an 8-bit input-only port, configured as shown in figure 8.9.

PB7 /AN 7
PB6 /AN 6
PB5 /AN 5
PB4 /AN 4

Port B

PB3 /AN 3
PB2 /AN 2
PB1 /AN 1
PB0 /AN 0

Figure 8.9 Port B Pin Configuration

8.10.2

Register Configuration and Description

Table 8.26 shows the port B register configuration.

Table 8.26 Port B Register
Name

Abbrev.

R/W

Address

Port data register B

PDRB

H'FFDD

Port Data Register B (PDRB)

Bit

Read/Write

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.

205

8.10.3

Pin Functions

Table 8.27 shows the port B pin functions.

Table 8.27 Port B Pin Functions
Pin

Pin Functions and Selection Method

PBn/ANn

Always as below.
(n = 7 to 0)
Pin function

8.10.4

PBn input pin or ANn input pin

Pin States

Table 8.28 shows the port B pin states in each operating mode.
Table 8.28 Port B Pin States
Pins

Reset

Sleep

Subsleep

Standby

Watch

Subactive Active

PBn/ANn

HighHighHighHighHighHighHighimpedance impedance impedance impedance impedance impedance impedance

(n = 7 to 0)

206

Section 9 Timers
9.1

Overview

The H8/3644 Series provides five timers: timers A, B1, V, X, and a watchdog timer. The functions
of these timers are outlined in table 9.1.
Table 9.1

Timer Functions

Name

Functions

Timer A

8-bit timer

Internal Clock

Event
Input Pin

Waveform
Output Pin

Interval function

/8 to /8192
(8 choices)

Time base

W/128
(choice of 4
overflow periods)

Clock output

/4 to /32
W/4 to W /32
(8 choices)

TMOW

/4 to /8192
(7 choices)

TMIB

Timer B1

8-bit timer
Interval timer
Event counter

Timer V

8-bit timer
/4 to /128
(6 choices)
Event counter
Output control by dual
compare match
Counter clearing option
Count-up start by
external trigger input can
be specified

TMCIV

TMOV

Timer X

16-bit free-running timer /2 to /32

(3 choices)
2 output compare
channels
4 input capture channels
Counter clearing option
Event counter

FTCI
FTIA
FTIB
FTIC
FTID

FTOA
FTOB

Watchdog
timer

Reset signal generated

when 8-bit counter
overflows

/8192

Remarks

207

9.2

Timer A

9.2.1

Overview

Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal
divided from 32.768 kHz or from the system clock can be output at the TMOW pin.
Features
Features of timer A are given below.
Choice of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, /8).
Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
An interrupt is requested when the counter overflows.
Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or
4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4.

208

Block Diagram
Figure 9.1 shows a block diagram of timer A.

1/4

TMA

PSW

W /32
W /16
W /8
W /4

W /128

TMOW

256*

128*

64*

/8192, /4096, /2048,

/512, /256, /128,
/32, /8

8*

TCA
/32
/16
/8
/4

Internal data bus

W/4

PSS
IRRTA

Legend:
TMA:
TCA:
IRRTA:
PSW:
PSS:

Timer mode register A

Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S

Note: * Can be selected only when the prescaler W output (W/128) is used as the TCA input clock.

Figure 9.1 Block Diagram of Timer A

Pin Configuration
Table 9.2 shows the timer A pin configuration.
Table 9.2

Pin Configuration

Name

Abbrev.

I/O

Function

Clock output

TMOW

Output

Output of waveform generated by timer A output

circuit

209

Register Configuration
Table 9.3 shows the register configuration of timer A.
Table 9.3

Timer A Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register A

TMA

R/W

H'10

H'FFB0

Timer counter A

TCA

H'00

H'FFB1

9.2.2

Register Descriptions

Timer Mode Register A (TMA)

Bit

TMA7

TMA6

TMA5

TMA3

TMA2

TMA1

TMA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock.
Upon reset, TMA is initialized to H'10.
Bits 7 to 5Clock Output Select (TMA7 to TMA5): Bits 7 to 5 choose which of eight clock
signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in
active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in
active mode, sleep mode, and subactive mode.
Bit 7: TMA7

Bit 6: TMA6

Bit 5: TMA5

Clock Output

/32

/16

/8

/4

W/32

W/16

W/8

W/4

(initial value)

Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
210

Bits 3 to 0Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA.
The selection is made as follows.
Description
Bit 3:
TMA3

Bit 2:
TMA2

Bit 1:
TMA1

Bit 0:
TMA0

Prescaler and Divider Ratio

or Overflow Period

Function

PSS, /8192

Interval timer

PSS, /4096

PSS, /2048

PSS, /512

PSS, /256

PSS, /128

PSS, /32

PSS, /8

PSW, 1 s

PSW, 0.5 s

PSW, 0.25 s

PSW, 0.03125 s

PSW and TCA are reset

(initial value)

Clock time base

1
1

0
1

Timer Counter A (TCA)

Bit

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

Initial value

Read/Write

TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
211

9.2.3

Timer Operation

Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0,
timer A functions as an 8-bit interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see 3.3, Interrupts.
Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions
as a real-time clock time base by counting clock signals output by prescaler W. The overflow
period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.
In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to
their initial values of H'00.
Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be
output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7
to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and
sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep
mode, and subactive mode.

212

9.2.4

Timer A Operation States

Table 9.4 summarizes the timer A operation states.

Table 9.4

Timer A Operation States

Watch

Subactive

Subsleep

Standby

Reset

Functions Functions Halted

Halted

Halted

Halted

Reset

Functions Functions Functions Functions Functions Halted

Reset

Functions Retained Retained Functions Retained Retained

Operation Mode

Reset Active

TCA Interval
Clock time base
TMA

Sleep

Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ (s) in
the count cycle.

213

9.3

Timer B1

9.3.1

Overview

Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operation modes, interval and auto reload.
Features
Features of timer B1 are given below.
Choice of seven internal clock sources (/8192, /2048, /512, /256, /64, /16, /4) or an
external clock (can be used to count external events).
An interrupt is requested when the counter overflows.
Block Diagram
Figure 9.2 shows a block diagram of timer B1.

PSS

TCB1

TLB1

TMIB

IRRTB1

Legend:
TMB1: Timer mode register B1
TCB1: Timer counter B1
TLB1: Timer load register B1
IRRTB1: Timer B1 interrupt request flag
PSS:
Prescaler S

Figure 9.2 Block Diagram of Timer B1

214

Internal data bus

TMB1

Pin Configuration
Table 9.5 shows the timer B1 pin configuration.
Table 9.5

Pin Configuration

Name

Abbrev.

I/O

Function

Timer B1 event input

TMIB

Input

Event input to TCB1

Register Configuration
Table 9.6 shows the register configuration of timer B1.
Table 9.6

Timer B1 Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer mode register B1

TMB1

R/W

H'78

H'FFB2

Timer counter B1

TCB1

H'00

H'FFB3

Timer load register B1

TLB1

H'00

H'FFB3

9.3.2

Register Descriptions

Timer Mode Register B1 (TMB1)

Bit

TMB17

TMB12

TMB11

TMB10

Initial value

Read/Write

R/W

R/W

R/W

R/W

TMB1 is an 8-bit read/write register for selecting the auto-reload function and input clock.
Upon reset, TMB1 is initialized to H'78.
Bit 7Auto-Reload Function Select (TMB17): Bit 7 selects whether timer B1 is used as an
interval timer or auto-reload timer.
Bit 7: TMB17

Description

Interval timer function selected

Auto-reload function selected

(initial value)

215

Bits 6 to 3Reserved Bits: Bits 6 to 3 are reserved; they are always read as 1, and cannot be
modified.
Bits 2 to 0Clock Select (TMB12 to TMB10): Bits 2 to 0 select the clock input to TCB1. For
external event counting, either the rising or falling edge can be selected.
Bit 2: TMB12

Bit 1: TMB11

Bit 0: TMB10

Description

Internal clock: /8192

Internal clock: /2048

Internal clock: /512

Internal clock: /256

Internal clock: /64

Internal clock: /16

Internal clock: /4

External event (TMIB): rising or falling edge*

(initial value)

Note: * The edge of the external event signal is selected by bit INTEG6 in interrupt edge select
register 2 (IEGR2). See 3.3.2, Interrupt Control Registers, for details.

Timer Counter B1 (TCB1)

Bit

TCB17

TCB16

TCB15

TCB14

TCB13

TCB12

TCB11

TCB10

Initial value

Read/Write

TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in timer
mode register B1 (TMB1). TCB1 values can be read by the CPU at any time.
When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 bit in IRR1 is
set to 1.
TCB1 is allocated to the same address as TLB1.
Upon reset, TCB1 is initialized to H'00.

216

Timer Load Register B1 (TLB1)

Bit

TLB17

TLB16

TLB15

TLB14

TLB13

TLB12

TLB11

TLB10

Initial value

Read/Write

TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1).
When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as
well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in
auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set
within the range of 1 to 256 input clocks.
The same address is allocated to TLB1 as to TCB1.
Upon reset, TLB1 is initialized to H'00.
9.3.3

Timer Operation

Interval Timer Operation: When bit TMB17 in timer mode register B1 (TMB1) is cleared to 0,
timer B1 functions as an 8-bit interval timer.
Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer B1 is selected from seven internal clock
signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits
TMB12 to TMB10 of TMB1.
After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to
overflow, setting bit IRRTB1 to 1 in interrupt request register 1 (IRR1). If IENTB1 = 1 in
interrupt enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCB1 returns to H'00 and starts counting up again.
During interval timer operation (TMB17 = 0), when a value is set in timer load register B1
(TLB1), the same value is set in TCB1.
Note: * For details on interrupts, see 3.3, Interrupts.
Auto-Reload Timer Operation: Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as
an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into
TCB1, becoming the value from which TCB1 starts its count.

217

After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to
overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The
overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1
value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode.
In auto-reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also set in
TCB1.
Event Counter Operation: Timer B1 can operate as an event counter, counting rising or falling
edges of an external event signal input at pin TMIB. External event counting is selected by setting
bits TMB12 to TMB10 in timer mode register B1 (TMB1) to all 1s (111).
When timer B1 is used to count external event input, bit INTEN6 in IENR3 should be cleared to 0
to disable INT6 interrupt requests.
9.3.4

Timer B1 Operation States

Table 9.7 summarizes the timer B1 operation states.

Table 9.7

Timer B1 Operation States

Operation Mode

Reset

Active

Sleep

Watch

Subactive

Subsleep

Standby

TCB1 Interval

Reset

Functions

Functions

Halted

Halted

Halted

Halted

Reset

Functions

Functions

Halted

Halted

Halted

Halted

Reset

Functions

Retained

Retained

Retained Retained Retained

Auto reload
TMB1

218

9.4

Timer V

9.4.1

Overview

Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare
match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an
arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse
output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. The
trigger input signal is shared with the realtime port.
Features
Features of timer V are given below.
Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock (can
be used as an external event counter).
Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
Three interrupt sources: two compare match, one overflow
Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.

219

Block Diagram
Figure 9.3 shows a block diagram of timer V.

TCRV1

TCORB
Trigger
control

TRGV

Comparator

TCNTV
Internal data bus

Clock select

TMCIV

Comparator

PSS
TCORA

TMRIV

Clear control

TCRVO
Interrupt
request
control

TMOV

Output
control

TCSRV

Legend:
TCORA:
TCORB:
TCNTV:
TCSRV:
TCRV0:
TCRV1:
PSS:
CMIA:
CMIB:
OVI:

Time constant register A

Time constant register B
Timer counter V
Timer control/status register V
Timer control register V0
Timer control register V1
Prescaler S
Compare-match interrupt A
Compare-match interrupt B
Overflow interrupt

Figure 9.3 Block Diagram of Timer V

220

CMIA
CMIB
OVI

Pin Configuration
Table 9.8 shows the timer V pin configuration.
Table 9.8

Pin Configuration

Name

Abbrev.

I/O

Function

Timer V output

TMOV

Output

Timer V waveform output

Timer V clock input

TMCIV

Input

Clock input to TCNTV

Timer V reset input

TMRIV

Input

External input to reset TCNTV

Trigger input

TRGV

Input

Trigger input to initiate counting

Register Configuration
Table 9.9 shows the register configuration of timer V.
Table 9.9

Timer V Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer control register V0

TCRV0

R/W

H'00

H'FFB8

Timer control/status register V

TCSRV

R/(W)*

H'10

H'FFB9

Time constant register A

TCORA

R/W

H'FF

H'FFBA

Time constant register B

TCORB

R/W

H'FF

H'FFBB

Timer counter V

TCNTV

R/W

H'00

H'FFBC

Timer control register V1

TCRV1

R/W

H'E2

H'FFBD

Note: * Bits 7 to 5 can only be written with 0, for flag clearing.

221

9.4.2

Register Descriptions

Timer Counter V (TCNTV)

Bit

TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input.
The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and
written by the CPU at any time. TCNTV can be cleared by an external reset signal, or by compare
match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows from H'FF to H'00, OVF is set to 1 in TCSRV.
TCNTV is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Time Constant Registers A and B (TCORA, TCORB)
Bit

TCORn7 TCORn6 TCORn5 TCORn4 TCORn3 TCORn2 TCORn1 TCORn0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W
n = A or B

TCORA and TCORB are 8-bit read/write registers.

TCORA and TCNTV are compared at all times, except during the T3 state of a TCORA write
cycle. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is
also set to 1 in TCRV0, a CPU interrupt is requested.
Timer output from the TMOV pin can be controlled by a signal resulting from compare match,
according to the settings of bits OS3 to OS0 in TCSRV.
TCORA is initialized to H'FF upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
TCORB is similar to TCORA.

222

Timer Control Register V0 (TCRV0)

Bit

CMIEB

CMIEA

OVIE

CCLR1

CCLR0

CKS2

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of
TCNTV, and enables interrupts.
TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Compare Match Interrupt Enable B (CMIEB): Bit 7 enables or disables the interrupt
request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV.
Bit 7: CMIEB

Description

Interrupt request (CMIB) from CMFB disabled

Interrupt request (CMIB) from CMFB enabled

(initial value)

Bit 6Compare Match Interrupt Enable A (CMIEA): Bit 6 enables or disables the interrupt
request (CMIA) generated from CMFA when CMFA is set to 1 in TCSRV.
Bit 6: CMIEA

Description

Interrupt request (CMIA) from CMFA disabled

Interrupt request (CMIA) from CMFA enabled

(initial value)

Bit 5Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables the interrupt
request (OVI) generated from OVF when OVF is set to 1 in TCSRV.
Bit 5: OVIE

Description

Interrupt request (OVI) from OVF disabled

Interrupt request (OVI) from OVF enabled

(initial value)

223

Bits 4 and 3Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to
clear TCNTV, and select compare match A or B or an external reset input.
When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also
halted. Counting resumes when a trigger edge is input at the TRGV pin.
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
Bit 4: CCLR1

Bit 3: CCLR0

Description

Clearing is disabled

Cleared by compare match A

Cleared by compare match B

Cleared by rising edge of external reset input

(initial value)

Bits 2 to 0Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 and bit ICKS0 in TCRV1 select
the clock input to TCNTV.
Six internal clock sources divided from the system clock () can be selected. The counter
increments on the falling edge.
If the external clock is selected, there is a further selection of incrementing on the rising edge,
falling edge, or both edges.
If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.
TCRV0

TCRV1

Bit 2:
CKS2

Bit 1:
CKS1

Bit 0:
CKS0

Bit 0:
ICKS0

Description

Clock input disabled

Internal clock: /4, falling edge

Internal clock: /8, falling edge

Internal clock: /16, falling edge

Internal clock: /32, falling edge

Internal clock: /64, falling edge

Internal clock: /128, falling edge

Clock input disabled

External clock: rising edge

External clock: falling edge

External clock: rising and falling edges

224

(initial value)

Timer Control/Status Register V (TCSRV)

Bit

CMFB

CMFA

OVF

OS3

OS2

OS1

OS0

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/W

R/W

R/W

R/W

Note: * Bits 7 to 5 can be only written with 0, for flag clearing.

TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls
compare match output.
TCSRV is initialized to H'10 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Compare Match Flag B (CMFB): Bit 7 is a status flag indicating that TCNTV has
matched TCORB. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7: CMFB

Description

Clearing conditions:
After reading CMFB = 1, cleared by writing 0 to CMFB

(initial value)

Setting conditions:
Set when the TCNTV value matches the TCORB value

Bit 6Compare Match Flag A (CMFA): Bit 6 is a status flag indicating that TCNTV has
matched TCORA. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 6: CMFA

Description

Clearing conditions:
After reading CMFA = 1, cleared by writing 0 to CMFA

(initial value)

Setting conditions:
Set when the TCNTV value matches the TCORA value

225

Bit 5Timer Overflow Flag (OVF): Bit 5 is a status flag indicating that TCNTV has overflowed
from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 5: OVF

Description

Clearing conditions:
After reading OVF = 1, cleared by writing 0 to OVF

(initial value)

Setting conditions:
Set when TCNTV overflows from H'FF to H'00

Bit 4Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0Output Select 3 to 0 (OS3 to OS0): Bits 3 to 0 select the way in which the output
level at the TMOV pin changes in response to compare match between TCNTV and TCORA or
TCORB.
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two levels can be controlled independently.
If two compare matches occur simultaneously, any conflict between the settings is resolved
according to the following priority order: toggle output > 1 output > 0 output.
When OS3 to OS0 are all cleared to 0, timer output is disabled.
After a reset, the timer output is 0 until the first compare match.
Bit 3: OS3

Bit 2: OS2

Description

No change at compare match B

0 output at compare match B

1 output at compare match B

Output toggles at compare match B

Bit 1: OS1

Bit 0: OS0

Description

No change at compare match A

0 output at compare match A

1 output at compare match A

Output toggles at compare match A

226

(initial value)

(initial value)

Timer Control Register V1 (TCRV1)

Bit

TVEG1

TVEG0

TRGE

ICKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV
input, and selects the clock input to TCNTV.
TCRV1 is initialized to H'E2 upon reset and in watch mode, subsleep mode, and subactive mode.
Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bits 4 and 3TRGV Input Edge Select (TVEG1, TVEG0): Bits 4 and 3 select the TRGV input
edge.
Bit 4: TVEG1

Bit 3: TVEG0

Description

TRGV trigger input is disabled

Rising edge is selected

Falling edge is selected

Rising and falling edges are both selected

(initial value)

Bit 2TRGV Input Enable (TRGE): Bit 2 enables TCNTV counting to be triggered by input at
the TRGV pin, and enables TCNTV counting to be halted when TCNTV is cleared by compare
match. TCNTV stops counting when TRGE is set to 1, then starts counting when the edge selected
by bits TVEG1 and TVEG0 is input at the TRGV pin.
Bit 2: TRGE

Description

TCNTV counting is not triggered by input at the TRGV pin, and does not stop
when TCNTV is cleared by compare match
(initial value)

TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV
is cleared by compare match

Bit 1Reserved Bit: Bit 1 is reserved; it is always read as 1, and cannot be modified.
Bit 0Internal Clock Select 0 (ICKS0): Bit 0 and bits CKS2 to CKS0 in TCRV0 select the
TCNTV clock source. For details see 9.4.2 Register Descriptions.

227

9.4.3

Timer Operation

Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0
to H'00, TCSRV to H'10, and TCRV1 to H'E2.
Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock,
as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. The valid edge or edges
of the external clock can also be selected by CKS2 to CKS0. When the clock source is selected,
TCNTV starts counting the selected clock input.
The TCNTV contents are always compared with TCORA and TCORB. When a match occurs, the
CMFA or CMFB bit is set to 1 in TCSRV. If CMIEA or CMIEB is set to 1 in TCRV0, a CPU
interrupt is requested. At the same time, the output level selected by bits OS3 to OS0 in TCSRV is
output from the TMOV pin.
When TCNT overflows from H'FF to H'00, if OVIE is 1 in TCRV0, a CPU interrupt is requested.
If bits CCLR1 and CCLR0 in TCRV0 are set to 01 (clear by compare match A) or 10 (clear by
compare match B), TCNTV is cleared by the corresponding compare match. If these bits are set to
11, TCNTV is cleared by input of a rising edge at the TMRIV pin.
When the counter clear event selected by bits CCLR1 and CCLR0 in TCRV0 occurs, TCNTV is
cleared and the count-up is halted. TCNTV starts counting when the signal edge selected by bits
TVEG1 and TVEG0 in TCRV1 is input at the TRGV pin.

228

TCNTV Increment Timing: TCNTV is incremented by an input (internal or external) clock.

Internal clock
One of six clocks (/128, /64, /32, /16, /8, /4) divided from the system clock () can be
selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 9.4 shows the
timing.

Internal
clock
FRC
input
TCNTV
input
TCNTV

N1

N1

Figure 9.4 Increment Timing with Internal Clock

External clock
Incrementation on the rising edge, falling edge, or both edges of the external clock can be
selected by bits CKS2 to CKS0 in TCRV0.
The external clock pulse width should be at least 1.5 system clocks () when a single edge is
counted, and at least 2.5 system clocks when both edges are counted. Shorter pulses will not be
counted correctly.
Figure 9.5 shows the timing when both the rising and falling edges of the external clock are
selected.

229

TMCIV
(external clock
input pin)
TCNTV
input clock

N1

TCNTV

N1

Figure 9.5 Increment Timing with External Clock

Overflow flag Set Timing: The overflow flag (OVF) is set to 1 when TCNTV overflows from
H'FF to H'00. Figure 9.6 shows the timing.

TCNTV

H'FF

H'00

Overflow
signal

Figure 9.6 OVF Set Timing

230

Compare Match Flag set Timing: Compare match flag A or B (CMFA or CMFB) is set to 1
when TCNTV matches TCORA or TCORB. The internal compare-match signal is generated in the
last state in which the values match (when TCNTV changes from the matching value to a new
value). Accordingly, when TCNTV matches TCORA or TCORB, the compare match signal is not
generated until the next clock input to TCNTV. Figure 9.7 shows the timing.

TCNTV

TCORA or
TCORB

N+1

Compare
match signal

CMFA or
CMFB

Figure 9.7 CMFA and CMFB Set Timing

TMOV Output Timing: The TMOV output responds to compare match A or B by remaining
unchanged, changing to 0, changing to 1, or toggling, as selected by bits OS3 to OS0 in TCSRV.
Figure 9.8 shows the timing when the output is toggled by compare match A.

Compare
match A
signal
Timer V
output pin

Figure 9.8 TMOV Output Timing

231

TCNTV Clear Timing by Compare Match: TCNTV can be cleared by compare match A or B,
as selected by bits CCLR1 and CCLR0 in TCRV0. Figure 9.9 shows the timing.

Compare
match A signal

TCNTV

H'00

Figure 9.9 Clear Timing by Compare Match

TCNTV Clear Timing by TMRIV: TCNTV can be cleared by a rising edge at the TMRIV pin,
as selected by bits CCLR1 and CCLR0 in TCRV0. A TMRIV input pulse width of at least 1.5
system clocks is necessary. Figure 9.10 shows the timing.

Compare
match A signal

Timer V
output pin

TCNTV

N1

H'00

Figure 9.10 Clear Timing by TMRIV Input

232

9.4.4

Timer V Operation Modes

Table 9.10 summarizes the timer V operation states.

Table 9.10 Timer V Operation States
Operation Mode

Reset

Active

Sleep

Watch

Subactive

Subsleep

Standby

TCNTV

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TCRV0, TCRV1

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TCORA, TCORB

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TCSRV

Reset

Functions

Functions

Reset

Reset

Reset

Reset

9.4.5

Interrupt Sources

Timer V has three interrupt sources: CMIA, CMIB, and OVI. Table 9.11 lists the interrupt sources
and their vector address. Each interrupt source can be enabled or disabled by an interrupt enable
bit in TCRV0. Although all three interrupts share the same vector, they have individual interrupt
flags, so software can discriminate the interrupt source.
Table 9.11 Timer V Interrupt Sources
Interrupt

Description

Vector Address

CMIA

Generated from CMFA

H'0022

CMIB

Generated from CMFB

OVI

Generated from OVF

233

9.4.6

Application Examples

Pulse Output with Arbitrary Duty Cycle: Figure 9.11 shows an example of output of pulses
with an arbitrary duty cycle. To set up this output:
Clear bit CCLR1 to 0 and set bit CCLR0 to 1 in TCRV0 so that TCNTV will be cleared by
compare match with TCORA.
Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with
TCORA and to 0 at compare match with TCORB.
Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
TCNTV
H'FF

Counter cleared

TCORA
TCORB
H'00

TMOV

Figure 9.11 Pulse Output Example

234

Single-Shot Output with Arbitrary Pulse Width and Delay from TRGV Input: The trigger
function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the
TRGV input, as shown in figure 9.12. To set up this output:
Set bit CCLR1 to 1 and clear bit CCLR0 to 0 in TCRV0 so that TCNTV will be cleared by
compare match with TCORB.
Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with
TCORA and to 0 at compare match with TCORB.
Set bits TVEG1 and TVEG0 to 10 in TCRV1 and set TRGE to 1 to select the falling edge of
the TRGV input.
Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
After these settings, a pulse waveform will be output without further software intervention, with a
delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB
TCORA).

H'FF

TCNTV
Counter cleared

TCORB
TCORA
H'00
TRGV

TMOV
Compare match A
Compare match B
clears TCNTV and
halts count-up

Compare match A
Compare match B
clears TCNTV and
halts count-up

Figure 9.12 Pulse Output Synchronized to TRGV Input

235

9.4.7

Application Notes

The following types of contention can occur in timer V operation.

Contention between TCNTV Write and Counter Clear: If a TCNTV clear signal is generated
in the T3 state of a TCNTV write cycle, clearing takes precedence and the write to the counter is
not carried out. Figure 9.13 shows the timing.
TCNTV write cycle by CPU
T1

T2

T3

Address

TCNTV address

Internal write
signal

Counter clear
signal

TCNTV

H'00

Figure 9.13 Contention between TCNTV Write and Clear

236

Contention between TCNTV Write and Increment: If a TCNTV increment clock signal is
generated in the T3 state of a TCNTV write cycle, the write takes precedence and the counter is not
incremented. Figure 9.14 shows the timing.
TCNTV write cycle by CPU
T1

T2

T3

Address

TCNTV address

Internal write
signal

TCNTV clock

TCNTV

M
TCNTV write data

Figure 9.14 Contention between TCNTV Write and Increment

237

Contention between TCOR Write and Compare Match: If a compare match is generated in the
T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence
and the compare match signal is inhibited. Figure 9.15 shows the timing.
TCORA write cycle by CPU
T1

T2

T3

Address

TCORA address

Internal write
signal

TCNTV

N+1

TCORA

M
TCORA write data

Compare match
signal
Inhibited

Figure 9.15 Contention between TCORA Write and Compare Match

238

Contention between Compare Match A and B: If compare match A and B occur

simultaneously, any conflict between the output selections for compare match A and compare
match B is resolved by following the priority order in table 9.12.
Table 9.12 Timer Output Priority Order
Output Setting

Priority

Toggle output

High

1 output
0 output
No change

Low

Internal Clock Switching and Counter Operation: Depending on the timing, TCNTV may be
incremented by a switch between different internal clock sources. Table 9.13 shows the relation
between internal clock switchover timing (by writing to bits CKS1 and CKS0) and TCNTV
operation.
When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an
internal clock signal, which is divided from the system clock (). For this reason, in a case like No.
3 in table 9.13 where the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment.
TCNTV can also be incremented by a switch between internal and external clocks.

239

Table 9.13 Internal Clock Switching and TCNTV Operation

No.
1

Clock Levels Before

and After Modifying
Bits CKS1 and CKS0

TCNTV Operation

Goes from low level

to low level*1

Clock before
switching
Clock after
switching
Count clock

TCNTV

N+1

N
Write to CKS1 and CKS0

Goes from low

to high*2

Clock before
switching
Clock after
switching
Count clock

TCNTV

N+1

N+2

Write to CKS1 and CKS0

Notes: 1. Including a transition from the low level to the stopped state, or from the stopped state
to the low level.
2. Including a transition from the stopped state to the high level.

240

Table 9.13 Internal Clock Switching and TCNTV Operation (cont)

No.
3

Clock Levels Before

and After Modifying
Bits CKS1 and CKS0

TCNTV Operation

Goes from high level

to low level*1

Clock before
switching

Clock after
switching
*2
Count clock

TCNTV

N+1

N+2

Write to CKS1 and CKS0

Goes from high

to high

Clock before
switching

Clock after
switching
Count clock

TCNTV

N +1

N +2
Write to CKS1 and CKS0

Notes: 1. Including a transition from the high level to the stopped state.
2. The switchover is seen as a falling edge, and TCNTV is incremented.

241

9.5

Timer X

9.5.1

Overview

Timer X is based on a 16-bit free-running counter (FRC). It can output two independent
waveforms, or measure input pulse widths and external clock periods.
Features
Features of timer X are given below.
Choice of three internal clock sources (/2, /8, /32) or an external clock (can be used as an
external event counter).
Two independent output compare waveforms.
Four independent input capture channels, with selection of rising or falling edge and buffering
option.
Counter can be cleared by compare match A.
Seven independent interrupt sources: two compare match, four input capture, one overflow

242

Block Diagram
Figure 9.16 shows a block diagram of timer X.

ICRA
FTIA
FTIB
FTIC
FTID

Input
capture
control

ICRC
ICRB
ICRD
TCRX

Comparator
FRC
FTCI
Comparator

Internal data bus

OCRB

OCRA

PSS

FTOA
FTOB

TOCR

TCSRX
TIER
Legend:
TIER:
TCSRX:
FRC:
OCRA:
OCRB:
TCRX:
TOCR:
ICRA:
ICRB:
ICRC:
ICRD:
PSS:

Interrupt
request
Timer interrupt enable register
Timer control/status register X
Free-running counter
Output compare register A
Output compare register B
Timer control register X
Timer output compare control register
Input capture register A
Input capture register B
Input capture register C
Input capture register D
Prescaler S

Figure 9.16 Block Diagram of Timer X

243

Pin Configuration
Table 9.14 shows the timer X pin configuration.
Table 9.14

Pin Configuration

Name

Abbrev.

I/O

Function

Counter clock input

FTCI

Input

Clock input to FRC

Output compare A

FTOA

Output

Output pin for output compare A

Output compare B

FTOB

Output

Output pin for output compare B

Input capture A

FTIA

Input

Input pin for input capture A

Input capture B

FTIB

Input

Input pin for input capture B

Input capture C

FTIC

Input

Input pin for input capture C

Input capture D

FTID

Input

Input pin for input capture D

244

Register Configuration
Table 9.15 shows the register configuration of timer X.
Table 9.15 Timer X Registers
Name

Abbrev.

R/W

Timer interrupt enable register

TIER

R/W
1

Initial Value

Address

H'01

H'F770

H'00

H'F771

Timer control/status register X

TCSRX

R/(W)*

Free-running counter H

FRCH

R/W

H'00

H'F772

Free-running counter L

FRCL

R/W

H'00

H'F773

Output compare register AH

OCRAH

R/W

H'FF

H'F774*2

Output compare register AL

OCRAL

R/W

H'FF

H'F775*2

Output compare register BH

OCRBH

R/W

H'FF

H'F774*2

Output compare register BL

OCRBL

R/W

H'FF

H'F775*2

Timer control register X

TCRX

R/W

H'00

H'F776

Timer output compare control

register

TOCR

R/W

H'E0

H'F777

Input capture register AH

ICRAH

H'00

H'F778

Input capture register AL

ICRAL

H'00

H'F779

Input capture register BH

ICRBH

H'00

H'F77A

Input capture register BL

ICRBL

H'00

H'F77B

Input capture register CH

ICRCH

H'00

H'F77C

Input capture register CL

ICRCL

H'00

H'F77D

Input capture register DH

ICRDH

H'00

H'F77E

Input capture register DL

ICRDL

H'00

H'F77F

Notes: 1. Bits 7 to 1 can only be written with 0 for flag clearing. Bit 0 is a read/write bit.
2. OCRA and OCRB share the same address. They are selected by the OCRS bit in
TOCR.

245

9.5.2

Register Descriptions

Free-Running Counter (FRC)

Free-Running Counter H (FRCH)
Free-Running Counter L (FRCL)
FRC
Bit

15

14

13

12

11

10

Initial value

Read/Write

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

FRCH

FRCL

FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input.
The clock source is selected by bits CKS1 and CKS0 in TCRX.
FRC can be cleared by compare match A, depending on the setting of CCLRA in TCSRX.
When FRC overflows from H'FFFF to H'0000, OVF is set to 1 in TCSRX. If OVIE = 1 in TIER, a
CPU interrupt is requested.
FRC can be written and read by the CPU. Since FRC has 16 bits, data is transferred between the
CPU and FRC via a temporary register (TEMP). For details see 9.5.3, CPU Interface.
FRC is initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Output Compare Registers A and B (OCRA, OCRB)
Output Compare Registers AH and BH (OCRAH, OCRBH)
Output Compare Registers AL and BL (OCRAL, OCRBL)
OCRA, OCRB
Bit

15

14

13

12

11

10

Initial value

Read/Write

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

OCRAH, OCRBH

OCRAL, OCRBL

There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of
which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in
246

TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested.

When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value
selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the
output from the FTOA or FTOB pin is 0 until the first compare match occurs.
OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is
transferred between them and the CPU via a temporary register (TEMP). For details see 9.5.3,
CPU Interface.
OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode,
subsleep mode, and subactive mode.
Input Capture Registers A to D (ICRA to ICRD)
Input Capture Registers AH to DH (ICRAH to ICRDH)
Input Capture Registers AL to DL (ICRAL to ICRDL)
ICRA, ICRB, ICRC, ICRD
Bit

15

14

13

12

11

10

Initial value

Read/Write

ICRAH, ICRBH, ICRCH, ICRDH

ICRAL, ICRBL, ICRCL, ICRDL

There are four 16-bit read only input capture registers, ICRA to ICRD.
When the falling edge of an input capture signal is input, the FRC value is transferred to the
corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is
set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in
TCRX, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits
IEDGA to IEDGD in TCRX.
ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by
bits BUFEA and BUFEB in TCRX.
Figure 9.17 shows the interconnections when ICRC operates as a buffer register of ICRA (when
BUFEA = 1). When ICRC is used as the ICRA buffer, both the rising and falling edges of the
external input signal can be selected simultaneously, by setting IEDGA IEDGC. If IEDGA =
IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9.16.
Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of
the input capture flag (ICF).
247

IEOGA BUFEA IEDGC

Edge detector
and internal
capture signal
generator

FTIA

ICRC

ICRA

FRC

Figure 9.17 Buffer Operation (Example)

Table 9.16 Input Edge Selection during Buffer Operation
IEDGA

IEDGC

Input Edge Selection

Falling edge of input capture A input signal is captured

Rising and falling edge of input capture A input signal are both captured

(initial value)

0
1

Rising edge of input capture A input signal is captured

ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is
transferred from them to the CPU via a temporary register (TEMP). For details see 9.5.3, CPU
Interface.
To assure input capture, the pulse width of the input capture input signal must be at least 1.5
system clocks () when a single edge is selected, or at least 2.5 system clocks () when both edges
are selected.
ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep
mode, and subactive mode.

248

Timer Interrupt Enable Register (TIER)

Bit

ICIAE

ICIBE

ICICE

ICIDE

OCIAE

OCIBE

OVIE

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TIER is an 8-bit read/write register that enables or disables interrupt requests.

TIER is initialized to H'01 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Input Capture Interrupt A Enable (ICIAE): Bit 7 enables or disables the ICIA interrupt
requested when ICFA is set to 1 in TCSRX.
Bit 7: ICIAE

Description

Interrupt request by ICFA (ICIA) is disabled

Interrupt request by ICFA (ICIA) is enabled

(initial value)

Bit 6Input Capture Interrupt B Enable (ICIBE): Bit 6 enables or disables the ICIB interrupt
requested when ICFB is set to 1 in TCSRX.
Bit 6: ICIBE

Description

Interrupt request by ICFB (ICIB) is disabled

Interrupt request by ICFB (ICIB) is enabled

(initial value)

Bit 5Input Capture Interrupt C Enable (ICICE): Bit 5 enables or disables the ICIC interrupt
requested when ICFC is set to 1 in TCSRX.
Bit 5: ICICE

Description

Interrupt request by ICFC (ICIC) is disabled

Interrupt request by ICFC (ICIC) is enabled

(initial value)

249

Bit 4Input Capture Interrupt D Enable (ICIDE): Bit 4 enables or disables the ICID interrupt
requested when ICFD is set to 1 in TCSRX.
Bit 4: ICIDE

Description

Interrupt request by ICFD (ICID) is disabled

Interrupt request by ICFD (ICID) is enabled

(initial value)

Bit 3Output Compare Interrupt A Enable (OCIAE): Bit 3 enables or disables the OCIA
interrupt requested when OCFA is set to 1 in TCSRX.
Bit 3: OCIAE

Description

Interrupt request by OCFA (OCIA) is disabled

Interrupt request by OCFA (OCIA) is enabled

(initial value)

Bit 2Output Compare Interrupt B Enable (OCIBE): Bit 2 enables or disables the OCIB
interrupt requested when OCFB is set to 1 in TCSRX.
Bit 2: OCIBE

Description

Interrupt request by OCFB (OCIB) is disabled

Interrupt request by OCFB (OCIB) is enabled

(initial value)

Bit 1Timer Overflow Interrupt Enable (OVIE): Bit 1 enables or disables the FOVI interrupt
requested when OVF is set to 1 in TCSRX.
Bit 1: OVIE

Description

Interrupt request by OVF (FOVI) is disabled

Interrupt request by OVF (FOVI) is enabled

(initial value)

Bit 0Reserved Bit: Bit 0 is reserved; it is always read as 1, and cannot be modified.
Timer Control/Status Register X (TCSRX)
Bit

ICFA

ICFB

ICFC

ICFD

OCFA

OCFB

OVF

CCLRA

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/W

Note: * Bits 7 to 1 can only be written with 0 for flag clearing.

TCSRX is an 8-bit register that selects clearing of the counter and controls interrupt request
signals.
250

TCSRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode. Other timing is described in section 9.6.3, Timer Operation.
Bit 7Input Capture Flag A (ICFA): Bit 7 is a status flag that indicates that the FRC value has
been transferred to ICRA by an input capture signal. If BUFEA is set to 1 in TCRX, ICFA
indicates that the FRC value has been transferred to ICRA by an input capture signal and that the
ICRA value before this update has been transferred to ICRC.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 7: ICFA

Description

Clearing conditions:
After reading ICFA = 1, cleared by writing 0 to ICFA

(initial value)

Setting conditions:
Set when the FRC value is transferred to ICRA by an input capture signal

Bit 6Input Capture Flag B (ICFB): Bit 6 is a status flag that indicates that the FRC value has
been transferred to ICRB by an input capture signal. If BUFEB is set to 1 in TCRX, ICFB
indicates that the FRC value has been transferred to ICRB by an input capture signal and that the
ICRB value before this update has been transferred to ICRC.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 6: ICFB

Description

Clearing conditions:
After reading ICFB = 1, cleared by writing 0 to ICFB

(initial value)

Setting conditions:
Set when the FRC value is transferred to ICRB by an input capture signal

Bit 5Input Capture Flag C (ICFC): Bit 5 is a status flag that indicates that the FRC value has
been transferred to ICRC by an input capture signal. If BUFEA is set to 1 in TCRX, ICFC is set
by the input capture signal even though the FRC value is not transferred to ICRC. In buffered
operation, ICFC can accordingly be used as an external interrupt, by setting the ICICE bit to 1.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 5: ICFC

Description

Clearing conditions:
After reading ICFC = 1, cleared by writing 0 to ICFC

(initial value)

Setting conditions:
Set by input capture signal

251

Bit 4Input Capture Flag D (ICFD): Bit 4 is a status flag that indicates that the FRC value has
been transferred to ICRD by an input capture signal. If BUFEB is set to 1 in TCRX, ICFD is set
by the input capture signal even though the FRC value is not transferred to ICRD. In buffered
operation, ICFD can accordingly be used as an external interrupt, by setting the ICIDE bit to 1.
This flag is set by hardware and cleared by software. It cannot be set by software.
Bit 4: ICFD

Description

Clearing conditions:
After reading ICFD = 1, cleared by writing 0 to ICFD

(initial value)

Setting conditions:
Set by input capture signal

Bit 3Output Compare Flag A (OCFA): Bit 3 is a status flag that indicates that the FRC value
has matched OCRA. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 3: OCFA

Description

Clearing conditions:
After reading OCFA = 1, cleared by writing 0 to OCFA

(initial value)

Setting conditions:
Set when FRC matches OCRA

Bit 2Output Compare Flag B (OCFB): Bit 2 is a status flag that indicates that the FRC value
has matched OCRB. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 2: OCFB

Description

Clearing conditions:
After reading OCFB = 1, cleared by writing 0 to OCFB

(initial value)

Setting conditions:
Set when FRC matches OCRB

Bit 1Timer Overflow Flag (OVF): Bit 1 is a status flag that indicates that FRC has overflowed
from H'FFFF to H'0000. This flag is set by hardware and cleared by software. It cannot be set by
software.

252

Bit 1: OVF

Description

Clearing conditions:
After reading OVF = 1, cleared by writing 0 to OVF

(initial value)

Setting conditions:
Set when the FRC value overflows from H'FFFF to H'0000

Bit 0Counter Clear A (CCLRA): Bit 0 selects whether or not to clear FRC by compare match
A (when FRC matches OCRA).
Bit 0: CCLRA

Description

FRC is not cleared by compare match A

FRC is cleared by compare match A

(initial value)

Timer Control Register X (TCRX)

Bit

IEDGA

IEDGB

IEDGC

IEDGD

BUFEA

BUFEB

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals,
enables buffering, and selects the FRC clock source.
TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7Input Edge Select A (IEDGA): Bit 7 selects the rising or falling edge of the input capture
A input signal (FTIA).
Bit 7: IEDGA

Description

Falling edge of input capture A is captured

Rising edge of input capture A is captured

(initial value)

Bit 6Input Edge Select B (IEDGB): Bit 6 selects the rising or falling edge of the input capture
B input signal (FTIB).
Bit 6: IEDGB

Description

Falling edge of input capture B is captured

Rising edge of input capture B is captured

(initial value)

253

Bit 5Input Edge Select C (IEDGC): Bit 5 selects the rising or falling edge of the input capture
C input signal (FTIC).
Bit 5: IEDGC

Description

Falling edge of input capture C is captured

Rising edge of input capture C is captured

(initial value)

Bit 4 Input Edge Select D (IEDGD): Bit 4 selects the rising or falling edge of the input capture
D input signal (FTID).
Bit 4: IEDGD

Description

Falling edge of input capture D is captured

Rising edge of input capture D is captured

(initial value)

Bit 3Buffer Enable A (BUFEA): Bit 3 selects whether or not to use ICRC as a buffer register
for ICRA.
Bit 3: BUFEA

Description

ICRC is not used as a buffer register for ICRA

ICRC is used as a buffer register for ICRA

(initial value)

Bit 2Buffer Enable B (BUFEB): Bit 2 selects whether or not to use ICRD as a buffer register
for ICRB.
Bit 2: BUFEB

Description

ICRD is not used as a buffer register for ICRB

ICRD is used as a buffer register for ICRB

(initial value)

Bits 1 and 0Clock Select (CKS1, CKS0): Bits 1 and 0 select one of three internal clock
sources or an external clock for input to FRC. The external clock is counted on the rising edge.
Bit 1: CKS1

Bit 0: CKS0

Description

Internal clock: /2

Internal clock: /8

Internal clock: /32

External clock: rising edge

254

(initial value)

Timer Output Compare Control Register (TOCR)

Bit

OCRS

OEA

OEB

OLVLA

OLVLB

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

TOCR is an 8-bit read/write register that selects the output compare output levels, enables output
compare output, and controls access to OCRA and OCRB.
TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bits 7 to 5Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
OCRS selects which register is accessed when this address is written or read. It does not affect the
operation of OCRA and OCRB.
Bit 4: OCRS

Description

OCRA is selected

OCRB is selected

(initial value)

Bit 3Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output
compare A.
Bit 3: OEA

Description

Output compare A output is disabled

Output compare A output is enabled

(initial value)

Bit 2Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output
compare B.
Bit 2: OEB

Description

Output compare B output is disabled

Output compare B output is enabled

(initial value)

255

Bit 1Output Level A (OLVLA): Bit 1 selects the output level that is output at pin FTOA by
compare match A (when FRC matches OCRA).
Bit 1: OLVLA

Description

Low level

High level

(initial value)

Bit 0Output Level B (OLVLB): Bit 0 selects the output level that is output at pin FTOB by
compare match B (when FRC matches OCRB).
Bit 0: OLVLB

Description

Low level

High level

9.5.3

(initial value)

CPU Interface

FRC, OCRA, OCRB, and ICRA to ICRD are 16-bit registers, but the CPU is connected to the onchip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore
uses an 8-bit temporary register (TEMP).
These registers should always be accessed 16 bits at a time. If two consecutive byte-size MOV
instructions are used, the upper byte must be accessed first and the lower byte second. Data will
not be transferred correctly if only the upper byte or only the lower byte is accessed.

256

Write Access: Write access to the upper byte results in transfer of the upper-byte write data to
TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper
register byte, and direct transfer of the lower-byte write data to the lower register byte.
Figure 9.18 shows an example of the writing of H'AA55 to FRC.
Write to upper byte

CPU
(H'AA)

Module data bus

Bus
interface

TEMP
(H'AA)

FRCH
(
)

FRCL
(
)

Write to lower byte

CPU
(H'55)

Module data bus

Bus
interface

TEMP
(H'AA)

FRCH
(H'AA)

FRCL
(H'55)

Figure 9.18 Write Access to FRC (CPU FRC)

257

Read Access: In access to FRC and ICRA to ICRD, when the upper byte is read the upper-byte
data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when
the lower byte is read, the lower-byte data in TEMP is transferred to the CPU.
In access to OCRA or OCRB, when the upper byte is read the upper-byte data is transferred
directly to the CPU, and when the lower byte is read the lower-byte data is transferred directly to
the CPU.
Figure 9.19 shows an example of the reading of FRC when FRC contains H'AAFF.
Read upper byte

CPU
(H'AA)

Module data bus

Bus
interface

TEMP
(H'FF)

FRCH
(H'AA)

FRCL
(H'FF)

Read lower byte

CPU
(H'FF)

Module data bus

Bus
interface

TEMP
(H'FF)

FRCH
( AB )

FRCL
( 00 )

Note: * H'AB00 if counter has been updated once.

Figure 9.19 Read Access to FRC (FRC CPU)

258

9.5.4

Timer Operation

Timer X Operation
Output compare operation
Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in
TCRX can select one of three internal clock sources or an external clock for input to FRC. The
FRC contents are compared constantly with OCRA and OCRB. When a match occurs, the
output at pin FTOA or FTOB goes to the level selected by OLVLA or OLVLB in TOCR.
Following a reset, the output at both FTOA and FTOB is 0 until the first compare match. If
CCLRA is set to 1 in TCSRX, compare match A clears FRC to H'0000.
Input capture operation
Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in
TCRX can select one of three internal clock sources or an external clock for input to FRC.
When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA to FTID,
the FRC value is transferred to ICRA to ICRD, and ICFA to ICFD are set to 1 in TCSRX. If
bits ICIAE to ICIDE are set to 1 in TIER, a CPU interrupt is requested.
If bits BUFEA and BUFEB are set to 1 in TCRX, ICRC and ICRD operate as buffer registers
for ICRA or ICRB. When the edges selected by bits IEDGA to IEDGD in TCRX are input at
pins FTIA and FTIB, the FRC value is transferred to ICRA or ICRB, and the previous value in
ICRA or ICRB is transferred to ICRC or ICRD. Simultaneously, ICFA or ICFB is set to 1. If
bit ICIAE or ICIBE is set to 1 in TIER, a CPU interrupt is requested.

259

FRC Count Timing: FRC is incremented by clock input. Bits CKS1 and CKS0 in TCRX can
select one of three internal clock sources (/2, /8, /32) or an external clock.
Internal clock
Bits CKS1 and CKS0 in TCRX select one of three internal clock sources (/2, /8, /32)
created by dividing the system clock (). Figure 9.20 shows the increment timing.

Internal
clock

FRC input
clock

FRC

N1

N+1

Figure 9.20 Increment Timing with Internal Clock

External clock
External clock input is selected when bits CKS1 and CKS0 are both set to 1 in TCRX. FRC
increments on the rising edge of the external clock. An external pulse width of at least 1.5
system clocks () is necessary. Shorter pulses will not be counted correctly. Figure 9.21 shows
the timing.

FTCI
(external clock
input pin)
FRC input
clock

FRC

Figure 9.21 Increment Timing with External Clock

260

N1

Output Compare Timing: When a compare match occurs, the output level selected by the OLVL
bit in TOCR is output at pin FTOA or FTOB. Figure 9.22 shows the output timing for output
compare A.

FRC

OCRA

N+1

N+1

Compare
match A
signal
Clear*
OLVLA

FTOA
(output compare
A output pin)
Note: * By execution of a software instruction.

Figure 9.22 Output Compare A Output Timing

FRC Clear Timing: FRC can be cleared by compare match A. Figure 9.23 shows the timing.

Compare
match A signal

FRC

H'0000

Figure 9.23 Clear Timing by Compare Match A

261

Input Capture Timing

Input capture timing
The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX.
Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1).

Input capture
pin
Input capture
signal

Figure 9.24 Input Capture Signal Timing (Normal Case)

If the input at the input capture pin occurs while the upper byte of the corresponding input
capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by
one system clock (). Figure 9.25 shows the timing.
ICRA to ICRD upper byte read cycle
T1

T2

T3

Input capture
pin

Input capture
signal

Figure 9.25 Input Capture Signal Timing (during ICRA to ICRD Read)

262

 Buffered input capture timing

Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB.
Figure 9.26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both
the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and
IEDGC = 1).

FTIA

Input capture
signal

FRC

n+1

N+1

ICRA

ICRC

Figure 9.26 Buffered Input Capture Timing (Normal Case)

When ICRC or ICRD is used as a buffer register, the input capture flag is still set by the
selected edge of the input capture input signal. For example, if ICRC is used to buffer ICRA,
when the edge transition selected by the IEDGC bit occurs at the input capture pin, ICFC will
be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however.
In buffered operation, if the upper byte of one of the two registers that receives a data transfer
(ICRA and ICRC, or ICRB and ICRD) is being read when an input capture signal would
normally occur, the input capture signal will be delayed by one system clock (). Figure 9.27
shows the case when BUFEA = 1.

263

ICRA or ICRC upper byte read cycle by CPU

T1

T2

T3

FTIA

Input capture
signal

Figure 9.27 Buffered Input Capture Signal Timing (during ICRA or ICRD Read)
Input Capture Flag (ICFA to ICFD) Set Timing: Figure 9.28 shows the timing when an input
capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input
capture register (ICRA to ICRD).

Input capture
signal

ICFA to ICFD

FRC

ICRA to ICRD

Figure 9.28 ICFA to ICFD Set Timing

264

Output Compare Flag (OCFA or OCFB) Set Timing: OCFA and OCFB are set to 1 by internal
compare match signals that are output when FRC matches OCRA or OCRB. The compare match
signal is generated in the last state during which the values match (when FRC is updated from the
matching value to a new value). When FRC matches OCRA or OCRB, the compare match signal
is not generated until the next counter clock. Figure 9.29 shows the OCFA and OCFB set timing.

FRC

N+1

OCRA, OCRB

Compare match
signal

OCFA, OCFB

Figure 9.29 OCFA and OCFB Set Timing

Overflow Flag (OVF) Set Timing: OVF is set to 1 when FRC overflows from H'FFFF to H'0000.
Figure 9.30 shows the timing.

FRC

H'FFFF

H'0000

Overflow signal

OVF

Figure 9.30 OVF Set Timing

265

9.5.5

Timer X Operation Modes

Figure 9.17 shows the timer X operation modes.

Table 9.17 Timer X Operation Modes
Operation Mode

Reset

Active

Sleep

Watch

Subactive

Subsleep

Standby

FRC

Reset

Functions

Functions

Reset

Reset

Reset

Reset

OCRA, OCRB

Reset

Functions

Functions

Reset

Reset

Reset

Reset

ICRA to ICRD

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TIER

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TCRX

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TOCR

Reset

Functions

Functions

Reset

Reset

Reset

Reset

TCSRX

Reset

Functions

Functions

Reset

Reset

Reset

Reset

9.5.6

Interrupt Sources

Timer X has three types of interrupts and seven interrupt sources: ICIA to ICID, OCIA, OCIB,
and FOVI. Table 9.18 lists the sources of interrupt requests. Each interrupt source can be enabled
or disabled by an interrupt enable bit in TIER. Although all seven interrupts share the same vector,
they have individual interrupt flags, so software can discriminate the interrupt source.
Table 9.18 Timer X Interrupt Sources
Interrupt

Description

Vector Address

ICIA

Interrupt requested by ICFA

H'0020

ICIB

Interrupt requested by ICFB

ICIC

Interrupt requested by ICFC

ICID

Interrupt requested by ICFD

OCIA

Interrupt requested by OCFA

OCIB

Interrupt requested by OCFB

FOVI

Interrupt requested by OVF

266

9.5.7

Timer X Application Example

Figure 9.31 shows an example of the output of pulse signals with a 50% duty cycle and arbitrary
phase offset. To set up this output:
Set bit CCLRA to 1 in TCSRX.
Have software invert the OLVLA and OLVLB bits at each corresponding compare match.
FRC
H'FFFF

Counter cleared

OCRA
OCRB
H'0000
FTOA

FTOB

Figure 9.31 Pulse Output Example

267

9.5.8

Application Notes

The following types of contention can occur in timer X operation.

1. Contention between FRC write and counter clear
If an FRC clear signal is generated in the T3 state of a write cycle to the lower byte of FRC,
clearing takes precedence and the write to the counter is not carried out. Figure 9.32 shows the
timing.
FRC lower byte write cycle
T1

T2

T3

Address

FRC address

Internal write
signal

Counter clear
signal

FRC

H'0000

Figure 9.32 Contention between FRC Write and Clear

268

2. Contention between FRC write and increment

If an FRC increment clock signal is generated in the T3 state of a write cycle to the lower byte
of FRC, the write takes precedence and the counter is not incremented. Figure 9.33 shows the
timing.
FRC lower byte write cycle
T1

T2

T3

Address

FRC address

Internal write
signal

FRC input clock

FRC

M
FRC write data

Figure 9.33 Contention between FRC Write and Increment

269

3. Contention between OCR write and compare match

If a compare match is generated in the T 3 state of a write cycle to the lower byte of OCRA or
OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is
inhibited. Figure 9.34 shows the timing.
OCR lower byte write cycle
T1

T2

T3

Address

OCR address

Internal write
signal

FRC

N+1

OCR

M
Write data

Compare match
signal
Inhibited

Figure 9.34 Contention between OCR Write and Compare Match

270

4. Internal clock switching and counter operation

Depending on the timing, FRC may be incremented by a switch between different internal
clock sources. Table 9.19 shows the relation between internal clock switchover timing (by
writing to bits CKS1 and CKS0) and FRC operation.
When FRC is internally clocked, an increment pulse is generated from the falling edge of an
internal clock signal, which is divided from the system clock (). For this reason, in a case like
No. 3 in table 9.19 where the switch is from a high clock signal to a low clock signal, the
switchover is seen as a falling edge, causing FRC to increment.
FRC can also be incremented by a switch between internal and external clocks.
Table 9.19 Internal Clock Switching and FRC Operation

No.
1

Clock Levels Before

and After Modifying
Bits CKS1 and CKS0

FRC Operation

Goes from low level

to low level

Clock before
switching
Clock after
switching
Count clock

FRC

N+1

N
Write to CKS1 and CKS0

Goes from low

to high

Clock before
switching
Clock after
switching
Count clock

FRC

N+1

N+2

Write to CKS1 and CKS0

271

Table 9.19 Internal Clock Switching and FRC Operation (cont)

No.
3

Clock Levels Before

and After Modifying
Bits CKS1 and CKS0

FRC Operation

Goes from high level

to low level

Clock before
switching

Clock after
switching
*
Count clock

FRC

N+1

N+2

Write to CKS1 and CKS0

Goes from high to high

Clock before
switching

Clock after
switching
Count clock

FRC

N+1

N+2
Write to CKS1 and CKS0

Note: * The switchover is seen as a falling edge, and FRC is incremented.

272

9.6

Watchdog Timer

9.6.1

Overview

The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
Features
Features of the watchdog timer are given below.
Incremented by internal clock source (/8192).
A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times 8192/ (from approximately 2 ms to 500 ms when = 4.19 MHz).
Block Diagram
Figure 9.35 shows a block diagram of the watchdog timer.

PSS

/8192

TCW

Legend:
TCSRW: Timer control/status register W
TCW:
Timer counter W
PSS:
Prescaler S

Internal data bus

TCSRW

Internal reset
signal

Figure 9.35 Block Diagram of Watchdog Timer

273

Register Configuration
Table 9.20 shows the register configuration of the watchdog timer.
Table 9.20

Watchdog Timer Registers

Name

Abbrev.

R/W

Initial Value

Address

Timer control/status register W

TCSRW

R/W

H'AA

H'FFBE

Timer counter W

TCW

R/W

H'00

H'FFBF

9.6.2

Register Descriptions

Timer Control/Status Register W (TCSRW)

Bit

B6WI

TCWE

B4WI

TCSRWE

B2WI

WDON

B0WI

WRST

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/(W)*

Note: * Write is permitted only under certain conditions, which are given in the descriptions of the
individual bits.

TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7Bit 6 Write Inhibit (B6WI): Bit 7 controls the writing of data to bit 6 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 7: B6WI

Description

Bit 6 is write-enabled

Bit 6 is write-protected

(initial value)

Bit 6Timer Counter W Write Enable (TCWE): Bit 6 controls the writing of data to bit 8 to
TCW.
Bit 6: TCWE

Description

Data cannot be written to TCW

Data can be written to TCW

274

(initial value)

Bit 5Bit 4 Write Inhibit (B4WI): Bit 5 controls the writing of data to bit 4 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 5: B4WI

Description

Bit 4 is write-enabled

Bit 4 is write-protected

(initial value)

Bit 4Timer Control/Status Register W Write Enable (TCSRWE): Bit 4 controls the writing
of data to TCSRW bits 2 and 0.
Bit 4: TCSRWE

Description

Data cannot be written to bits 2 and 0

Data can be written to bits 2 and 0

(initial value)

Bit 3Bit 2 Write Inhibit (B2WI): Bit 3 controls the writing of data to bit 2 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 3: B2WI

Description

Bit 2 is write-enabled

Bit 2 is write-protected

(initial value)

Bit 2Watchdog Timer On (WDON): Bit 2 enables watchdog timer operation.

Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 2: WDON

Description

Watchdog timer operation is disabled

(initial value)

Clearing conditions:
Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON
1

Watchdog timer operation is enabled

Setting conditions:
When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON

275

Bit 1Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 1: B0WI

Description

Bit 0 is write-enabled

Bit 0 is write-protected

(initial value)

Bit 0Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed, generating
an internal reset signal. The internal reset signal generated by the overflow resets the entire chip.
WRST is cleared to 0 by a reset from the RES pin, or when software writes 0.
Bit 0: WRST

Description

Clearing conditions:
(initial value)
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST

Setting conditions:
When TCW overflows and an internal reset signal is generated

Timer Counter W (TCW)

Bit

TCW7

TCW6

TCW5

TCW4

TCW3

TCW2

TCW1

TCW0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is /8192. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.

276

9.6.3

Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (/8192).
When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in
WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate
the watchdog timer). When the TCW count value reaches H'FF, the next clock input causes the
watchdog timer to overflow and generates an internal reset signal. The internal reset signal is
output for 512 clock cycles of the OSC clock. It is possible to write to TCW, causing TCW to
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.36 shows an example of watchdog timer operations.
Example: = 4 MHz and the desired overflow period is 30 ms.
4 106
30 103 = 14.6
8192

The value set in TCW should therefore be 256 15 = 241 (H'F1).

TCW overflow

H'FF
H'F1
TCW count
value

H'00
Start
H'F1 written
in TCW

H'F1 written in TCW

Reset

Internal reset
signal
512 OSC clock cycles

Figure 9.36 Typical Watchdog Timer Operations (Example)

277

9.6.4

Watchdog Timer Operation States

Table 9.21 summarizes the watchdog timer operation states.

Table 9.21 Watchdog Timer Operation States
Operation Mode

Reset

Active

Sleep

Watch

Subactive

Subsleep

Standby

TCW

Reset

Functions

Functions

Halted

Halted

Halted

Halted

TCSRW

Reset

Functions

Functions

Retained

Retained Retained Retained

278

Section 10 Serial Communication Interface

10.1

Overview

The H8/3644 Series is provided with a two-channel serial communication interface (SCI). Table
10.1 summarizes the functions and features of the two SCI channels.
Table 10.1 Serial Communication Interface Functions
Channel
SCI1

Functions

Features

Synchronous serial transfer

Choice of 8 internal clocks (/1024 to /2)

or external clock
Open drain output possible
Interrupt requested at completion of
transfer

Choice of 8-bit or 16-bit data length

Continuous clock output

SCI3

Synchronous serial transfer

8-bit data length
Send, receive, or simultaneous
send/receive
Asynchronous serial transfer

On-chip baud rate generator

Receive error detection
Break detection
Interrupt requested at completion of
transfer or error

Multiprocessor communication
Choice of 7-bit or 8-bit data length
Choice of 1 or 2 stop bits
Parity addition

10.2

SCI1

10.2.1

Overview

Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit
data. SSB (Synchronized Serial Bus) communication is also provided, enabling multiple ICs to be
controlled.
Features
Choice of 8-bit or 16-bit data length
Choice of eight internal clock sources (/1024, /256, /64, /32, /16, /8, /4, /2) or an
external clock
Interrupt requested at completion of transfer
Choice of HOLD mode or LATCH mode in SSB mode.
Block Diagram
281

Figure 10.1 shows a block diagram of SCI1.

PSS

SCR1

SCK1

Transmit/receive
control circuit

SCSR1

Internal data bus

Transfer bit counter

SDRU

SI1

SDRL
SO1
IRRS1
Legend:
SCR1:
SCSR1:
SDRU:
SDRL:
IRRS1:
PSS:

Serial control register 1

Serial control/status register 1
Serial data register U
Serial data register L
SCI1 interrupt request flag
Prescaler S

Figure 10.1 SCI1 Block Diagram

282

Pin Configuration
Table 10.2 shows the SCI1 pin configuration.
Table 10.2 Pin Configuration
Name

Abbrev.

I/O

Function

SCI1 clock pin

SCK 1

I/O

SCI1 clock input or output

SCI1 data input pin

SI 1

Input

SCI1 receive data input

SCI1 data output pin

SO1

Output

SCI1 transmit data output

Register Configuration
Table 10.3 shows the SCI1 register configuration.
Table 10.3 SCI1 Registers
Name

Abbrev.

R/W

Initial Value

Address

Serial control register 1

SCR1

R/W

H'00

H'FFA0

Serial control status register 1

SCSR1

R/W

H'9C

H'FFA1

Serial data register U

SDRU

R/W

Not fixed

H'FFA2

Serial data register L

SDRL

R/W

Not fixed

H'FFA3

283

10.2.2

Register Descriptions

Serial Control Register 1 (SCR1)

Bit

SNC1

SNC0

MRKON

LTCH

CKS3

CKS2

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source,
and the prescaler division ratio.
Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the transfer.
Bits 7 and 6Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation
mode.
Bit 7: SNC1

Bit 6: SNC0

Description

8-bit synchronous transfer mode

16-bit synchronous transfer mode

Continuous clock output mode*1

Reserved*2

(initial value)

Notes: 1. Pins SI 1 and SO1 should be used as general input or output ports.
2. Dont set bits SNC1 and SNC0 to 11.

Bits 5TAIL MARK Control (MRKON): Bit 5 controls TAIL MARK output after an 8- or 16bit data transfer.
Bit 5: MRKON

Description

TAIL MARK is not output (synchronous mode)

TAIL MARK is output (SSB mode)

(initial value)

Bits 4LATCH TAIL Select (LTCH): Bit 4 selects whether LATCH TAIL or HOLD TAIL is
output as TAIL MARK when bit MRKON is set to 1 (SSB mode).
Bit 4: LTCH

Description

HOLD TAIL is output

LATCH TAIL is output

(initial value)

Bit 3Clock Source Select (CKS3): Bit 3 selects the clock source and sets pin SCK1 as an input
or output pin.
284

Bit 3: CKS3

Description

Clock source is prescaler S, and pin SCK 1 is output pin

Clock source is external clock, and pin SCK1 is input pin

(initial value)

Bits 2 to 0Clock Select (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler
division ratio and the serial clock cycle.
Serial Clock Cycle
Bit 2: CKS2

Bit 1: CKS1

Bit 0: CKS0

Prescaler Division

= 5 MHz

= 2.5 MHz

/1024 (initial value)

204.8 s

409.6 s

/256

51.2 s

102.4 s

/64

12.8 s

25.6 s

/32

6.4 s

12.8 s

/16

3.2 s

6.4 s

/8

1.6 s

3.2 s

/4

0.8 s

1.6 s

/2

0.8 s

285

Serial Control/Status Register 1 (SCSR1)

Bit

SOL

ORER

MTRF

STF

Initial value

Read/Write

R/W

R/(W)*

R/W

Note: * Only a write of 0 for flag clearing is possible.

SCSR1 is an 8-bit read/write register indicating operation status and error status.
Upon reset, SCSR1 is initialized to H'9C.
Bit 7Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified.
Bit 6Extended Data Bit (SOL): Bit 6 sets the SO1 output level. When read, SOL returns the
output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value
of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or
after a transmission. The SOL bit setting remains valid only until the start of the next transmission.
SSB mode settings also become invalid. To control the level of the SO1 pin after transmission
ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this
register while transmission is in progress, because that may cause a malfunction.
Bit 6: SOL

Description

Read: SO 1 pin output level is low

(initial value)

Write: SO1 pin output level changes to low

1

Read: SO 1 pin output level is high

Write: SO1 pin output level changes to high

Bit 5Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the
occurrence of an overrun error. If noise occurs during a transfer, causing an extraneous pulse to be
superimposed on the normal serial clock, incorrect data may be transferred. If a clock pulse is
input after transfer completion, this bit is set to 1 indicating an overrun.
Bit 5: ORER

Description

Clearing conditions:
After reading ORER = 1, cleared by writing 0 to ORER

286

(initial value)

Setting conditions:
Set if a clock pulse is input after transfer is complete, when an external clock is
used

Bits 4 to 2Reserved Bits: Bits 4 to 2 are reserved. They are always read as 0, and cannot be
modified.
Bit 1TAIL MARK Transmit Flag (MTRF): When bit MRKON is set to 1, bit 1 indicates that
TAIL MARK is being sent. Bit 1 is a read-only bit and cannot be modified.
Bit 1: MTRF

Description

Idle state, or 8- or 16-bit data is being transferred

TAIL MARK is being sent

(initial value)

Bit 0Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF

Description

Read: Indicates that transfer is stopped

(initial value)

Write: Invalid
1

Read: Indicates transfer in progress

Write: Starts a transfer operation

Serial Data Register U (SDRU)

Bit

Initial value
Read/Write

SDRU7

SDRU6

SDRU5

SDRU4

SDRU3

SDRU2

SDRU1

SDRU0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is not fixed.

287

Serial Data Register L (SDRL)

Bit

Initial value
Read/Write

SDRL7

SDRL6

SDRL5

SDRL4

SDRL3

SDRL2

SDRL1

SDRL0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit
(LSB). This data is then replaced by LSB-first data input at pin SI 1, which is shifted in the
direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU.
SDRL must be written or read only after data transmission or reception is complete. If this register
is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL value upon reset is not fixed.
10.2.3

Operation in Synchronous Mode

Data can be sent and received in an 8-bit or 16-bit format, with an internal or external clock
selected as the clock source. Overrun errors can be detected when an external clock is used.
Clock: The serial clock can be selected from a choice of eight internal clocks and an external
clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When
continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock
signal (/1024 to /2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When
an external clock is used, pin SCK1 is the clock input pin.
Data Transfer Format: Figure 10.2 shows the data transfer format. Data is sent and received
starting from the least significant bit, in LSB-first format. Transmit data is output from one falling
edge of the serial clock until the next rising edge. Receive data is latched at the rising edge of the
serial clock.

SCK 1
SO1 /SI 1

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Figure 10.2 Transfer Format

288

Bit 6

Bit 7

Data Transfer Operations

Transmitting: A transmit operation is carried out as follows.
1. Set bits SO1 and SCK1 to 1 in PMR3 to select the SO1 and SCK1 pin functions. If necessary,
set bit POF1 in PMR7 for NMOS open-drain output at pin SO 1.
2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating
8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing
data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1.
3. Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1.
5. After data transmission is complete, bit IRRS1 in interrupt request register 2 (IRR2) is
set to 1.
When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit
transmitted.
When an external clock is used, data is transmitted in synchronization with the serial clock input at
pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be
input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in
SCSR1.
Receiving: A receive operation is carried out as follows.
1. Set bits SI1 and SCK1 to 1 in PMR3 to select the SI1 and SCK1 pin functions.
2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating
8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing
data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1.
3. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI 1.
4. After data reception is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1.
5. Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
6. After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.

289

Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as

follows.
1. Set bits SO1, SI1, and SCK1 to 1 in PMR3 to select the SO1, SI1, and SCK1 pin functions. If
necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO1.
2. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating
8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing
data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1.
3. Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO 1.
Receive data is input at pin SI1.
5. After data transmission and reception are complete, bit IRRS1 in IRR2 is set to 1.
6. Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK 1. After data transmission and reception are complete, an overrun occurs if
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in
SCSR1.

290

10.2.4

Operation in SSB Mode

SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables
multiple ICs to be connected as shown in figure 10.3.
In SSB mode, TAIL MARK is sent after an 8- or 16-bit data transfer. HOLD TAIL or LATCH
TAIL can be selected as TAIL MARK.

SCL

H8/3644 SCK
1
Series LSI SO1

IC-A

IC-B

SDA

SCL

SDA

SCL

SDA

SCL

SDA

IC-C

Figure 10.3 Example of SSB Connection

Clock: The transfer clock can be selected from eight internal clocks or an external clock, but since
the H8/3644 Series uses clock output, an external clock should not be selected. The transfer rate
can be selected by bits CKS2 to CKS0 in SCR1. Since this is also the TAIL MARK transfer rate,
the setting should be made to give a transfer clock cycle of at least 2 s.
Data Transfer Format: Figure 10.4 shows the SCI1 transfer format. Data is sent starting from the
least significant bit, in LSB-first format. TAIL MARK is sent after an 8- or 16-bit data transfer.
SCK1

SO 1

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5 Bit 14 Bit 15

TAIL MARK
1 frame

Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1)

291

TAIL MARK: TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output
waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in the figure is
determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1.
< HOLD TAIL >

< LATCH TAIL >

SCK1

SCK1
t

SO 1

Bit 14 Bit 15

2t

Bit 0

SO 1

2t

Bit 14 Bit 15

Figure 10.5 HOLD TAIL and LATCH TAIL Waveforms

Transmitting: A transmit operation is carried out as follows.
1. Set bit SOL in SCSR1 to 1.
2. Set bits SO1 and SCK1 to 1 in PMR3 to select the S01 and SCK1 pin functions. Set bit POF1
in PMR7 to 1 for NMOS open-drain output at pin SO1.
3. Clear bit SNC1 in SCR1 to 0 and set bit SNC0 to 0 or 1, designating 8-bit mode or 16-bit
mode. Set bit MRKON in SCR1 to 1, selecting SSB mode.
4. Write transmit data in SDRL and SDRU as follows, and select TAIL MARK with bit LTCH
in SCR1.
8-bit mode: SDRL
16-bit mode: Upper byte in SDRU, lower byte in SDRL
5. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin S01.
6. After 8- or 16-bit data transmission is complete, bit STF in SCSR1 is cleared to 0 and bit
IRRS1 in interrupt request register 2 (IRRS2) is set to 1. The selected TAIL MARK is output
after the data transmission. During TAIL MARK output, bit MTRF in SCSR1 is set to 1.
Data can be sent continuously by repeating steps 4 to 6. Check that SCI1 is in the idle state before
rewriting bit MRKON in SCR1.

292

10.2.5

Interrupts

SCI1 can generate an interrupt at the end of a data transfer.

When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2
(IENR2).
For further details, see 3.3, Interrupts.

10.3

SCI3

10.3.1

Overview

Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
Features
Features of SCI3 are listed below.

Choice of asynchronous or synchronous mode for serial data communication

Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 12 data transfer formats.
Data length

7 or 8 bits

Stop bit length

1 or 2 bits

Parity

Even, odd, or none

Multiprocessor bit

1 or 0

Receive error detection

Parity, overrun, and framing errors

Break detection

Break detected by reading the RXD pin level directly when

a framing error occurs

293

 Synchronous mode
Serial data communication is synchronized with a clock. In his mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length

8 bits

Receive error detection

Overrun errors

Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
On-chip baud rate generator, allowing any desired bit rate to be selected
Choice of an internal or external clock as the transmit/receive clock source
Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error

294

Block Diagram
Figure 10.6 shows a block diagram of SCI3.

External
clock

SCK3

Internal clock (/64, /16, /4, )

Baud rate generator

BRC

BRR

SMR
Transmit/receive
control circuit

SCR3
SSR

TXD

TSR

TDR

RXD

RSR

RDR

Internal data bus

Clock

Interrupt request
(TEI, TXI, RXI, ERI)
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:

Receive shift register

Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter

Figure 10.6 SCI3 Block Diagram

295

Pin Configuration
Table 10.4 shows the SCI3 pin configuration.
Table 10.4 Pin Configuration
Name

Abbrev.

I/O

Function

SCI3 clock

SCK 3

I/O

SCI3 clock input/output

SCI3 receive data input

RXD

Input

SCI3 receive data input

SCI3 transmit data output

TXD

Output

SCI3 transmit data output

Register Configuration
Table 10.5 shows the SCI3 register configuration.
Table 10.5 Registers
Name

Abbrev.

R/W

Initial Value

Address

Serial mode register

SMR

R/W

H'00

H'FFA8

Bit rate register

BRR

R/W

H'FF

H'FFA9

Serial control register 3

SCR3

R/W

H'00

H'FFAA

Transmit data register

TDR

R/W

H'FF

H'FFAB

Serial status register

SSR

R/W

H'84

H'FFAC

Receive data register

RDR

H'00

H'FFAD

Transmit shift register

TSR

Protected

Receive shift register

RSR

Protected

Bit rate counter

BRC

Protected

10.3.2

Register Descriptions

Receive Shift Register (RSR)

Bit

Read/Write

296

RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
Receive Data Register (RDR)
Bit

RDR7

RDR6

RDR5

RDR4

RDR3

RDR2

RDR1

RDR0

Initial value

Read/Write

RDR is an 8-bit register that stores received serial data.

When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then enabled for reception. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Transmit Shift Register (TSR)
Bit

Read/Write

TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred from TDR to TSR, and transmission started, automatically. Data transfer from TDR to
TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial
status register (SSR)).
TSR cannot be read or written directly by the CPU.

297

Transmit Data Register (TDR)

Bit

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1

TDR0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode.
Serial Mode Register (SMR)
Bit

COM

CHR

PE

PM

STOP

MP

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7Communication Mode (COM): Bit 7 selects whether SCI3 operates in asynchronous
mode or synchronous mode.
Bit 7: COM

Description

Asynchronous mode

Synchronous mode

298

(initial value)

Bit 6Character Length (CHR): Bit 6 selects either 7 or 8 bits as the data length to be used in
asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6
setting.
Bit 6: CHR

Description

8-bit data

7-bit data*

(initial value)

Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.

Bit 5Parity Enable (PE): Bit 5 selects whether a parity bit is to be added during transmission
and checked during reception in asynchronous mode. In synchronous mode parity bit addition and
checking is not performed, irrespective of the bit 5 setting.
Bit 5: PE

Description

Parity bit addition and checking disabled

Parity bit addition and checking enabled*

(initial value)

Note: * When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit data
before it is sent, and the received parity bit is checked against the parity designated by bit
PM.

Bit 4Parity Mode (PM): Bit 4 selects whether even or odd parity is to be used for parity
addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set
to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode,
and in asynchronous mode if parity bit addition and checking is disabled.
Bit 4: PM

Description

Even parity*1

(initial value)

Odd parity*

Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.

299

Bit 3Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous
mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is
selected the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP

Description

1 stop bit *1

2 stop bits*

(initial value)
2

Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.

In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication
function. When the multiprocessor communication function is enabled, the parity settings in the
PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When
synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor
communication function, see 10.3.6.
Bit 2: MP

Description

Multiprocessor communication function disabled

Multiprocessor communication function enabled

(initial value)

Bits 1 and 0Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 choose /64, /16, /4, or as the
clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see Bit Rate
Register (BRR).
Bit 1: CKS1

Bit 0: CKS0

Description

clock

/4 clock

/16 clock

/16 clock

300

(initial value)

Serial Control Register 3 (SCR3)

Bit

TIE

RIE

TE

RE

MPIE

TEIE

CKE1

CKE0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7Transmit interrupt Enable (TIE): Bit 7 selects enabling or disabling of the transmit data
empty interrupt request (TXI) when transmit data is transferred from the transmit data register
(TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to
1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7: TIE

Description

Transmit data empty interrupt request (TXI) disabled

Transmit data empty interrupt request (TXI) enabled

(initial value)

Bit 6Receive Interrupt Enable (RIE): Bit 6 selects enabling or disabling of the receive data
full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is
transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF
in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun,
framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6: RIE

Description

Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) disabled
(initial value)

Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) enabled

301

Bit 5Transmit Enable (TE): Bit 5 selects enabling or disabling of the start of transmit
operation.
Bit 5: TE

Description

Transmit operation disabled*1 (TXD pin is transmit data pin)*3

Transmit operation enabled * (TXD pin is transmit data pin) *

2

(initial value)

Notes: 1. Bit TDRE in SSR is fixed at 1.

2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings to decide the transmission format before setting bit TE to 1.
3. When bit TXD in PMR7 is set to 1. When bit TXD is cleared to 0, the TXD pin functions
as an I/O port regardless of the TE bit setting.

Bit 4Receive Enable (RE): Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4: RE

Description

Receive operation disabled *1 (RXD pin is I/O port)

Receive operation enabled*2 (RXD pin is receive data pin)

(initial value)

Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.

Bit 3Multiprocessor Interrupt Enable (MPIE): Bit 3 selects enabling or disabling of the
multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is
selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid
when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3: MPIE

Description

Multiprocessor interrupt request disabled (normal receive operation)

(initial value)
Clearing conditions:
When data is received in which the multiprocessor bit is set to 1

Multiprocessor interrupt request enabled*

Note: * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF,
FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF,
FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is
received. When a receive character with the multiprocessor bit set to 1 is received, bit
MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests
(when bits TIE and RIE in serial control register (SCR) are set to 1) and setting of the
RDRF, FER, and OER flags are enabled.

302

Bit 2Transmit End Interrupt Enable (TEIE): Bit 2 selects enabling or disabling of the
transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to
be sent.
Bit 2: TEIE

Description

Transmit end interrupt request (TEI) disabled

Transmit end interrupt request (TEI) enabled *

(initial value)

Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.

Bits 1 and 0Clock Enable 1 and 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and
enabling or disabling of clock output from the SCK3 pin. These bits determine whether the SCK3
pin functions as an I/O port, a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.10 in 10.3.3, Operation.
Description
Bit 1: CKE1

Bit 0: CKE0

Communication Mode

Clock Source

SCK3 Pin Function

Asynchronous

Internal clock

I/O port*1

Synchronous

Internal clock

Serial clock output *1

Asynchronous

Internal clock

Clock output*2

Synchronous

Reserved

Asynchronous

External clock

Clock input *3

Synchronous

External clock

Serial clock input

Asynchronous

Reserved

Synchronous

Reserved

Notes: 1. Initial value

2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.

303

Serial Status Register (SSR)

Bit

TDRE

RDRF

OER

FER

PER

TEND

MPBR

MPBT

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/W

Note: * Only a write of 0 for flag clearing is possible.

SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been
transferred from TDR to TSR.
Bit 7: TDRE

Description

Transmit data written in TDR has not been transferred to TSR

Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction

Transmit data has not been written to TDR, or transmit data written in TDR has
been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR

304

(initial value)

Bit 6Receive Data Register Full (RDRF): Bit 6 indicates that received data is stored in RDR.
Bit 6: RDRF

Description

There is no receive data in RDR

(initial value)

Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
1

There is receive data in RDR

Setting conditions:
When reception ends normally and receive data is transferred from RSR to
RDR

Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.

Bit 5Overrun Error (OER): Bit 5 indicates that an overrun error has occurred during
reception.
Bit 5: OER

Description

Reception in progress or completed*1

(initial value)

Clearing conditions:
After reading OER = 1, cleared by writing 0 to OER
1

An overrun error has occurred during reception*2

Setting conditions:
When reception is completed with RDRF set to 1

Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.

305

Bit 4Framing Error (FER): Bit 4 indicates that a framing error has occurred during reception
in asynchronous mode.
Bit 4: FER

Description

Reception in progress or completed*1

(initial value)

Clearing conditions:
After reading FER = 1, cleared by writing 0 to FER
1

A framing error has occurred during reception*2

Setting conditions:
When the stop bit at the end of the receive data is checked for a value of 1 at
the end of reception, and the stop bit is 0*2

Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.

Bit 3Parity Error (PER): Bit 3 indicates that a parity error has occurred during reception with
parity added in asynchronous mode.
Bit 3: PER

Description

Reception in progress or completed*1

(initial value)

Clearing conditions:
After reading PER = 1, cleared by writing 0 to PER
1

A parity error has occurred during reception*2

Setting conditions:
When the number of 1 bits in the receive data plus parity bit does not match
the parity designated by bit PM in the serial mode register (SMR)

Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit PER is set to 1.

306

Bit 2Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a
transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2: TEND

Description

Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction

Transmission ended

(initial value)

Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent

Bit 1Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive
character during multiprocessor format reception in asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1: MPBR

Description

Data in which the multiprocessor bit is 0 has been received *

Data in which the multiprocessor bit is 1 has been received

(initial value)

Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.

Bit 0Multiprocessor Bit Transfer (MPBT): Bit 0 stores the multiprocessor bit added to
transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when
synchronous mode is selected, when the multiprocessor communication function is disabled, and
when not transmitting.
Bit 0: MPBT

Description

A 0 multiprocessor bit is transmitted

A 1 multiprocessor bit is transmitted

(initial value)

307

Bit Rate Register (BRR)

Bit

BRR7

BRR6

BRR5

BRR4

BRR3

BRR2

BRR1

BRR0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode.
Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)

OSC (MHz)
2

2.4576

4.194304

Bit Rate
(bits/s)

Error
(%)

Error
(%)

Error
(%)

Error
(%)

110

70

+0.03

86

+0.31

141

+0.03

148

0.04

150

207

+0.16

255

103

+0.16

108

+0.21

300

103

+0.16

127

207

+0.16

217

+0.21

600

51

+0.16

63

103

+0.16

108

+0.21

1200

25

+0.16

31

51

+0.16

54

0.70

2400

12

+0.16

15

25

+0.16

26

+1.14

4800

12

+0.16

13

2.48

9600

2.48

19200

31250

38400

308

Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (cont)
OSC (MHz)
4.9152

7.3728

Bit Rate
(bits/s)

Error
(%)

Error
(%)

Error
(%)

Error
(%)

110

174

0.26

212

+0.03

64

+0.70

70

+0.03

150

127

155

+0.16

191

207

+0.16

300

255

77

+0.16

95

103

+0.16

600

127

155

+0.16

191

207

+0.16

1200

63

77

+0.16

95

103

+0.16

2400

31

38

+0.16

47

51

+0.16

4800

15

19

2.34

23

25

+0.16

9600

2.34

11

12

+0.16

19200

2.34

31250

38400

Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (cont)
OSC (MHz)
9.8304

10

Bit Rate
(bits/s)

Error
(%)

Error
(%)

110

86

+0.31

88

0.25

150

255

64

+0.16

300

127

129

+0.16

600

255

64

+0.16

1200

127

129

+0.16

2400

63

64

+0.16

4800

31

32

1.36

9600

15

15

+1.73

19200

+1.73

31250

1.70

38400

+1.73

309

Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
N=

OSC
106 1
(64 22n B)

where
B:
Bit rate (bit/s)
N:
Baud rate generator BRR setting (0 N 255)
OSC: Value of OSC (MHz)
n:
Baud rate generator input clock number (n = 0, 1, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Table 10.7 Relation between n and Clock
SMR Setting
n

Clock

CKS1

CKS0

/4

16

/64

3. The error in table 10.6 is the value obtained from the following equation, rounded to
two decimal places.
Error (%) =

310

B (rate obtained from n, N, OSC) R (bit rate in left-hand column in table 10.6)
100
R (bit rate in left-hand column in table 10.6)

Table 10.8 shows the maximum bit rate for each frequency. The values shown are for active (highspeed) mode.
Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)

Maximum Bit Rate (bits/s)

31250

2.4576

38400

62500

4.194304

65536

4.9152

76800

93750

7.3728

115200

125000

9.8304

153600

10

156250

311

Table 10.9 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode)
OSC (MHz)
2

10

Bit Rate
(bits/s)

110

250

249

124

249

500

124

249

124

1k

249

124

249

2.5k

99

199

99

124

5k

49

99

199

249

10k

24

49

99

124

25k

19

39

49

50k

19

24

100k

250k

0*

0*

0*

500k
1M
2.5M

Blank: Cannot be set.

:
A setting can be made, but an error will result.
*:
Continuous transmission/reception is not possible.

312

Note: The value set in BRR is given by the following equation:

N=

OSC
106 1
(8 22n B)

where
B:
N:
OSC:
n:

Bit rate (bit/s)

Baud rate generator BRR setting (0 N 255)
Value of OSC (MHz)
Baud rate generator input clock number (n = 0, 1, 2, or 3)
(The relation between n and the clock is shown in table 10.10.)

Table 10.10 Relation between n and Clock

SMR Setting
n

Clock

CKS1

CKS0

/4

16

/64

313

10.3.3

Operation

SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.11.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.12.
Asynchronous Mode
Choice of 7- or 8-bit data length
Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The
combination of these parameters determines the data transfer format and the character length.)
Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
Synchronous Mode
Data transfer format: Fixed 8-bit data length
Overrun error (OER) detection during reception
Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.

314

Table 10.11 SMR Settings and Corresponding Data Transfer Formats

SMR Setting

Communication Format

Bit 7: Bit 6: Bit 2: Bit 5: Bit 3:

COM CHR MP
PE
STOP Mode

MultiproData Length cessor Bit

Parity Stop Bit

Bit
Length

8-bit data

No

0
1

Asynchronous
mode

No

2 bits

Yes

1
1

7-bit data

No

1 bit
2 bits

Yes

1
0

1 bit
2 bits

1
1

1 bit

1 bit
2 bits

Asynchronous 8-bit data

mode
(multiprocessor
7-bit data
format)

Yes

Synchronous
mode

No

8-bit data

No

1 bit
2 bits
1 bit
2 bits

No

No

Note: * Dont care

Table 10.12 SMR and SCR3 Settings and Clock Source Selection
SMR

SCR3

Bit 7:
COM

Bit 1:
CKE1

Bit 0:
CKE0

0
1

Transmit/Receive Clock
Mode
Asynchronous
mode

Clock
Source

SCK3 Pin Function

Internal

I/O port (SCK3 pin not used)

Outputs clock with same frequency as
bit rate

Synchronous
mode

Reserved (Do not specify these combinations)

External

Outputs clock with frequency 16 times

bit rate

Internal

Outputs serial clock

External

Inputs serial clock

315

Interrupts and Continuous Transmission/Reception: SCI3 can carry out continuous reception
using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13.
Table 10.13 Transmit/Receive Interrupts
Interrupt
RXI

Flags
RDRF
RIE

TXI

TDRE
TIE

TEI

TEND
TEIE

316

Interrupt Request Conditions

Notes

When serial reception is performed

normally and receive data is
transferred from RSR to RDR, bit
RDRF is set to 1, and if bit RIE is set
to 1 at this time, RXI is enabled and
an interrupt is requested. (See figure
10.7 (a).)

The RXI interrupt routine reads

the receive data transferred to
RDR and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.

When TSR is found to be empty (on

completion of the previous
transmission) and the transmit data
placed in TDR is transferred to TSR,
bit TDRE is set to 1. If bit TIE is set to
1 at this time, TXI is enabled and an
interrupt is requested. (See figure
10.7 (b).)

The TXI interrupt routine writes

the next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.

When the last bit of the character in

TSR is transmitted, if bit TDRE is set
to 1, bit TEND is set to 1. If bit TEIE is
set to 1 at this time, TEI is enabled
and an interrupt is requested. (See
figure 10.7 (c).)

TEI indicates that the next

transmit data has not been written
to TDR when the last bit of the
transmit character in TSR is sent.

RDR

RDR

RSR (reception in progress)

RXD pin

RSR (reception completed, transfer)

RXD pin
RDRF 1
(RXI request when RIE = 1)

RDRF = 0

Figure 10.7 (a) RDRF Setting and RXI Interrupt

TDR (next transmit data)

TDR

TSR (transmission in progress)

TSR (transmission completed, transfer)

TXD pin

TXD pin
TDRE 1
(TXI request when TIE = 1)

TDRE = 0

Figure 10.7 (b) TDRE Setting and TXI Interrupt

TDR

TDR

TSR (transmission in progress)

TSR (reception completed)

TXD pin

TXD pin
TEND = 0

TEND 1
(TEI request when TEIE = 1)

Figure 10.7 (c) TEND Setting and TEI Interrupt

317

10.3.4

Operation in Asynchronous Mode

In asynchronous mode, serial communication is performed with synchronization provided

character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
Data Transfer Format: The general data transfer format in asynchronous communication is
shown in figure 10.8.
(LSB)
Serial
data

(MSB)

Start
bit

Transmit/receive data

1 bit

7 or 8 bits

1
Parity
bit

1 bit
or none

Stop
bit(s)

Mark
state

1 or 2 bits

One transfer data unit (character or frame)

Figure 10.8 Data Format in Asynchronous Communication

In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period,
so that the transfer data is latched at the center of each bit.

318

Table 10.14 shows the 12 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
Table 10.14 Data Transfer Formats (Asynchronous Mode)
SMR Settings

Serial Data Transfer Format and Frame Length

CHR

PE

MP

STOP

10

11

12

8-bit data

STOP

8-bit data

STOP STOP

8-bit data

STOP

8-bit data

STOP STOP

7-bit data

STOP

7-bit data

STOP STOP

7-bit data

STOP

7-bit data

STOP STOP

8-bit data

MPB STOP

8-bit data

MPB STOP STOP

7-bit data

MPB STOP

7-bit data

MPB STOP STOP

* Dont care
Legend:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit

319

Clock: Either an internal clock generated by the baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means
of bit COM in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock
source selection.
When an external clock is input at the SCK3 pin, a clock with a frequency of 16 times the bit rate
used should be input.
When SCI3 operates on an internal clock, the clock can be output at the SCK 3 pin. In this case the
frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises
at the center of each bit of transmit/receive data, as shown in figure 10.9.

Clock
Serial
data

D0

D1

D2

D3

D4

D5

D6

D7

0/1

1 character (1 frame)

Figure 10.9 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
Data Transfer Operations
SCI3 Initialization: Before data is transferred on SCI3, bits TE and RE in SCR3 must first be
cleared to 0, and then SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.

320

Figure 10.10 shows an example of a flowchart for initializing SCI3.

Start

Clear bits TE and

RE to 0 in SCR3

Set bits CKE1

and CKE0

Set data transfer

format in SMR

Set value in BRR

1. Set clock selection in SCR3. Be sure to

clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
2. Set the data transfer format in the serial
mode register (SMR).

Wait

Has 1-bit period

elapsed?
Yes

Set bit TE or RE to
1 in SCR3, set bits
RIE, TIE, TEIE, and
MPIE as necessary,
and when transmitting
(TE = 1), set bit TXD
to 1 in PMR7

No

3. Write the value corresponding to the

transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
4. Wait for at least the interval required to
transmit or receive one bit, then set TE or
RE in the serial control register (SCR3).
Setting RE enables the RxD pin to be used,
and when transmitting, setting bit TXD in
PMR7 enables the TXD output pin to be
used.
Also set the RIE, TIE, TEIE, and MPIE bits
as necessary to enable interrupts. The
initial states are the mark transmit state
and the idle receive state (waiting for a
start bit).

End

Figure 10.10 Example of SCI3 Initialization Flowchart

321

Transmitting: Figure 10.11 shows an example of a flowchart for data transmission. This
procedure should be followed for data transmission after initializing SCI3.

Start

Read bit TDRE

in SSR

No
TDRE = 1?

2. When continuing data transmission,

be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.

Yes
Write transmit
data to TDR

Continue data
transmission?

1. Read the serial status register (SSR)

and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.

Yes

No

3. If a break is to be output when data

transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TXD in PMR7 and bit TE in SCR3 to 0.

Read bit TEND

in SSR

TEND = 1?

No

Yes
3

Break output?

No

Yes
Set PDR = 0,
PCR = 1

Clear bit TE to 0
in SCR3

End

Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode)

322

SCI3 operates as follows when transmitting data.

SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit
TDRE is set to 1, bit TEND in SSR is set to 1, and the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.12 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data

Transmit
data
D0

D1

D7

Parity Stop Start

bit
bit bit
0/1

1 frame

Transmit
data
D0

D1

D7

Parity Stop
bit
bit
0/1

Mark
state
1

1 frame

TDRE
TEND
LSI
TXI request
operation

TDRE
cleared to 0

User
processing

Data written
to TDR

TXI request

TEI request

Figure 10.12 Example of Operation when Transmitting in Asynchronous Mode

(8-Bit Data, Parity, 1 Stop Bit)

323

Receiving: Figure 10.13 shows an example of a flowchart for data reception. This procedure
should be followed for data reception after initializing SCI3.

Start

Read bits OER,

PER, FER in SSR

OER + PER
+ FER = 1?

1. Read bits OER, PER, and FER in the

serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.

Yes

2. Read SSR and check that bit RDRF is

set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.

No
2

Read bit RDRF

in SSR

RDRF = 1?

3.

No

When continuing data reception, finish

reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.

Yes
Read receive
data in RDR

Continue data
reception?

Receive error
processing

Yes

No
(A)
Clear bit RE to
0 in SCR3

End

Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode)

324

Start receive
error processing
Overrun error
processing
OER = 1?

Yes

No
FER = 1?

Break?
Yes

No

No
PER = 1?

Yes

4. If a receive error has

occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD pin.

Framing error
processing

No
Clear bits OER, PER,
FER to 0 in SSR

Parity error
processing

(A)

End of receive
error processing

Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode) (cont)

325

SCI3 operates as follows when receiving data.

SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant data
transfer format in table 10.14. The received data is first placed in RSR in LSB-to-MSB order, and
then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
Status check
SCI3 checks that bit RDRF is set to 1, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.15 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.15 Receive Error Detection Conditions and Receive Data Processing
Receive Error

Abbreviation

Detection Conditions

Received Data Processing

Overrun error

OER

When the next date receive

operation is completed while bit
RDRF is still set to 1 in SSR

Receive data is not transferred

from RSR to RDR

Framing error

FER

When the stop bit is 0

Receive data is transferred

from RSR to RDR

Parity error

PER

When the parity (odd or even)

set in SMR is different from that
of the received data

Receive data is transferred

from RSR to RDR

326

Figure 10.14 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data

Receive
data
D0

D1

D7

Parity Stop Start

bit
bit bit
0/1

1 frame

Receive
data
D0

D1

Parity Stop
bit
bit
D7

0/1

Mark state
(idle state)
1

1 frame

RDRF
FER
LSI
operation

RXI request

RDRF
cleared to 0
RDR data read

User
processing

0 start bit
detected

ERI request in
response to
framing error
Framing error
processing

Figure 10.14 Example of Operation when Receiving in Asynchronous Mode

(8-Bit Data, Parity, 1 Stop Bit)
10.3.5

Operation in Synchronous Mode

In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.

327

Data Transfer Format: The general data transfer format in synchronous communication is shown
in figure 10.15.

Serial
clock
LSB
Serial
data

Bit 0

Don't
care

MSB
Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

8 bits

Bit 7

Don't
care

One transfer data unit (character or frame)

Note: High level except in continuous transmission/reception

Figure 10.15 Data Format in Synchronous Communication

In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the
serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the MSB,
the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity and multiprocessor bits cannot be added.
Clock: Either an internal clock generated by the baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM
in SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK 3 pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.

328

Data Transfer Operations

SCI3 Initialization: Data transfer on SCI3 first of all requires that SCI3 be initialized as described
in 10.3.4, SCI3 Initialization, and shown in figure 10.10.
Transmitting: Figure 10.16 shows an example of a flowchart for data transmission. This
procedure should be followed for data transmission after initializing SCI3.

Start

Read bit TDRE

in SSR

No
TDRE = 1?

2. When continuing data transmission, be

sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.

Yes
Write transmit
data to TDR

Continue data
transmission?

1. Read the serial status register (SSR) and

check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started.

Yes

No
Read bit TEND
in SSR

TEND = 1?

No

Yes
Clear bit TE to 0
in SCR3

End

Figure 10.16 Example of Data Transmission Flowchart (Synchronous Mode)

329

SCI3 operates as follows when transmitting data.

SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is
selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK3 pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags (OER, FER, and PER) are all
cleared to 0 before a transmit operation.
Figure 10.17 shows an example of the operation when transmitting in synchronous mode.

Serial
clock
Serial
data

Bit 0

Bit 1

Bit 7

1 frame

Bit 0

Bit 1

Bit 6

Bit 7

1 frame

TDRE
TEND
LSI
TXI request
operation

TDRE cleared
to 0

User
processing

Data written
to TDR

TXI request

TEI request

Figure 10.17 Example of Operation when Transmitting in Synchronous Mode

330

Receiving: Figure 10.18 shows an example of a flowchart for data reception. This procedure
should be followed for data reception after initializing SCI3.

Start

Read bit OER

in SSR

1. Read bit OER in the serial status register

(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes

OER = 1?

2. Read SSR and check that bit RDRF is

set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.

No
2

Read bit RDRF

in SSR

RDRF = 1?

3. When continuing data reception, finish

reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.

No

4. If an overrun error has occurred, read bit

OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.

Yes
Read receive
data in RDR

Continue data
reception?

Overrun error
processing

Yes

No
Clear bit RE to
0 in SCR3

End

Start overrun
error processing

Overrun error
processing

Clear bit OER to

0 in SSR

End of overrun
error processing

Figure 10.18 Example of Data Reception Flowchart (Synchronous Mode)

331

SCI3 operates as follows when receiving data.

SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies
an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.15 for the conditions for detecting an overrun error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.19 shows an example of the operation when receiving in synchronous mode.

Serial
clock
Serial
data

Bit 7

Bit 0

Bit 7

Bit 0

1 frame

Bit 1

Bit 6

Bit 7

1 frame

RDRF
OER
LSI
operation
User
processing

RXI request

RDRE cleared
to 0
RDR data read

RXI request

ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)

Overrun error
processing

Figure 10.19 Example of Operation when Receiving in Synchronous Mode

332

Simultaneous Transmit/Receive: Figure 10.20 shows an example of a flowchart for a

simultaneous transmit/receive operation. This procedure should be followed for simultaneous
transmission/reception after initializing SCI3.

Start

Read bit TDRE

in SSR

1. Read the serial status register (SSR) and

check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.

No

TDRE = 1?

2. Read SSR and check that bit RDRF is set

to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.

Yes
Write transmit
data to TDR

3. When continuing data transmission/reception,

finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before transmitting the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.

Read bit OER

in SSR

Yes

OER = 1?

4. If an overrun error has occurred, read bit OER

in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission
and reception cannot be resumed if bit OER is
set to 1. See figure 10-18 for details on overrun
error processing.

No

Read bit RDRF

in SSR

No

RDRF = 1?
Yes
Read receive data
in RDR

Continue data
transmission/reception?

Overrun error
processing

Yes

No
Clear bits TE and
RE to 0 in SCR

End

Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart

(Synchronous Mode)
333

Notes: 1. When switching from transmission to simultaneous transmission/reception, check that

SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously with a single instruction.
2. When switching from reception to simultaneous transmission/reception, check that
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously with a single instruction.
10.3.6

Multiprocessor Communication Function

The multiprocessor communication function enables data to be exchanged among a number of

processors on a shared communication line. Serial data communication is performed in
asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the
transfer data).
In multiprocessor communication, each receiver is assigned its own ID code. The serial
communication cycle consists of two cycles, an ID transmission cycle in which the receiver is
specified, and a data transmission cycle in which the transfer data is sent to the specified receiver.
These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID
transmission cycle, and 0, a data transmission cycle.
The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver
it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the
transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it
compares the ID code with its own ID code, and if they are the same, receives the transfer data
sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor
bit set to 1 is sent again.
In this way, a number of processors can exchange data among themselves.
Figure 10.21 shows an example of communication between processors using the multiprocessor
format.

334

Sender
Communication line

Serial
data

Receiver A

Receiver B

Receiver C

Receiver D

(ID = 01)

(ID = 02)

(ID = 03)

(ID = 04)

H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)

H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified buy the ID)
MPB: Multiprocessor bit

Figure 10.21 Example of Inter-Processor Communication Using Multiprocessor Format

(Sending Data H'AA to Receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10.14 for details.
For details on the clock used in multiprocessor communication, see 10.3.4, Operation in
Synchronous Mode.
Multiprocessor Transmitting: Figure 10.22 shows an example of a flowchart for multiprocessor
data transmission. This procedure should be followed for multiprocessor data transmission after
initializing SCI3.

335

Start

Read bit TDRE

in SSR

TDRE = 1?

No

2. When continuing data transmission, be

sure to read TDRE = 1 to confirm that a
write can be performed before writing data
to TDR. When data is written to TDR, bit
TDRE is cleared to 0 automatically.

Yes
Set bit MPBT
in SSR

3. If a break is to be output when data

transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.

Write transmit
data to TDR

Continue data
transmission?

1. Read the serial status register (SSR)

and check that bit TDRE is set to 1,
then set bit MPBT in SSR to 0 or 1 and
write transmit data to the transmit data
register (TDR). When data is written to
TDR, bit TDRE is cleared to 0 automatically.

Yes

No
Read bit TEND
in SSR

TEND = 1?

No

Yes

Break output?

No

Yes
Set PDR = 0,
PCR = 1

Clear bit TE to
0 in SCR3

End

Figure 10.22 Example of Multiprocessor Data Transmission Flowchart

336

SCI3 operates as follows when transmitting data.

SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit
TDRE is set to 1, bit TEND in SSR is set to 1, and the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.23 shows an example of the operation when transmitting using the multiprocessor
format.
Start
bit
Serial
data

Transmit
data
D0

D1

D7

MPB
0/1

Stop Start
bit bit
1

1 frame

Transmit
data
D0

D1

MPB

D7

0/1

Stop
bit

Mark
state

1 frame

TDRE
TEND
LSI
TXI request
operation

TDRE
cleared to 0

User
processing

Data written
to TDR

TXI request

TEI request

Figure 10.23 Example of Operation when Transmitting using Multiprocessor Format

(8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
Multiprocessor Receiving: Figure 10.24 shows an example of a flowchart for multiprocessor data
reception. This procedure should be followed for multiprocessor data reception after initializing
SCI3.

337

Start

1. Set bit MPIE to 1 in SCR3.

Set bit MPIE to 1

in SCR3

2. Read bits OER and FER in the serial

status register (SSR) to determine if
there is an error. If a receive error has
occurred, execute receive error processing.

Read bits OER

and FER in SSR

OER + FER = 1?

3. Read SSR and check that bit RDRF is

set to 1. If it is, read the receive data in
RDR and compare it with this receiver's
own ID. If the ID is not this receiver's,
set bit MPIE to 1 again. When the RDR
data is read, bit RDRF is cleared to 0
automatically.

Yes

No
3

Read bit RDRF

in SSR

RDRF = 1?

4. Read SSR and check that bit RDRF is

set to 1, then read the data in RDR.

No

5. If a receive error has occurred, read bits

OER and FER in SSR to identify the error,
and after carrying out the necessary error
processing, ensure that bits OER and FER
are both cleared to 0. Reception cannot be
resumed if either of these bits is set to 1.
In the case of a framing error, a break can
be detected by reading the value of the
RXD pin.

Yes
Read receive
data in RDR

Own ID?

No

Yes
Read bits OER
and FER in SSR

OER + FER = 1?

Yes

No
4

Read bit RDRF

in SSR

RDRF = 1?

No

Yes
Read receive
data in RDR4

Continue data
reception?
No

Receive error
processing

Yes

(A)

Clear bit RE to
0 in SCR3
End

Figure 10.24 Example of Multiprocessor Data Reception Flowchart

338

Start receive
error processing
Overrun error
processing
OER = 1?

Yes
Yes

No
FER = 1?
No

Break?
Yes

No
Framing error
processing

Clear bits OER and

FER to 0 in SSR

End of receive
error processing

(A)

Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont)

Figure 10.25 shows an example of the operation when receiving using the multiprocessor format.

339

Start
bit
Serial
data

Receive
data (ID1)
D0

D1

D7

MPB
1

Stop Start
bit bit
1

Receive data
(Data1)
D0

1 frame

D1

D7

MPB

Stop
bit

Mark state
(idle state)

1 frame

MPIE

RDRF
RDR
value

ID1

LSI
operation

RDRF cleared
to 0

RXI request
MPIE cleared
to 0

No RXI request
RDR retains
previous state

RDR data read

User
processing

When data is not

this receiver's ID,
MPIE is set to 1
again

(a) When data does not match this receiver's ID

Start
bit
Serial
data

Receive
data (ID2)
D0

D1

D7

MPB
1

Stop Start
bit bit
1

Receive data
(Data2)
D0

1 frame

D1

D7

MPB

Stop
bit

Mark state
(idle state)

1 frame

MPIE

RDRF
RDR
value

ID1

LSI
operation
User
processing

ID2

RXI request
MPIE cleared
to 0

RDRF cleared
to 0
RDR data read

Data2

RXI request

When data is
this receiver's
ID, reception
is continued

RDRF cleared
to 0
RDR data read
MPIE set to 1
again

(b) When data matches this receiver's ID

Figure 10.25 Example of Operation when Receiving using Multiprocessor Format

(8-Bit Data, Multiprocessor Bit, 1 Stop Bit)
340

10.3.7

Interrupts

SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.16.
Table 10.16 SCI3 Interrupt Requests
Interrupt
Abbreviation

Interrupt Request

Vector Address

RXI

Interrupt request initiated by receive data full flag (RDRF)

H'0024

TXI

Interrupt request initiated by transmit data empty flag (TDRE)

TEI

Interrupt request initiated by transmit end flag (TEND)

ERI

Interrupt request initiated by receive error flag (OER, FER,

PER)

Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI
interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see 3.3, Interrupts.

341

10.3.8

Application Notes

The following points should be noted when using SCI3.

1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared
to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has
not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to
TDR once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to
the states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR
will not be performed, and the receive data will be lost.
Table 10.17 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER

FER

PER

Receive Data Transfer

(RSR RDR)
Receive Error Status

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity error

O: Receive data is transferred from RSR to RDR.

: Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception.

342

3. Break detection and processing

When a framing error is detected, a break can be detected by reading the value of the RXD pin
directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is
set and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD pin to the
mark state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1
and PDR = 1. Since bit TE is cleared to 0 at this time, the TXD pin functions as an I/O port and
1 is output.
To detect a break during transmission, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD pin functions as an I/O port, and 0 is output from the TXD pin.
5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even
if bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer
rate. When receiving, SCI3 performs internal synchronization by sampling the falling edge of
the start bit with the basic clock. Receive data is latched internally at the 8th rising edge of the
basic clock. This is illustrated in figure 10.26.

343

16 clock pulses
8 clock pulses
0

15 0

15 0

Internal
basic clock
Receive data
(RXD)

Start bit

D0

D1

Synchronization
sampling timing

Data sampling
timing

Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode

Consequently, the receive margin in asynchronous mode can be expressed as shown in
equation (1).

1
D 0.5
M = (0.5
)
(L 0.5) F 100 . . . . . . . . . . . . . . . Equation (1)
2N
N

where
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 1/(2 16)} 100 [%] = 46.875%

. . . . . . . . . . . . . . . . . . Equation (2)

However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.

344

7. Relation between RDR reads and bit RDRF

In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1,
this indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed
while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is
cleared to 0, if the read operation coincides with completion of reception of a frame, the next
frame of data may be read. This is illustrated in figure 10.27.

Communication
line

Frame 1

Frame 2

Frame 3

Data 1

Data 2

Data 3

Data 1

Data 3

RDRF

RDR

(A)
RDR read

(B)

RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)

Figure 10.27 Relation between RDR Read Timing and Data

In this case, only a single RDR read operation (not two or more) should be performed after
first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the
first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that
there is sufficient margin in an RDR read operation before reception of the next frame is
completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is
transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode.

345

Section 11 14-Bit PWM

11.1

Overview

The H8/3644 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can
be used as a D/A converter by connecting a low-pass filter.
11.1.1

Features

Features of the 14-bit PWM are as follows.

Choice of two conversion periods
A conversion period of 32,768/, with a minimum modulation width of 2/ or a conversion
period of 16,384/, with a minimum modulation width of 1/ can be chosen.
Pulse division method for less ripple
11.1.2

Block Diagram

Figure 11.1 shows a block diagram of the 14-bit PWM.

PWDRU

/2
/4

PWM
waveform
generator

Internal data bus

PWDRL

PWCR
PWM
Legend:
PWDRL: PWM data register L
PWDRU: PWM data register U
PWCR: PWM control register

Figure 11.1 Block Diagram of the 14-Bit PWM

347

11.1.3

Pin Configuration

Table 11.1 shows the output pin assigned to the 14-bit PWM.
Table 11.1 Pin Configuration
Name

Abbrev.

I/O

Function

PWM output pin

PWM

Output

Pulse-division PWM waveform output

11.1.4

Register Configuration

Table 11.2 shows the register configuration of the 14-bit PWM.

Table 11.2 Register Configuration
Name

Abbrev.

R/W

Initial Value

Address

PWM control register

PWCR

H'FE

H'FFD0

PWM data register U

PWDRU

H'C0

H'FFD1

PWM data register L

PWDRL

H'00

H'FFD2

11.2

Register Descriptions

11.2.1

PWM Control Register (PWCR)

Bit

PWCR0

Initial value

Read/Write

PWCR is an 8-bit write-only register for input clock selection.

Upon reset, PWCR is initialized to H'FE.
Bits 7 to 1Reserved Bits: Bits 7 to 1 are reserved; they are always read as 1, and cannot be
modified.

348

Bit 0Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a
write-only bit; it is always read as 1.
Bit 0: PWCR0

Description

The input clock is /2 (t* = 2/). The conversion period is 16,384/, with
a minimum modulation width of 1/
(initial value)

The input clock is /4 (t* = 4/). The conversion period is 32,768/, with
a minimum modulation width of 2/.

Note: * t : Period of PWM input clock

11.2.2

PWM Data Registers U and L (PWDRU, PWDRL)

PWDRU
Bit

Initial value

Read/Write

PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0

PWDRL
Bit

PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0

Initial value

Read/Write

PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM
waveform generator, updating the PWM waveform generation data. The 14-bit data should always
be written in the following sequence:
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.

349

11.3

Operation

When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P14/PWM is designated for PWM
output.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32,768/ (PWCR0 = 1) or 16,384/ (PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL.
This relation can be represented as follows.
TH = (data value in PWDRU and PWDRL + 64) t/2

where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1).
Example: Settings in order to obtain a conversion period of 8,192 s:
When bit PWCR0 = 0, the conversion period is 16,384/, so must be 2 MHz. In
this case tfn = 128 s, with 1/ (resolution) = 0.5 s.
When bit PWCR0 = 1, the conversion period is 32,768/, so must be 4 MHz. In
this case tfn = 128 s, with 2/ (resolution) = 0.5 s.
Accordingly, for a conversion period of 8,192 s, the system clock frequency ()
must be 2 MHz or 4 MHz.
1 conversion period
t f1

t H1

t f2

t H2

t f63

t H3

t H63

TH = t H1 + t H2 + t H3 + ..... t H64
t f1 = t f2 = t f3 ..... = t f64

Figure 11.2 PWM Output Waveform

350

t f64

t H64

Section 12 A/D Converter

12.1

Overview

The H8/3644 Series includes on-chip a resistance-ladder-based successive-approximation analogto-digital converter, and can convert up to 8 channels of analog input.
12.1.1

Features

The A/D converter has the following features.

8-bit resolution
Eight input channels
Conversion time: approx. 12.4 s per channel (at 5 MHz operation)
Built-in sample-and-hold function
Interrupt requested on completion of A/D conversion
A/D conversion can be started by external trigger input

351

12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the A/D converter.

ADTRG

Multiplexer

ADSR
AVCC
+
Comparator

AVCC
Reference
voltage

Control logic

AVSS
ADRR

AVSS

Legend:
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register

Figure 12.1 Block Diagram of the A/D Converter

352

Internal data bus

AMR
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7

IRRAD

12.1.3

Pin Configuration

Table 12.1 shows the A/D converter pin configuration.

Table 12.1 Pin Configuration
Name

Abbrev.

I/O

Function

Analog power supply

AVCC

Input

Power supply and reference voltage of analog part

Analog ground

AVSS

Input

Ground and reference voltage of analog part

Analog input 0

AN 0

Input

Analog input channel 0

Analog input 1

AN 1

Input

Analog input channel 1

Analog input 2

AN 2

Input

Analog input channel 2

Analog input 3

AN 3

Input

Analog input channel 3

Analog input 4

AN 4

Input

Analog input channel 4

Analog input 5

AN 5

Input

Analog input channel 5

Analog input 6

AN 6

Input

Analog input channel 6

Analog input 7

AN 7

Input

Analog input channel 7

External trigger input

ADTRG

Input

External trigger input for starting A/D conversion

12.1.4

Register Configuration

Table 12.2 shows the A/D converter register configuration.

Table 12.2 Register Configuration
Name

Abbrev.

R/W

Initial Value

Address

A/D mode register

AMR

R/W

H'30

H'FFC4

A/D start register

ADSR

R/W

H'7F

H'FFC6

A/D result register

ADRR

Not fixed

H'FFC5

353

12.2

Register Descriptions

12.2.1

A/D Result Register (ADRR)

Bit
Initial value
Read/Write

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R

The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2

A/D Mode Register (AMR)

Bit

CKS

TRGE

CH3

CH2

CH1

CH0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Bit 7Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7: CKS

Conversion Period

= 2 MHz

= 5 MHz

= 8 MHz*1

62/ (initial value)

31 s

12.4 s

7.75 s

31/

15.5 s

Notes: 1. F-ZTAT version only.

2. Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a
value of at least 12.4 s.
354

Bit 6External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by
external trigger input.
Bit 6: TRGE

Description

Disables start of A/D conversion by external trigger

Enables start of A/D conversion by rising or falling edge of external trigger at

pin ADTRG*

(initial value)

Note: * The external trigger ( ADTRG) edge is selected by bit INTEG5 of IEGR2. See 3.3.2 Interrupt
Edge Select Register 2 (IEGR2) for details.

Bits 5 and 4Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be
modified.
Bits 3 to 0Channel Select (CH3 to CH0): Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3:
CH3

Bit 2:
CH2

Bit 1:
CH1

Bit 0:
CH0

Analog Input Channel

No channel selected

AN 0

AN 1

AN 2

AN 3

AN 4

AN 5

AN 6

AN 7

Reserved

Reserved

Reserved

Reserved

(initial value)

Note: * Dont care

355

12.2.3

A/D Start Register (ADSR)

Bit

ADSF

Initial value

Read/Write

R/W

The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared
to 0.
Bit 7A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7: ADSF

Description

Read: Indicates the completion of A/D conversion

(initial value)

Write: Stops A/D conversion

1

Read: Indicates A/D conversion in progress

Write: Starts A/D conversion

Bits 6 to 0Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be
modified.

356

12.3

Operation

12.3.1

A/D Conversion Operation

The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2

Start of A/D Conversion by External Trigger Input

The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit TRGE in AMR is set to 1. Then when
the input signal edge designated in bit INTEG5 of interrupt edge select register 2 (IEGR2) is
detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion.
Figure 12.2 shows the timing.

Pin ADTRG
(when bit
INTEG5 = 0)
ADSF

A/D conversion

Figure 12.2 External Trigger Input Timing

357

12.4

Interrupts

When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 2 (IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5

Typical Use

An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.

358

Figure 12.3 Typical A/D Converter Operation Timing

Interrupt
(IRRAD)
Set *
IENAD

ADSF

Channel 1 (AN 1)
operation state

A/D conversion starts

Idle

Set *

A/D conversion (1)

Set *

Idle

A/D conversion (2)

Read conversion result

ADRR
Note: * ( ) indicates instruction execution by software.

A/D conversion result (1)

Idle

Read conversion result

A/D conversion result (2)

Conversion result is reset when next conversion starts

359

Start

Set A/D conversion speed

and input channel

Disable A/D conversion

end interrupt

Start A/D conversion

Read ADSR

No
ADSF = 0?
Yes
Read ADRR data

Yes

Perform A/D
conversion?
No
End

Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)

360

Start

Set A/D conversion speed

and input channels

Enable A/D conversion

end interrupt

Start A/D conversion

A/D conversion
end interrupt?
No

Yes

Clear bit IRRAD to

0 in IRR2

Read ADRR data

Yes

Perform A/D
conversion?
No
End

Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used)

12.6

Application Notes

Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in
the A/D start register (ADSR) is cleared to 0.
Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.

361

Section 13 Electrical Characteristics

13.1

Absolute Maximum Ratings

Table 13.1 lists the absolute maximum ratings.

Table 13.1 Absolute Maximum Ratings*1
Item

Symbol

Value

Unit

Power supply voltage

VCC

0.3 to +7.0

Analog power supply voltage

AVCC

0.3 to +7.0

Programming
voltage

VPP

Input voltage

0.3 to +13.0

HD64F3644, HD64F3643, FV PP
HD64F3642A

HD6473644

0.3 to +13.0

Ports other than Port B

0.3 to VCC +0.3

Port B

0.3 to AVCC +0.3

TEST (HD64F3644,
HD64F3643,HD64F3642A)

0.3 to +13.0

Vin

Operating temperature

Topr

20 to +75

Storage temperature

Tstg

55 to +125

Note

Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. The voltage at the FVPP and TEST pins should not exceed 13 V, including peak
overshoot.

363

13.2

Electrical Characteristics (ZTAT, Mask ROM Version)

13.2.1

Power Supply Voltage and Operating Range

The power supply voltage and operating range are indicated by the shaded region in the figures
below.
1. Power supply voltage vs. oscillator frequency range

32.768

fw (kHz)

f OSC (MHz)

10.0

5.0

2.0

2.7 *

4.0

Active mode (high speed)

Sleep mode (high speed)

5.5
VCC (V)

2.7 *

4.0

5.5
VCC (V)

All operating modes

Note: * 2.5 V for the HD6433644, HD6433643, HD6433642, HD6433641 and HD6433640.

364

2. Power supply voltage vs. clock frequency range

16.384
SUB (kHz)

2.5

8.192
4.096

0.5
2.7 *

4.0

2.7 *

5.5
VCC (V)

Active (high speed) mode

Sleep (high speed) mode (except CPU)

4.0

5.5
VCC (V)

Subactive mode
Subsleep mode (except CPU)
Watch mode (except CPU)

625.00
(kHz)

(MHz)

5.0

39.062

7.812

2.7*

4.0

5.5
VCC (V)

Active (medium speed) mode

Sleep (medium speed) mode (except CPU)

Note: * 2.5 V for the HD6433644, HD6433643, HD6433642, HD6433641 and HD6433640.
365

3. Analog power supply voltage vs. A/D converter guaranteed accuracy range

(MHz)

5.0

Do not exceed the maximum

conversion time value.

2.5

0.5
2.7*

4.0 4.5

Active (high speed) mode

Sleep (high speed) mode

5.5
AVCC (V)
Active (medium speed) mode
Sleep (medium speed) mode

Note: * The voltage for guaranteed A/D conversion operation is 2.5 (V).

366

13.2.2

DC Characteristics (HD6473644)

Table 13.2 lists the DC characteristics of the HD6473644.

Table 13.2 DC Characteristics
VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input high
voltage

VIH

Typ

Max

Unit

RES,
0.8 V CC
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.9 V CC
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

VCC + 0.3

VCC + 0.3

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

0.7 V CC

VCC + 0.3

0.8 V CC

VCC + 0.3

PB 0 to PB7

0.7 V CC

AV CC + 0.3 V

0.8 V CC

AV CC + 0.3

OSC1

Min

VCC 0.5

VCC + 0.3

VCC 0.3

VCC + 0.3

Test Condition

Notes

VCC = 2.7 V to 5.5 V

including subactive
mode

VCC = 2.7 V to 5.5 V

including subactive
mode

VCC = 2.7 V to 5.5 V

including subactive
mode
V
VCC = 2.7 V to 5.5 V
including subactive
mode

Note: Connect the TEST pin to VSS .

367

Table 13.2 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input low
voltage

VIL

368

Min

Typ

Max

Unit

RES,
0.3
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.3
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

0.2 V CC

0.1 V CC

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94,
PB 0 to PB7

0.3

0.3 V CC

0.3

0.2 V CC

OSC1

0.3

0.5

0.3

0.3

Test Condition

VCC = 2.7 V to 5.5 V

including subactive
mode

VCC = 2.7 V to 5.5 V

including subactive
mode

V
VCC = 2.7 V to 5.5 V
including subactive
mode

Notes

Table 13.2 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Output
high
voltage

VOH

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

Output
low
voltage

Input/
output
leakage
current

VOL

| I IL |

Typ

Max

Unit

Test Condition

VCC 1.0

I OH = 1.5 mA

VCC 0.5

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P73 to P77,
P80 to P87,
P90 to P94

0.6

0.4

P60 to P67

1.0

0.4

IOL = 1.6 mA

0.4

VCC = 2.7 V to 5.5 V

IOL = 0.4 mA

OSC1, P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

1.0

Vin = 0.5 V to
(VCC 0.5 V)

PB 0 to PB7

1.0

Vin = 0.5 V to
(AVCC 0.5 V)

Notes

VCC = 2.7 V to 5.5 V

I OH = 0.1 mA

IOL = 1.6 mA

VCC = 2.7 V to 5.5 V

IOL = 0.4 mA

IOL = 10.0 mA

Input
leakage
current

| I IL |

RES, IRQ0

20

Vin = 0.5 V to
(VCC 0.5 V)

Pull-up
MOS
current

I p

P10, P14 to P17,

P30 to P32,
P50 to P57

50

300

VCC = 5 V,
Vin = 0 V

25

VCC = 2.7 V,
Vin = 0 V

Reference
value

369

Table 13.2 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Input
capacitance

Cin

All input pins

except RES

15.0

pF

RES

60.0

f = 1 MHz,
Vin = 0 V,
Ta = 25C

IRQ0

30.0

VCC

10

15

mA

Active (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 10 MHz

10

20

10

Active
IOPE1
mode
current
dissipation

IOPE2

Sleep
ISLEEP1
mode
current
dissipation

ISLEEP2

Subactive ISUB
mode
current
dissipation

370

VCC

VCC

VCC

VCC

mA

mA

mA

Notes

VCC = 2.7 V,
fOSC = 10 MHz

1, 2
Reference
value

Active (mediumspeed) mode

VCC = 5 V,
fOSC = 10 MHz

1, 2

VCC = 2.7 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 10 MHz
VCC = 2.7 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (mediumspeed) mode

VCC = 5 V,
fOSC = 10 MHz

1, 2

VCC = 2.7 V,
fOSC = 10 MHz

1, 2
Reference
value

VCC = 2.7 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

VCC = 2.7 V
32-kHz crystal
oscillator
( SUB = W/8)

1, 2
Reference
value

Table 13.2 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Notes

Subsleep ISUBSP
mode
current
dissipation

VCC

10

VCC = 2.7 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

Watch
IWATCH
mode
current
dissipation

VCC

VCC = 2.7 V
32-kHz crystal
oscillator

1, 2

Standby
ISTBY
mode
current
dissipation

VCC

32-kHz crystal
oscillator not used

1, 2

RAM data
retaining
voltage

VCC

VRAM

Notes: 1. Pin states during current measurement are given below.

Mode

RES Pin

Internal State

Other Pins

Oscillator Pins

Active (high-speed)
mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Active (medium-speed)
mode
Sleep (high-speed)
mode

Operates
( OSC/128)
VCC

Sleep (medium-speed)
mode

Only timers operate

Subclock oscillator:
Pin X1 = VCC
VCC

Only timers operate

( OSC/128)

Subactive mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Subsleep mode

VCC

Only timers operate,

CPU stops

VCC

Subclock oscillator:
crystal

Watch mode

VCC

Only time base

operates, CPU stops

VCC

Standby mode

VCC

CPU and timers

both stop

VCC

System clock oscillator:

ceramic or crystal
Subclock oscillator:
Pin X1 = VCC

2. Excludes current in pull-up MOS transistors and output buffers.

371

Table 13.2 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise indicated.
Values
Item
Allowable output low
current (per pin)

Output pins except

port 6

Symbol

Min

Typ

Max

Unit

IOL

mA

10

40

80

Port 6
Allowable output low
current (total)

Output pins except

port 6

IOL

Port 6

mA

Allowable output high

current (per pin)

All output pins

I OH

mA

Allowable output high

current (total)

All output pins

(IOH)

30

mA

372

13.2.3

AC Characteristics (HD6473644)

Table 13.3 lists the control signal timing, and tables 13.4 and 13.5 list the serial interface timing of
the HD6473644.
Table 13.3 Control Signal Timing
VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

System clock
oscillation frequency

fOSC

OSC1, OSC2 2

OSC clock ( OSC)

cycle time

tOSC

OSC1, OSC2 100

System clock ()
cycle time

tcyc

Subclock oscillation
frequency

fW

Watch clock (W )
cycle time

tW

Subclock (SUB)
cycle time

tsubcyc

trc

Oscillation
stabilization time
(ceramic oscillator)

trc

Max

Unit

Test Condition

10

MHz

VCC = 2.7 V to 5.5 V

Reference
Figure

1000 ns

VCC = 2.7 V to 5.5 V *1

Figure 13.1
VCC = 2.7 V to 5.5 V *1

128

tOSC

25.6

X1, X2

32.768

kHz

VCC = 2.7 V to 5.5 V

X1, X2

30.5

VCC = 2.7 V to 5.5 V

tW

VCC = 2.7 V to 5.5 V *2

tcyc
VCC = 2.7 V to 5.5 V
tsubcyc

OSC1, OSC2

40

ms

60

OSC1, OSC2

20

40

Instruction cycle
time
Oscillation
stabilization time
(crystal oscillator)

Min Typ

VCC = 2.7 V to 5.5 V

ms
VCC = 2.7 V to 5.5 V

Oscillation stabilization trc

time

X1, X2

VCC = 2.7 V to 5.5 V

External clock high

width

tCPH

OSC1

40

ns

VCC = 2.7 V to 5.5 V Figure 13.1

External clock low

width

tCPL

OSC1

40

ns

VCC = 2.7 V to 5.5 V

External clock rise

time

tCPr

15

ns

VCC = 2.7 V to 5.5 V

External clock fall

time

tCPf

15

ns

VCC = 2.7 V to 5.5 V

Pin RES low width

tREL

10

tcyc

VCC = 2.7 V to 5.5 V Figure 13.2

RES

Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
373

Table 13.3 Control Signal Timing (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Applicable
Pins

Values

Item

Symbol

Input pin high width

tIH

IRQ0 to IRQ3, 2
INT0 to INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

Input pin low width

tIL

IRQ0 to IRQ3, 2
INT6, INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

374

Min Typ

Max

Unit

Test Condition

tcyc
tsubcyc

tcyc
VCC = 2.7 V to 5.5 V
tsubcyc

Reference
Figure
Figure 13.3

Table 13.4 Serial Interface (SCI1) Timing

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

Input serial clock

cycle time

tScyc

SCK1

tcyc

VCC = 2.7 V to 5.5 V Figure 13.4

Input serial clock

high width

tSCKH

SCK1

0.4

tScyc

VCC = 2.7 V to 5.5 V

Input serial clock

low width

tSCKL

SCK1

0.4

tScyc

VCC = 2.7 V to 5.5 V

Input serial clock

rise time

tSCKr

SCK1

60

ns

80

Input serial clock

fall time

tSCKf

SCK1

60

80

Serial output data

delay time

tSOD

SO 1

200

350

Serial input data

setup time

tSIS

SI 1

180

360

Serial input data

hold time

tSIH

SI 1

180

360

Min

Typ

Max

Unit

Test Condition

Reference
Figure

VCC = 2.7 V to 5.5 V

ns
VCC = 2.7 V to 5.5 V
ns
VCC = 2.7 V to 5.5 V
ns
VCC = 2.7 V to 5.5 V
ns
VCC = 2.7 V to 5.5 V

Table 13.5 Serial Interface (SCI3) Timing

VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise
specified.
Values
Item

Typ

Max

Unit

tScyc

tcyc

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Transmit data delay time

(synchronous)

tTXD

tcyc

VCC = 4.0 V to 5.5 V Figure 13.6

Receive data setup time

(synchronous)

tRXS

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Receive data hold time

(synchronous)

tRXH

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Input clock
cycle

Asynchronous
Synchronous

Test Condition

Reference
Figure

Symbol Min

Figure 13.5

375

13.2.4

DC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641,

HD6433640)

Table 13.6 lists the DC characteristics of the HD6433644, the HD6433643, the HD6433642, the
HD6433641 and the HD6433640.
Table 13.6 DC Characteristics
VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input high
voltage

VIH

Typ

Max

Unit

RES,
0.8 V CC
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.9 V CC
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

VCC + 0.3

VCC + 0.3

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

0.7 V CC

VCC + 0.3

0.8 V CC

VCC + 0.3

PB 0 to PB7

0.7 V CC

AV CC + 0.3 V

0.8 V CC

AV CC + 0.3

OSC1

Note: Connect the TEST pin to VSS .

376

Min

VCC 0.5

VCC + 0.3

VCC 0.3

VCC + 0.3

Test Condition

VCC = 2.5 V to 5.5 V

including subactive
mode

VCC = 2.5 V to 5.5 V

including subactive
mode

VCC = 2.5 V to 5.5 V

including subactive
mode
V
VCC = 2.5 V to 5.5 V
including subactive
mode

Notes

Table 13.6 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input low
voltage

VIL

Min

Typ

Max

Unit

RES,
0.3
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.3
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

0.2 V CC

0.1 V CC

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94,
PB 0 to PB7

0.3

0.3 V CC

0.3

0.2 V CC

OSC1

0.3

0.5

0.3

0.3

Test Condition

Notes

VCC = 2.5 V to 5.5 V

including subactive
mode

VCC = 2.5 V to 5.5 V

including subactive
mode

V
VCC = 2.5 V to 5.5 V
including subactive
mode

377

Table 13.6 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Output
high
voltage

VOH

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

Output
low
voltage

Input/
output
leakage
current

VOL

| I IL |

Typ

Max

Unit

Test Condition

VCC 1.0

I OH = 1.5 mA

VCC 0.5

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P73 to P77,
P80 to P87,
P90 to P94

0.6

0.4

P60 to P67

1.0

0.4

IOL = 1.6 mA

0.4

VCC = 2.5 V to 5.5 V

IOL = 0.4 mA

OSC1, P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P90 to P94

1.0

Vin = 0.5 V to
(VCC 0.5 V)

PB 0 to PB7

1.0

Vin = 0.5 V to
(AVCC 0.5 V)

VCC = 2.5 V to 5.5 V

I OH = 0.1 mA

IOL = 1.6 mA

VCC = 2.5 V to 5.5 V

IOL = 0.4 mA

IOL = 10.0 mA

Input
leakage
current

| I IL |

RES, IRQ0

Vin = 0.5 V to
(VCC 0.5 V)

Pull-up
MOS
current

I p

P10, P14 to P17,

P30 to P32,
P50 to P57

50

300

VCC = 5 V,
Vin = 0 V

25

378

Notes

VCC = 2.7 V,
Vin = 0 V

Reference
value

Table 13.6 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Input
capacitance

Cin

All input pins

except RES

15.0

pF

RES

15.0

f = 1 MHz,
Vin = 0 V,
Ta = 25C

IRQ0

15.0

VCC

10

15

mA

Active (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 10 MHz

10

20

10

Active
IOPE1
mode
current
dissipation

IOPE2

Sleep
ISLEEP1
mode
current
dissipation

ISLEEP2

Subactive ISUB
mode
current
dissipation

VCC

VCC

VCC

VCC

mA

mA

mA

Notes

VCC = 2.5 V,
fOSC = 10 MHz

1, 2
Reference
value

Active (mediumspeed) mode

VCC = 5 V,
fOSC = 10 MHz

1, 2

VCC = 2.5 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 10 MHz
VCC = 2.5 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (mediumspeed) mode

VCC = 5 V,
fOSC = 10 MHz

1, 2

VCC = 2.5 V,
fOSC = 10 MHz

1, 2
Reference
value

VCC = 2.5 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

VCC = 2.5 V
32-kHz crystal
oscillator
( SUB = W/8)

1, 2
Reference
value

379

Table 13.6 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Notes

Subsleep ISUBSP
mode
current
dissipation

VCC

10

VCC = 2.5 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

Watch
IWATCH
mode
current
dissipation

VCC

VCC = 2.5 V
32-kHz crystal
oscillator

1, 2

Standby
ISTBY
mode
current
dissipation

VCC

32-kHz crystal
oscillator not used

1, 2

RAM data
retaining
voltage

VCC

VRAM

Notes: 1. Pin states during current measurement are given below.

Mode

RES Pin

Internal State

Other Pins

Oscillator Pins

Active (high-speed)
mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Active (medium-speed)
mode
Sleep (high-speed)
mode

Operates
( OSC/128)
VCC

Sleep (medium-speed)
mode

Only timers operate

Subclock oscillator:
Pin X1 = VCC
VCC

Only timers operate

( OSC/128)

Subactive mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Subsleep mode

VCC

Only timers operate,

CPU stops

VCC

Subclock oscillator:
crystal

Watch mode

VCC

Only time base

operates, CPU stops

VCC

Standby mode

VCC

CPU and timers

both stop

VCC

System clock oscillator:

ceramic or crystal
Subclock oscillator:
Pin X1 = VCC

2. Excludes current in pull-up MOS transistors and output buffers.

380

Table 13.6 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise indicated.
Values
Item
Allowable output low
current (per pin)

Output pins except

port 6

Symbol

Min

Typ

Max

Unit

IOL

mA

10

40

80

Port 6
Allowable output low
current (total)

Output pins except

port 6

IOL

Port 6

mA

Allowable output high

current (per pin)

All output pins

I OH

mA

Allowable output high

current (total)

All output pins

(IOH)

30

mA

13.2.5

AC Characteristics (HD6433644, HD6433643, HD6433642, HD6433641,

HD6433640)

Table 13.7 lists the control signal timing, and tables 13.8 and 13.9 list the serial interface timing of
the HD6433644, the HD6433643, the HD6433642, the HD6433641 and the HD6433640.

381

Table 13.7 Control Signal Timing

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

System clock
oscillation frequency

fOSC

OSC1, OSC2 2
2

OSC clock ( OSC)

cycle time

tOSC

System clock ()
cycle time

tcyc

Subclock oscillation
frequency

fW

Watch clock (W )
cycle time

tW

Subclock (SUB)
cycle time

tsubcyc

trc

Oscillation
stabilization time
(ceramic oscillator)

trc

Max

Unit

10

MHz

OSC1, OSC2 100

Test Condition

Reference
Figure

VCC = 2.5 V to 5.5 V

1000 ns

*1

200

1000

128

tOSC

25.6

X1, X2

32.768

kHz

VCC = 2.5 V to 5.5 V

X1, X2

30.5

VCC = 2.5 V to 5.5 V

tW

VCC = 2.5 V to 5.5 V *2

tcyc
VCC = 2.5 V to 5.5 V
tsubcyc

OSC1, OSC2

40

ms

60

OSC1, OSC2

20

40

Instruction cycle
time
Oscillation
stabilization time
(crystal oscillator)

Min Typ

VCC = 2.5 V to 5.5 V Figure 13.1

VCC = 2.5 V to 5.5 V

ms
VCC = 2.5 V to 5.5 V

Oscillation stabilization trc

time

X1, X2

External clock high

width

tCPH

OSC1

40

ns

80

External clock low

width

tCPL

40

80

External clock rise

time

tCPr

15

20

External clock fall

time

tCPf

15

Pin RES low width

tREL

OSC1

RES

20

10

VCC = 2.5 V to 5.5 V *1

VCC = 2.5 V to 5.5 V

Figure 13.1
VCC = 2.5 V to 5.5 V

ns
VCC = 2.5 V to 5.5 V
ns
VCC = 2.5 V to 5.5 V
ns
VCC = 2.5 V to 5.5 V
tcyc

VCC = 2.5 V to 5.5 V Figure 13.2

Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).

382

Table 13.7 Control Signal Timing (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Applicable
Pins

Values

Item

Symbol

Min Typ

Input pin high width

tIH

IRQ0 to IRQ3, 2
INT0 to INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

Input pin low width

tIL

IRQ0 to IRQ3, 2
INT6, INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

Test Condition

Reference
Figure

Max

Unit

tcyc
VCC = 2.5 V to 5.5 V Figure 13.3
tsubcyc

tcyc
VCC = 2.5 V to 5.5 V
tsubcyc

383

Table 13.8 Serial Interface (SCI1) Timing

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

Input serial clock

cycle time

tScyc

SCK1

tcyc

VCC = 2.5 V to 5.5 V Figure 13.4

Input serial clock

high width

tSCKH

SCK1

0.4

tScyc

VCC = 2.5 V to 5.5 V

Input serial clock

low width

tSCKL

SCK1

0.4

tScyc

VCC = 2.5 V to 5.5 V

Input serial clock

rise time

tSCKr

SCK1

60

ns

80

Input serial clock

fall time

tSCKf

SCK1

60

80

Serial output data

delay time

tSOD

SO 1

200

350

Serial input data

setup time

tSIS

SI 1

180

360

Serial input data

hold time

tSIH

SI 1

180

360

Min

Typ

Max

Unit

Test Condition

Reference
Figure

VCC = 2.5 V to 5.5 V

ns
VCC = 2.5 V to 5.5 V
ns
VCC = 2.5 V to 5.5 V
ns
VCC = 2.5 V to 5.5 V
ns
VCC = 2.5 V to 5.5 V

Table 13.9 Serial Interface (SCI3) Timing

VCC = 2.7 V to 5.5 V, AVCC = 2.5 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise
specified.
Values
Item

Typ

Max

Unit

tScyc

tcyc

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Transmit data delay time

(synchronous)

tTXD

tcyc

VCC = 4.0 V to 5.5 V Figure 13.6

Receive data setup time

(synchronous)

tRXS

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Receive data hold time

(synchronous)

tRXH

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Input clock
cycle

384

Asynchronous
Synchronous

Test Condition

Reference
Figure

Symbol Min

Figure 13.5

13.2.6

A/D Converter Characteristics

Table 13.10 shows the A/D converter characteristics of the HD6473644, the HD6433644, the
HD6433643, the HD6433642, the HD6433641 and the HD6433640.
Table 13.10 A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

Analog power
supply voltage

AV CC

AV CC

2.7

Analog input
voltage

AV in

AN0 to AN7

AV SS 0.3

AV CC + 0.3 V

Analog power
supply current

AI OPE

AV CC

1.5

mA

AI STOP1

AV CC

150

*2
Reference
value

AI STOP2

AV CC

*3

Analog input
capacitance

CAin

AN0 to AN7

30

pF

Allowable
signal source
impedance

RAin

5.0

Resolution

bit

Nonlinearity
error

2.0

LSB

Quantization
error

0.5

LSB

Absolute
accuracy

2.5

LSB

Conversion
time

12.4

124

Min

Typ

Max

Unit

5.5

Test Condition

Reference
Figure
*1

AV CC = 5 V

Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.

385

13.3

Electrical Characteristics (F-ZTAT Version)

13.3.1

Power Supply Voltage and Operating Range

The power supply voltage and operating range are indicated by the shaded region in the figures
below.
1. Power supply voltage vs. oscillator frequency range
32.768

10.0

fw (kHz)

f OSC (MHz)

16.0

2.0

3.0

4.0

Active mode (high speed)

Sleep mode (high speed)

386

5.5
VCC (V)

3.0

4.0

All operating modes

5.5
VCC (V)

2. Power supply voltage vs. clock frequency range

SUB (kHz)

5.0

16.384

8.192
4.096

0.5
3.0

4.0

5.5
VCC (V)

3.0

Active (high speed) mode

Sleep (high speed) mode (except CPU)

4.0

5.5
VCC (V)

Subactive mode
Subsleep mode (except CPU)
Watch mode (except CPU)

1000.00
625.00

(kHz)

(MHz)

8.0

39.062

7.812

3.0

4.0

5.5
VCC (V)

Active (medium speed) mode

Sleep (medium speed) mode (except CPU)

387

3. Analog power supply voltage vs. A/D converter operating range

(MHz)

8.0

Do not exceed the maximum

conversion time value.

5.0

0.5
3.0

4.0

Active (high speed) mode

Sleep (high speed) mode

388

5.5
AVCC (V)
Active (medium speed) mode
Sleep (medium speed) mode

13.3.2

DC Characteristics (HD64F3644, HD64F3643, HD64F3642A)

Table 13.11 lists the DC characteristics of the HD64F3644, HD64F3643, and HD64F3642A.
Table 13.11 DC Characteristics
VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input high
voltage

VIH

Typ

Max

Unit

RES,
0.8 V CC
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.9 V CC
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

VCC + 0.3

VCC + 0.3

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P91 to P94

0.7 V CC

VCC + 0.3

0.8 V CC

VCC + 0.3

PB 0 to PB7

0.7 V CC

AV CC + 0.3 V

0.8 V CC

AV CC + 0.3

OSC1

Min

VCC 0.5

VCC + 0.3

VCC 0.3

VCC + 0.3

Test Condition

Notes

VCC = 3.0 V to 5.5 V

including subactive
mode

VCC = 3.0 V to 5.5 V

including subactive
mode

VCC = 3.0 V to 5.5 V

including subactive
mode
V
VCC = 3.0 V to 5.5 V
including subactive
mode

Note: Except in boot mode, connect the TEST pin to VSS.

389

Table 13.11 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Input low
voltage

VIL

390

Min

Typ

Max

Unit

RES,
0.3
INT0 to INT7,
IRQ0 to IRQ3,
ADTRG, TMIB,
TMRIV, TMCIV,
0.3
FTCI, FTIA,
FTIB, FTIC, FTID,
SCK1, SCK3,
TRGV

0.2 V CC

0.1 V CC

SI 1, RXD,
P10, P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P91 to P94,
PB 0 to PB7

0.3

0.3 V CC

0.3

0.2 V CC

OSC1

0.3

0.5

0.3

0.3

Test Condition

VCC = 3.0 V to 5.5 V

including subactive
mode

VCC = 3.0 V to 5.5 V

including subactive
mode

V
VCC = 3.0 V to 5.5 V
including subactive
mode

Notes

Table 13.11 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Output
high
voltage

VOH

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P91 to P94

Output
low
voltage

Input/
output
leakage
current

VOL

| I IL |

Typ

Max

Unit

Test Condition

VCC 1.0

I OH = 1.5 mA

VCC 0.5

P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P73 to P77,
P80 to P87,
P91 to P94

0.6

0.4

P60 to P67

1.0

0.4

IOL = 1.6 mA

0.4

VCC = 2.7 V to 5.5 V

IOL = 0.4 mA

OSC1, RES,
P10,
P14 to P17,
P20 to P22,
P30 to P32,
P50 to P57,
P60 to P67,
P73 to P77,
P80 to P87,
P91 to P94

1.0

Vin = 0.5 V to
(VCC 0.5 V)

PB 0 to PB7

1.0

Vin = 0.5 V to
(AVCC 0.5 V)

Notes

VCC = 3.0 V to 5.5 V

I OH = 0.1 mA

IOL = 1.6 mA

VCC = 3.0 V to 5.5 V

IOL = 0.4 mA

IOL = 10.0 mA

Input
leakage
current

| I IL |

IRQ0, TEST

20

Vin = 0.5 V to
(VCC 0.5 V)

Pull-up
MOS
current

I p

P10, P14 to P17,

P30 to P32,
P50 to P57

50

300

VCC = 5 V,
Vin = 0 V

35

VCC = 3.0 V,
Vin = 0 V

Reference
value

391

Table 13.11 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Input
capacitance

Cin

All input pins

except TEST

15.0

pF

IRQ0, TEST

30.0

f = 1 MHz,
Vin = 0 V,
Ta = 25C

VCC

15

25

mA

Active (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 16 MHz

8.5

10

3.5

Active
IOPE1
mode
current
dissipation

IOPE2

Sleep
ISLEEP1
mode
current
dissipation

ISLEEP2

Subactive ISUB
mode
current
dissipation

392

VCC

VCC

VCC

VCC

mA

mA

Notes

VCC = 3.0 V,
fOSC = 10 MHz

1, 2
Reference
value

Active (mediumspeed) mode

VCC = 5 V,
fOSC = 16 MHz

1, 2

VCC = 3.0 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (high-speed) 1, 2
mode
VCC = 5 V,
fOSC = 16 MHz
VCC = 3.0 V,
fOSC = 10 MHz

1, 2
Reference
value

Sleep (mediumspeed) mode

VCC = 5 V,
fOSC = 16 MHz

1, 2

VCC = 3.0 V,
fOSC = 10 MHz

1, 2
Reference
value

mA

VCC = 3.0 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

mA

VCC = 3.0 V
32-kHz crystal
oscillator
( SUB = W/8)

1, 2
Reference
value

mA

Table 13.11 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C unless otherwise indicated.
Values
Item

Symbol

Applicable Pins

Min

Typ

Max

Unit

Test Condition

Notes

Subsleep ISUBSP
mode
current
dissipation

VCC

10

VCC = 3.0 V
32-kHz crystal
oscillator
( SUB = W/2)

1, 2

Watch
IWATCH
mode
current
dissipation

VCC

VCC = 3.0 V
32-kHz crystal
oscillator

1, 2

Standby
ISTBY
mode
current
dissipation

VCC

32-kHz crystal
oscillator not used

1, 2

RAM data
retaining
voltage

VCC

VRAM

Notes: 1. Pin states during current measurement are given below.

Mode

RES Pin

Internal State

Other Pins

Oscillator Pins

Active (high-speed)
mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Active (medium-speed)
mode
Sleep (high-speed)
mode

Operates
( OSC/128)
VCC

Sleep (medium-speed)
mode

Only timers operate

Subclock oscillator:
Pin X1 = VCC
VCC

Only timers operate

( OSC/128)

Subactive mode

VCC

Operates

VCC

System clock oscillator:

ceramic or crystal

Subsleep mode

VCC

Only timers operate,

CPU stops

VCC

Subclock oscillator:
crystal

Watch mode

VCC

Only time base

operates, CPU stops

VCC

Standby mode

VCC

CPU and timers

both stop

VCC

System clock oscillator:

ceramic or crystal
Subclock oscillator:
Pin X1 = VCC

2. Excludes current in pull-up MOS transistors and output buffers.

393

Table 13.11 DC Characteristics (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise indicated.
Values
Item
Allowable output low
current (per pin)

Output pins except

port 6

Symbol

Min

Typ

Max

Unit

IOL

mA

10

40

80

Port 6
Allowable output low
current (total)

Output pins except

port 6

IOL

Port 6

mA

Allowable output high

current (per pin)

All output pins

I OH

mA

Allowable output high

current (total)

All output pins

(IOH)

30

mA

394

13.3.3

AC Characteristics (HD64F3644, HD64F3643, HD64F3642A)

Table 13.12 lists the control signal timing, and tables 13.13 and 13.14 list the serial interface
timing of the HD64F3644, HD64F3643, and HD64F3642A.
Table 13.12 Control Signal Timing
VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

System clock
oscillation frequency

fOSC

OSC1, OSC2 2

OSC clock ( OSC)

cycle time

tOSC

OSC1, OSC2 62.5

System clock ()
cycle time

tcyc

Subclock oscillation
frequency

fW

X1, X2

Watch clock (W )
cycle time

tW

X1, X2

Subclock (SUB)
cycle time

tsubcyc

trc

Oscillation
stabilization time
(ceramic oscillator)

trc

Max

Unit

16

MHz

Test Condition

Reference
Figure

10

VCC = 3.0 V to 5.5 V

1000 ns

*1
Figure
13.1
VCC = 3.0 V to 5.5 V

100

1000

128

25.6

32.768

kHz

VCC = 3.0 V to 5.5 V

30.5

VCC = 3.0 V to 5.5 V

tW

VCC = 3.0 V to 5.5 V *2

tcyc
VCC = 3.0 V to 5.5 V
tsubcyc

OSC1, OSC2

40

ms

60

OSC1, OSC2

20

40

Instruction cycle
time
Oscillation
stabilization time
(crystal oscillator)

Min Typ

tOSC

VCC = 3.0 V to 5.5 V *1

VCC = 3.0 V to 5.5 V

ms
VCC = 3.0 V to 5.5 V

Oscillation stabilization trc

time

X1, X2

External clock high

width

tCPH

OSC1

20

ns

40

External clock low

width

tCPL

20

40

External clock rise

time

tCPr

15

ns

VCC = 3.0 V to 5.5 V

External clock fall

time

tCPf

15

ns

VCC = 3.0 V to 5.5 V

OSC1

VCC = 3.0 V to 5.5 V

Figure 13.1
VCC = 3.0 V to 5.5 V

ns
VCC = 3.0 V to 5.5 V

Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
395

Table 13.12 Control Signal Timing (cont)

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Symbol

Applicable
Pins

Min Typ

Max

Unit

Test Condition

Pin RES low width

tREL

RES

10

tcyc

VCC = 3.0 V to 5.5 V Figure 13.2

Input pin high level

width

tIH

IRQ0 to IRQ3, 2
INT0 to INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

tcyc
VCC = 3.0 V to 5.5 V Figure 13.3
tsubcyc

Input pin low level

width

tIL

IRQ0 to IRQ3, 2
INT6, INT7,
ADTRG,
TMIB,
TMCIV,
TMRIV, FTCI,
FTIA, FTIB,
FTIC, FTID,
TRGV

tcyc
VCC = 3.0 V to 5.5 V
tsubcyc

Item

396

Reference
Figure

Table 13.13 Serial Interface (SCI1) Timing

VCC = 4.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

Input serial clock

cycle time

tScyc

SCK1

tcyc

VCC = 3.0 V to 5.5 V Figure 13.4

Input serial clock

high width

tSCKH

SCK1

0.4

tScyc

VCC = 3.0 V to 5.5 V

Input serial clock

low width

tSCKL

SCK1

0.4

tScyc

VCC = 3.0 V to 5.5 V

Input serial clock

rise time

tSCKr

SCK1

60

ns

80

Input serial clock

fall time

tSCKf

SCK1

60

80

Serial output data

delay time

tSOD

SO 1

200

350

Serial input data

setup time

tSIS

SI 1

180

360

Serial input data

hold time

tSIH

SI 1

180

360

Min

Typ

Max

Unit

Test Condition

Reference
Figure

VCC = 3.0 V to 5.5 V

ns
VCC = 3.0 V to 5.5 V
ns
VCC = 3.0 V to 5.5 V
ns
VCC = 3.0 V to 5.5 V
ns
VCC = 3.0 V to 5.5 V

Table 13.14 Serial Interface (SCI3) Timing

VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = 20C to +75C, unless otherwise
specified.
Values
Item

Typ

Max

Unit

tScyc

tcyc

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Transmit data delay time

(synchronous)

tTXD

tcyc

VCC = 4.0 V to 5.5 V Figure 13.6

Receive data setup time

(synchronous)

tRXS

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Receive data hold time

(synchronous)

tRXH

200.0

ns

VCC = 4.0 V to 5.5 V

400.0

Input clock
cycle

Asynchronous
Synchronous

Test Condition

Reference
Figure

Symbol Min

Figure 13.5

397

13.3.4

A/D Converter Characteristics

Table 13.15 shows the A/D converter characteristics of the HD64F3644, HD64F3643, and
HD64F3642A.
Table 13.15 A/D Converter Characteristics
VCC = 3.0 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = 20C to +75C, unless otherwise specified.
Values

Item

Symbol

Applicable
Pins

Analog power
supply voltage

AV CC

AV CC

3.0

Analog input
voltage

AV in

AN0 to AN7

AV SS 0.3

AV SS + 0.3 V

Analog power
supply current

AI OPE

AV CC

1.5

mA

AI STOP1

AV CC

150

*2
Reference
value

AI STOP2

AV CC

5.0

*3

Analog input
capacitance

CAin

AN0 to AN7

30.0

pF

Allowable
signal source
impedance

RAin

5.0

Resolution

bit

Nonlinearity
error

2.0

LSB

Quantization
error

0.5

LSB

Absolute
accuracy

2.5

LSB

Conversion
time

7.75

124

Min

Typ

Max

Unit

5.5

Test Condition

Reference
Figure
*1

AV CC = 5.0 V

Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.

398

13.4

Operation Timing

Figures 13.1 to 13.6 show timing diagrams.

t OSC

VIH
OSC1
VIL

t CPH

t CPL

t CPr

t CPf

Figure 13.1 System Clock Input Timing

RES

VIL

tREL

Figure 13.2 RES Low Width Timing

IRQ0 to IRQ3
INT0 to INT7
ADTRG
TMIB, FTIA
FTIB
TMCIV, FTIC
FTID
TMRIV
FTCI, TRGV

VIH
VIL

t IL

t IH

Figure 13.3 Input Timing

399

t Scyc

SCK 1

V IH or V OH*
V IL or V OL *

t SCKL

t SCKH

t SCKf

t SCKr
t SOD

SO 1

VOH*
VOL *

t SIS
t SIH

SI 1

Note: * Output timing reference levels

Output high: VOH = 2.0 V
Output low: VOL = 0.8 V
Load conditions are shown in figure 13.7.

Figure 13.4 Serial Interface 1, 2 Input/Output Timing

400

t SCKW

SCK 3

t Scyc

Figure 13.5 SCK3 Input Clock Timing

t Scyc

SCK 3

VIH or VOH *
VIL or VOL *

t TXD

TXD
(transmit data)

VOH
VOL

t RXS

t RXH

RXD
(receive data)

Note: * Output timing reference levels

Output high: VOH = 2.0 V
Output low: VOL = 0.8 V
Load conditions are shown in figure 13.7.

Figure 13.6 Serial Interface 3 Synchronous Mode Input/Output Timing

401

13.5

Output Load Circuit

VCC

2.4 k

Output pin
30 pF

12 k

Figure 13.7 Output Load Condition

402

Appendix A CPU Instruction Set

A.1

Instructions

Operation Notation
Rd8/16

General register (destination) (8 or 16 bits)

Rs8/16

General register (source) (8 or 16 bits)

Rn8/16

General register (8 or 16 bits)

CCR

Condition code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

PC

Program counter

SP

Stack pointer

#xx: 3/8/16

Immediate data (3, 8, or 16 bits)

d: 8/16

Displacement (8 or 16 bits)

@aa: 8/16

Absolute address (8 or 16 bits)

Addition

Subtraction

Multiplication

Division

Logical AND

Logical OR

Exclusive logical OR

Move
Logical complement

Condition Code Notation

Symbol
Modified according to the instruction result
*

Not fixed (value not guaranteed)

Always cleared to 0

Not affected by the instruction execution result

403

Table A.1 lists the H8/300L CPU instruction set.

Instruction Set

MOV.B @Rs, Rd

B @Rs16 Rd8

MOV.B @(d:16, Rs), Rd

B @(d:16, Rs16) Rd8

MOV.B @Rs+, Rd

B @Rs16 Rd8
Rs16+1 Rs16

MOV.B @aa:8, Rd

B @aa:8 Rd8

MOV.B @aa:16, Rd

B @aa:16 Rd8

MOV.B Rs, @Rd

B Rs8 @Rd16

MOV.B Rs, @(d:16, Rd)

B Rs8 @(d:16, Rd16)

MOV.B Rs, @Rd

B Rd161 Rd16
Rs8 @Rd16

MOV.B Rs, @aa:8

B Rs8 @aa:8

MOV.B Rs, @aa:16

B Rs8 @aa:16

MOV.W #xx:16, Rd

W #xx:16 Rd

MOV.W Rs, Rd

W Rs16 Rd16

MOV.W @Rs, Rd

W @Rs16 Rd16

W @Rs16 Rd16
Rs16+2 Rs16

MOV.W @aa:16, Rd

W @aa:16 Rd16

MOV.W Rs, @Rd

W Rs16 @Rd16

MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16)

MOV.W Rs, @Rd

W Rd162 Rd16
Rs16 @Rd16

MOV.W Rs, @aa:16

W Rs16 @aa:16

POP Rd

W @SP Rd16
SP+2 SP

404

MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16

MOV.W @Rs+, Rd

No. of States

B Rs8 Rd8

H N Z V C

0 2

B #xx:8 Rd8

MOV.B Rs, Rd

0 4

MOV.B #xx:8, Rd

Condition Code

0 4

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

0 6

Table A.1

0 6

0 2
0 4
0 6
0 6

0 6
0 4
0 6
0 6

0 6
0 4
0 2
0 4
0 6
0 6

0 4
0 6
0 6

0 6

Instruction Set (cont)

ADD.W Rs, Rd

W Rd16+Rs16 Rd16

ADDX.B #xx:8, Rd

B Rd8+#xx:8 +C Rd8

No. of States

B Rd8+Rs8 Rd8

(4)

B Rd8+#xx:8 Rd8

ADD.B Rs, Rd

0 6

ADD.B #xx:8, Rd

H N Z V C

(1)

(2)

(2)

B Rd8+Rs8 +C Rd8

ADDS.W #1, Rd

W Rd16+1 Rd16

ADDS.W #2, Rd

W Rd16+2 Rd16

INC.B Rd

B Rd8+1 Rd8

DAA.B Rd

B Rd8 decimal adjust Rd8

* (3) 2

SUB.B Rs, Rd

B Rd8Rs8 Rd8

SUB.W Rs, Rd

W Rd16Rs16 Rd16

(1)

SUBX.B #xx:8, Rd

B Rd8#xx:8 C Rd8

SUBX.B Rs, Rd

B Rd8Rs8 C Rd8

SUBS.W #1, Rd

W Rd161 Rd16

SUBS.W #2, Rd

W Rd162 Rd16

DEC.B Rd

B Rd81 Rd8

DAS.B Rd

B Rd8 decimal adjust Rd8

* 2

NEG.B Rd

B 0Rd Rd

CMP.B #xx:8, Rd

B Rd8#xx:8

2
2
2

ADDX.B Rs, Rd

if R4L0 then
Repeat @R5 @R6
R5+1 R5
R6+1 R6
R4L1 R4L
Until R4L=0
else next;

EEPMOV

W SP2 SP
Rs16 @SP

PUSH Rs

Condition Code

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

Table A.1

2
2

(2)

(2)

CMP.B Rs, Rd

B Rd8Rs8

CMP.W Rs, Rd

W Rd16Rs16

(1)

MULXU.B Rs, Rd

B Rd8 Rs8 Rd16

14

405

Instruction Set (cont)

H N Z V C

B Rd16Rs8 Rd16 (RdH:

remainder, RdL: quotient)

AND.B #xx:8, Rd

B Rd8#xx:8 Rd8

AND.B Rs, Rd

B Rd8Rs8 Rd8

OR.B #xx:8, Rd

B Rd8#xx:8 Rd8

OR.B Rs, Rd

B Rd8Rs8 Rd8

XOR.B #xx:8, Rd

B Rd8#xx:8 Rd8

XOR.B Rs, Rd

B Rd8Rs8 Rd8

NOT.B Rd

B Rd Rd

SHAL.B Rd

0 2
0 2
0 2
0 2
0 2

b0

C
b0

C
b0

b0

C
b7

406

b0

C
b7

b7

ROTR.B Rd

ROTL.B Rd

0 2

b0

b7
B

0 2

b0

b7

ROTXR.B Rd

ROTXL.B Rd

2
2

b7
SHLR.B Rd

SHLL.B Rd

B
b7

(5) (6) 14

SHAR.B Rd

C
b7

No. of States

DIVXU.B Rs, Rd

Operation

Condition Code

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

Table A.1

b0

Instruction Set (cont)

BSET #xx:3, Rd

B (#xx:3 of Rd8) 1

BSET #xx:3, @Rd

B (#xx:3 of @Rd16) 1

BSET #xx:3, @aa:8

B (#xx:3 of @aa:8) 1

BSET Rn, Rd

B (Rn8 of Rd8) 1

BSET Rn, @Rd

B (Rn8 of @Rd16) 1

BSET Rn, @aa:8

B (Rn8 of @aa:8) 1

BCLR #xx:3, Rd

B (#xx:3 of Rd8) 0

BCLR #xx:3, @Rd

B (#xx:3 of @Rd16) 0

BCLR #xx:3, @aa:8

B (#xx:3 of @aa:8) 0

BCLR Rn, Rd

B (Rn8 of Rd8) 0

BCLR Rn, @Rd

B (Rn8 of @Rd16) 0

BCLR Rn, @aa:8

B (Rn8 of @aa:8) 0

BNOT #xx:3, Rd

B (#xx:3 of Rd8)
(#xx:3 of Rd8)

BNOT #xx:3, @Rd

B (#xx:3 of @Rd16)
(#xx:3 of @Rd16)

BNOT #xx:3, @aa:8

B (#xx:3 of @aa:8)
(#xx:3 of @aa:8)

BNOT Rn, Rd

B (Rn8 of Rd8)
(Rn8 of Rd8)

BNOT Rn, @Rd

B (Rn8 of @Rd16)
(Rn8 of @Rd16)

BNOT Rn, @aa:8

B (Rn8 of @aa:8)
(Rn8 of @aa:8)

BTST #xx:3, Rd

B (#xx:3 of Rd8) Z

BTST #xx:3, @Rd

B (#xx:3 of @Rd16) Z

BTST #xx:3, @aa:8

B (#xx:3 of @aa:8) Z

BTST Rn, Rd

B (Rn8 of Rd8) Z

BTST Rn, @Rd

B (Rn8 of @Rd16) Z

BTST Rn, @aa:8

B (Rn8 of @aa:8) Z

Condition Code

H N Z V C

No. of States

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

2
4

8
4

8
2

8
4

8
2

8
4

8
2

8
4

8
2

8
4

8
2

8
4

Table A.1

2
6
6
2
6
6

407

Instruction Set (cont)

BLD #xx:3, Rd

B (#xx:3 of Rd8) C

BLD #xx:3, @Rd

B (#xx:3 of @Rd16) C

BLD #xx:3, @aa:8

B (#xx:3 of @aa:8) C

BILD #xx:3, Rd

B (#xx:3 of Rd8) C

BILD #xx:3, @Rd

B (#xx:3 of @Rd16) C

BILD #xx:3, @aa:8

B (#xx:3 of @aa:8) C

BST #xx:3, Rd

B C (#xx:3 of Rd8)

BST #xx:3, @Rd

B C (#xx:3 of @Rd16)

BST #xx:3, @aa:8

B C (#xx:3 of @aa:8)

BIST #xx:3, Rd

B C (#xx:3 of Rd8)

BIST #xx:3, @Rd

B C (#xx:3 of @Rd16)

BIST #xx:3, @aa:8

B C (#xx:3 of @aa:8)

BAND #xx:3, Rd

B C(#xx:3 of Rd8) C

BAND #xx:3, @Rd

B C(#xx:3 of @Rd16) C

BAND #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BIAND #xx:3, Rd

B C(#xx:3 of Rd8) C

BIAND #xx:3, @Rd

B C(#xx:3 of @Rd16) C

BIAND #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BOR #xx:3, Rd

B C(#xx:3 of Rd8) C

BOR #xx:3, @Rd

B C(#xx:3 of @Rd16) C

BOR #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BIOR #xx:3, Rd

B C(#xx:3 of Rd8) C

BIOR #xx:3, @Rd

B C(#xx:3 of @Rd16) C

BIOR #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BXOR #xx:3, Rd

B C(#xx:3 of Rd8) C

BXOR #xx:3, @Rd

B C(#xx:3 of @Rd16) C

BXOR #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BIXOR #xx:3, Rd

B C(#xx:3 of Rd8) C

408

H N Z V C

No. of States

2
6
6
2
6
6

2
4

8
4

8
2

8
4

Condition Code

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

Table A.1

2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2

Instruction Set (cont)

BIXOR #xx:3, @Rd

Branching
Condition

B C(#xx:3 of @Rd16) C

Condition Code

H N Z V C

No. of States

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

Table A.1

BIXOR #xx:3, @aa:8

B C(#xx:3 of @aa:8) C

BRA d:8 (BT d:8)

PC PC+d:8

BRN d:8 (BF d:8)

PC PC+2

BHI d:8

CZ=0

CZ=1

C=0

C=1

Z=0

BEQ d:8

If
condition

is true
then
PC
PC+d:8
else next;

Z=1

BVC d:8

V=0

BVS d:8

V=1

BPL d:8

N=0

BMI d:8

N=1

BGE d:8

NV = 0

BLT d:8

NV = 1

BGT d:8

Z (NV) = 0

BLE d:8

Z (NV) = 1

JMP @Rn

PC Rn16

JMP @aa:16

PC aa:16

JMP @@aa:8

PC @aa:8

BSR d:8

SP2 SP
PC @SP
PC PC+d:8

JSR @Rn

SP2 SP
PC @SP
PC Rn16

JSR @aa:16

SP2 SP
PC @SP
PC aa:16

BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8

4
4

6
2
2

8
6

409

Instruction Set (cont)

SP2 SP
PC @SP
PC @aa:8

H N Z V C

PC @SP
SP+2 SP

2 8

RTE

CCR @SP
SP+2 SP
PC @SP
SP+2 SP

SLEEP

Transit to sleep mode.

LDC #xx:8, CCR

B #xx:8 CCR

LDC Rs, CCR

B Rs8 CCR

STC CCR, Rd

B CCR Rd8

ANDC #xx:8, CCR

B CCR#xx:8 CCR

ORC #xx:8, CCR

B CCR#xx:8 CCR

XORC #xx:8, CCR

B CCR#xx:8 CCR

NOP

PC PC+2

2 2

EEPMOV

if R4L0
Repeat @R5 @R6
R5+1 R5
R6+1 R6
R4L1 R4L
Until R4L=0
else next;

4 4

RTS

Condition Code

JSR @@aa:8

Operation

#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied

Mnemonic

Operand Size

Addressing Mode/
Instruction Length (Bytes)

No. of States

Table A.1

10

2 2
2

Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.

A.2

Operation Code Map

Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
410

Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.

Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.

411

412

OR

XOR

AND

MOV

Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.

BVC

SUBX

BILD

BIST
BLD

BST

BEQ

MOV

NEG

NOT

LDC

BIAND

BAND

RTE

BNE

AND

ANDC

CMP

BIXOR

BXOR

BSR

BCS

XOR

XORC

BIOR

BOR

RTS

BCC

OR

ORC

ADDX

BTST

BLS

ROTR

ROTXR

LDC

BCLR

BHI

ROTL

ROTXL

STC

ADD

BNOT

DIVXU

BRN

SHAR

SHLR

SLEEP

BSET

MULXU

BRA

SHAL

SHLL

NOP

Low

SUB

ADD

MOV

BVS

JMP

BPL

DEC

INC

CMP

MOV

BLT

JSR

BGT

SUBX

ADDX

Bit-manipulation instructions

BGE

MOV *

EEPMOV

BMI

SUBS

ADDS

# 
"#
High

BLE

DAS

DAA

Table A.2
Operation Code Map

A.3

Number of Execution States

The tables here can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table A.4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables as
follows:
Execution states = I S I + J S J + K S K + L S L + M S M + N S N

Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S I = 2, SL = 2
Number of states required for execution = 2 2 + 2 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,

L=M=N=0

From table A.3:

S I = SJ = SK = 2
Number of states required for execution = 2 2 + 1 2+ 1 2 = 8

413

Table A.3

Number of Cycles in Each Instruction

Access Location

Execution Status
(Instruction Cycle)

On-Chip Memory

On-Chip Peripheral Module

Instruction fetch

SI

Branch address read

SJ

Stack operation

SK

Byte data access

SL

2 or 3*

Word data access

SM

Internal operation

SN

Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.

414

Table A.4

Number of Cycles in Each Instruction

Instruction Mnemonic

Instruction Branch
Stack
Byte Data
Fetch
Addr. Read Operation Access
I
J
K
L

ADD

ADDS

ADDX

AND

ADD.B #xx:8, Rd
ADD.B Rs, Rd

ADD.W Rs, Rd

ADDS.W #1, Rd

ADDS.W #2, Rd

ADDX.B #xx:8, Rd

ADDX.B Rs, Rd

AND.B #xx:8, Rd

AND.B Rs, Rd

ANDC

ANDC #xx:8, CCR

BAND

BAND #xx:3, Rd

Bcc

BCLR

BAND #xx:3, @Rd

BAND #xx:3, @aa:8

BRA d:8 (BT d:8)

BRN d:8 (BF d:8)

BHI d:8

BLS d:8

BCC d:8 (BHS d:8)

BCS d:8 (BLO d:8)

BNE d:8

BEQ d:8

BVC d:8

BVS d:8

BPL d:8

BMI d:8

BGE d:8

BLT d:8

BGT d:8

BLE d:8

BCLR #xx:3, Rd

BCLR #xx:3, @Rd

BCLR #xx:3, @aa:8

BCLR Rn, Rd

Word Data Internal

Access
Operation
M
N

415

Table A.4

Number of Cycles in Each Instruction (cont)

Instruction Mnemonic

Instruction Branch
Stack
Byte Data
Fetch
Addr. Read Operation Access
I
J
K
L

BCLR

BCLR Rn, @aa:8

BIAND #xx:3, Rd

BIAND #xx:3, @Rd

BIAND #xx:3, @aa:8 2

BIAND

BILD

BIOR

BIST

BIXOR

BLD

BNOT

BOR

BSET

416

BCLR Rn, @Rd

BILD #xx:3, Rd

BILD #xx:3, @Rd

BILD #xx:3, @aa:8

BIOR #xx:3, Rd

BIOR #xx:3, @Rd

BIOR #xx:3, @aa:8

BIST #xx:3, Rd

BIST #xx:3, @Rd

BIST #xx:3, @aa:8

BIXOR #xx:3, Rd

BIXOR #xx:3, @Rd

BIXOR #xx:3, @aa:8 2

BLD #xx:3, Rd

BLD #xx:3, @Rd

BLD #xx:3, @aa:8

BNOT #xx:3, Rd

BNOT #xx:3, @Rd

BNOT #xx:3, @aa:8

BNOT Rn, Rd

BNOT Rn, @Rd

BNOT Rn, @aa:8

BOR #xx:3, Rd

BOR #xx:3, @Rd

BOR #xx:3, @aa:8

BSET #xx:3, Rd

BSET #xx:3, @Rd

BSET #xx:3, @aa:8

BSET Rn, Rd

BSET Rn, @Rd

Word Data Internal

Access
Operation
M
N

Table A.4

Number of Cycles in Each Instruction (cont)

Instruction Mnemonic

Instruction Branch
Stack
Byte Data
Fetch
Addr. Read Operation Access
I
J
K
L

BSET

BSET Rn, @aa:8

BSR

BSR d:8

BST

BST #xx:3, Rd

BST #xx:3, @Rd

BST #xx:3, @aa:8

BTST #xx:3, Rd

BTST #xx:3, @Rd

BTST #xx:3, @aa:8

BTST Rn, Rd

BTST Rn, @Rd

BTST Rn, @aa:8

BXOR #xx:3, Rd

BXOR #xx:3, @Rd

BXOR #xx:3, @aa:8 2

BTST

BXOR

CMP

CMP. B #xx:8, Rd

CMP. B Rs, Rd

CMP.W Rs, Rd

DAA

DAA.B Rd

DAS

DAS.B Rd

DEC

DEC.B Rd

DIVXU

DIVXU.B Rs, Rd

EEPMOV

EEPMOV

INC

INC.B Rd

JMP

JMP @Rn

JMP @aa:16

JMP @@aa:8

JSR @Rn

JSR @aa:16

JSR @@aa:8

LDC #xx:8, CCR

JSR

LDC

MOV

LDC Rs, CCR

MOV.B #xx:8, Rd

MOV.B Rs, Rd

Word Data Internal

Access
Operation
M
N

2
1

12
2n+2*

2
1

2
1
1

Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
417

Table A.4

Number of Cycles in Each Instruction (cont)

Instruction Mnemonic

Instruction Branch
Stack
Byte Data
Fetch
Addr. Read Operation Access
I
J
K
L

MOV

MOV.B @(d:16, Rs), 2

Rd

MOV.B @Rs+, Rd

MOV.B @aa:8, Rd

MOV.B @aa:16, Rd

MOV.B Rs, @Rd

MOV.B Rs, @(d:16,

Rd)

MOV.B Rs, @Rd

MOV.B Rs, @aa:8

MOV.B Rs, @aa:16

MOV.W #xx:16, Rd

MOV.W Rs, Rd

MOV.W @Rs, Rd

MOV.W @(d:16, Rs), 2

Rd

MOV.W @Rs+, Rd

MOV.W @aa:16, Rd 2

MOV.B @Rs, Rd

MOV.W Rs, @Rd

MOV.W Rs, @(d:16d) 2

MOV.W Rs, @Rd

MOV.W Rs, @aa:16 2

MULXU

MULXU.B Rs, Rd

NEG

NEG.B Rd

NOP

NOP

NOT

NOT.B Rd

OR

OR.B #xx:8, Rd

OR.B Rs, Rd

ORC

ORC #xx:8, CCR

ROTL

ROTL.B Rd

ROTR

ROTR.B Rd

ROTXL

ROTXL.B Rd

ROTXR

ROTXR.B Rd

418

Word Data Internal

Access
Operation
M
N

12

Table A.4

Number of Cycles in Each Instruction (cont)

Instruction Mnemonic

Instruction Branch
Stack
Byte Data
Fetch
Addr. Read Operation Access
I
J
K
L

RTE

RTE

RTS

RTS

SHAL

SHAL.B Rd

SHAR

SHAR.B Rd

SHLL

SHLL.B Rd

SHLR

SHLR.B Rd

SLEEP

SLEEP

STC

STC CCR, Rd

SUB

SUB.B Rs, Rd

SUB.W Rs, Rd

SUBS.W #1, Rd

SUBS.W #2, Rd

POP

POP Rd

PUSH

PUSH Rs

SUBX

SUBX.B #xx:8, Rd

SUBS

XOR

XORC

SUBX.B Rs, Rd

XOR.B #xx:8, Rd

XOR.B Rs, Rd

XORC #xx:8, CCR

Word Data Internal

Access
Operation
M
N

419

Appendix B Internal I/O Registers

B.1

Addresses

Register
Address Name
Bit 7

Bit Names
Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Module
Name

Timer X

H'F740
H'F741
H'F742
H'F743
H'F744
H'F770

TIER

ICIAE

ICIBE

ICICE

ICIDE

OCIAE

OCIBE

OVIE

H'F771

TCSRX

ICFA

ICFB

ICFC

ICFD

OCFA

OCFB

OVF

CCLRA

H'F772

FRCH

FRCH7

FRCH6

FRCH5

FRCH4

FRCH3

FRCH2

FRCH1

FRCH0

H'F773

FRCL

FRCL7

FRCL6

FRCL5

FRCL4

FRCL3

FRCL2

FRCL1

FRCL0

H'F774

OCRAH/
OCRBH

OCRAH7/ OCRAH6/ OCRAH5/ OCRAH4/ OCRAH3/ OCRAH2/ OCRAH1/ OCRAH0/O

OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 CRBH0

H'F775

OCRAL/
OCRBL

OCRAL7/ OCRAL6/ OCRAL5/ OCRAL4/ OCRAL3/ OCRAL2/ OCRAL1/ OCRAL0/

OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0

H'F776

TCRX

IEDGA

IEDGB

IEDGC

IEDGD

BUFEA

BUFEB

CKS1

CKS0

H'F777

TOCR

OCRS

OEA

OEB

OLVLA

OLVLB

H'F778

ICRAH

ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0

H'F779

ICRAL

ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0

F'F77A

ICRBH

ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0

F'F77B

ICRBL

ICRBL7 ICRBL6 ICRBL5 ICRBL4 ICRBL3 ICRBL2 ICRBL1 ICRBL0

H'F77C

ICRCH

ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0

H'F77D

ICRCL

ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0

H'F77E

ICRDH

ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0

H'F77F

ICRDL

ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0

H'FF80

FLMCR

VPP

EV

PV

H'FF82

EBR1

LB3

LB2

LB1

LB0

H'FF83

EBR2

SB7

SB6

SB5

SB4

SB3

SB2

SB1

SB0

H'FF81

420

Flash
memory
(flash
memory
version
only)

Bit Names

Register
Address Name
Bit 7

Bit 6

Bit 5

Bit 3

Bit 2

Bit 1

Bit 0

Module
Name

H'FFA0

SCR1

SNC1

SNC0

MRKON LTCH

CKS3

CKS2

CKS1

CKS0

SCI1

H'FFA1

SCSR1

SOL

ORER

MTRF

STF

H'FFA2

SDRU

SDRU7

H'FFA3

SDRL

SDRL7

SDRU6

SDRU5

SDRU4

SDRU3

SDRU2

SDRU1

SDRU0

SDRL6

SDRL5

SDRL4

SDRL3

SDRL2

SDRL1

SDRL0

H'FFA8

SMR

COM

CHR

PE

PM

STOP

MP

CKS1

CKS0

H'FFA9

BRR

BRR7

BRR6

BRR5

BRR4

BRR3

BRR2

BRR1

BRR0

H'FFAA
H'FFAB

SCR3

TIE

RIE

TE

RE

MPIE

TEIE

CKE1

CKE0

TDR

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1

TDR0

H'FFAC SSR

TDRE

RDRF

OER

FER

PER

TEND

MPBR

MPBT

H'FFAD RDR

RDR7

RDR6

RDR5

RDR4

RDR3

RDR2

RDR1

RDR0

Bit 4

H'FFA4
H'FFA5
H'FFA6
H'FFA7
SCI3

H'FFAE
H'FFAF
H'FFB0

TMA

TMA7

TMA6

TMA5

TMA3

TMA2

TMA1

TMA0

H'FFB1

TCA

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

H'FFB2

TMB1

TMB17

TMB12

TMB11

TMB10

H'FFB3

TCB1/
TLB1

TCB17/
TLB17

TCB16/
TLB16

TCB15/
TLB15

TCB14/
TLB14

TCB13/
TLB13

TCB12/
TLB12

TCB11/
TLB11

TCB10/
TLB10

H'FFB8

TCRV0

CMIEB

CMIEA

OVIE

CCLR1

CCLR0

CKS2

CKS1

CKS0

H'FFB9

TCSRV

CMFB

CMFA

OVF

OS3

OS2

OS1

OS0

H'FFBA

TCORA

TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0

H'FFBB

TCORB

TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0

Timer A

Timer B1

H'FFB4
H'FFB5
H'FFB6
H'FFB7

H'FFBC TCNTV

TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0

H'FFBD TCRV1

TVEG1

TVEG0

TRGE

Timer V

ICKS0

Legend:
SCI1: Serial communication interface 1

421

Bit Names

Register
Address Name
Bit 7

Bit 6

Bit 5

Bit 4

H'FFBE

TCSRW B6WI

TCWE

B4WI

H'FFBF

TCW

TCW7

TCW6

H'FFC4

AMR

CKS

H'FFC5

ADRR

ADR7

H'FFC6

ADSR

H'FFD0

PWCR

H'FFD1
H'FFD2

PWDRL

Bit 3

Bit 2

Bit 1

Bit 0

TCSRWE B2WI

WDON

BOWI

WRST

TCW5

TCW4

TCW3

TCW2

TCW1

TCW0

TRGE

CH3

CH2

CH1

CH0

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

ADSF

PWDRU

Module
Name
Watchdog
timer

H'FFC0
H'FFC1
H'FFC2
H'FFC3
A/D
converter

H'FFC7
H'FFC8
H'FFC9
H'FFCA
H'FFCB
H'FFCC
H'FFCD
H'FFCE
H'FFCF

PWCR0 14-bit
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM

PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0

H'FFD3
H'FFD4

PDR1

P17

P16

P15

P14

P10

H'FFD5

PDR2

P22

P21

P20

H'FFD6

PDR3

P32

P31

P30

H'FFD8

PDR5

P57

P56

P55

P54

P53

P52

P51

P50

H'FFD9

PDR6

P67

P66

P65

P64

P63

P62

P61

P60

H'FFDA PDR7

P77

P76

P75

P74

P73

H'FFDB PDR8

P87

P86

P85

P84

P83

P82

P81

P80

H'FFDC PDR9

P94

P93

P92

P91

P90

H'FFDD PDRB

PB 7

PB 6

PB 5

PB 4

PB 3

PB 2

PB 1

PB 0

H'FFD7

H'FFDE
H'FFDF

422

I/O ports

Register
Address Name
Bit 7

Bit Names
Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H'FFE0

Module
Name
I/O ports

H'FFE1
H'FFE2
H'FFE3
H'FFE4

PCR1

PCR17

PCR16

PCR15

PCR14

PCR10

H'FFE5

PCR2

PCR22

PCR21

PCR20

H'FFE6

PCR3

PCR32

PCR31

PCR30

H'FFE8

PCR5

PCR57

PCR56

PCR55

PCR54

PCR53

PCR52

PCR51

PCR50

H'FFE9

PCR6

PCR67

PCR66

PCR65

PCR64

PCR63

PCR62

PCR61

PCR60

H'FFEA

PCR7

PCR77

PCR76

PCR75

PCR74

PCR73

H'FFEB

PCR8

PCR87

PCR86

PCR85

PCR84

PCR83

PCR82

PCR81

PCR80

H'FFEC PCR9

PCR94

PCR93

PCR92

PCR91

PCR90

H'FFED PUCR1

PUCR17 PUCR16 PUCR15 PUCR14

PUCR10

H'FFEE

PUCR3

PUCR32 PUCR31 PUCR30

H'FFEF

PUCR5

PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50

H'FFF0

SYSCR1 SSBY

STS2

STS1

STS0

LSON

MA1

MA0

H'FFF1

SYSCR2

NESEL

DTON

MSON

SA1

SA0

H'FFF2

IEGR1

IEG3

IEG2

IEG1

IEG0

H'FFF3

IEGR2

INTEG7

INTEG6

INTEG5

INTEG4

INTEG3

INTEG2

INTEG1

INTEG0

H'FFF4

IENR1

IENTB1 IENTA

IEN3

IEN2

IEN1

IEN0

H'FFF5

IENR2

IENDT

IENSI

H'FFF6

IENR3

INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0

H'FFF7

IRR1

IRRTB1 IRRTA

IRRI3

IRRI2

IRRI1

IRRI0

H'FFF8

IRR2

IRRDT

IRRAD

IRRS1

H'FFF9

IRR3

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

H'FFFC

PMR1

IRQ3

IRQ2

IRQ1

PWM

TMOW

H'FFFD

PMR3

SO1

SI1

SCK1

PMR7

TXD

POF1

I/O ports

H'FFE7

IENAD

System
control

H'FFFA
H'FFFB
I/O ports

H'FFFE
H'FFFF

I/O ports

423

B.2

Functions

Register
acronym

Register
name

Address to which the

register is mapped

Name of
on-chip
supporting
module
Timer C

H'B4

TMCTimer mode register C

Bit
numbers
Bit

Initial bit
values

TMC7

TMC6

TMC5

TMC2

TMC1

TMC0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

Clock select
0 0 0 Internal clock: /8192
1 Internal clock: /2048
1 0 Internal clock: /512
1 Internal clock: /64
1 0 0 Internal clock: /16
1 Internal clock: /4
1 0 Internal clock: W /4
1 External event (TMIC): Rising or falling edge

Possible types of access

R

Read only

Write only

R/W Read and write

Counter up/down control

0 0 TCC is an up-counter
1 TCC is a down-counter
1 * TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
Auto-reload function select
0 Interval timer function selected
1 Auto-reload function selected
Note: * Don't care

424

Names of the
bits. Dashes
() indicate
reserved bits.

Full name
of bit

Descriptions
of bit settings

TIERTimer interrupt enable register

Bit

H'F770

Timer X

ICIAE

ICIBE

ICICE

ICIDE

OCIAE

OCIBE

OVIE

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Timer overflow interrupt enable

0 Interrupt request (FOVI) by OVF is disabled
1 Interrupt request (FOVI) by OVF is enabled
Output compare interrupt B enable
0 Interrupt request (OCIB) by OCFB is disabled
1 Interrupt request (OCIB) by OCFB is enabled
Output compare interrupt A enable
0 Interrupt request (OCIA) by OCFA is disabled
1 Interrupt request (OCIA) by OCFA is enabled
Input capture interrupt D enable
0 Interrupt request (ICID) by ICFD is disabled
1 Interrupt request (ICID) by ICFD is enabled
Input capture interrupt C enable
0 Interrupt request (ICIC) by ICFC is disabled
1 Interrupt request (ICIC) by ICFC is enabled
Input capture interrupt B enable
0 Interrupt request (ICIB) by ICFB is disabled
1 Interrupt request (ICIB) by ICFB is enabled
Input capture interrupt A enable
0 Interrupt request (ICIA) by ICFA is disabled
1 Interrupt request (ICIA) by ICFA is enabled

425

TCSRXTimer control/status register X

Bit

H'F771

Timer X

ICFA

ICFB

ICFC

ICFD

OCFA

OCFB

OVF

CCLRA

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/(W)*

R/W

Counter clear A
0 FRC is not cleared by compare match A
1 FRC is cleared by compare match A
Timer overflow
0 [Clearing condition]
After reading OVF = 1, cleared by writing 0 to OVF
1 [Setting condition]
Set when the FRC value goes from H'FFFF to H'0000
Output compare flag B
0 [Clearing condition]
After reading OCFB = 1, cleared by writing 0 to OCFB
1 [Setting condition]
Set when FRC matches OCRB
Output compare flag A
0 [Clearing condition]
After reading OCFA = 1, cleared by writing 0 to OCFA
1 [Setting condition]
Set when FRC matches OCRA
Input capture flag D
0 [Clearing condition]
After reading ICFD = 1, cleared by writing 0 to ICFD
1 [Setting condition]
Set by input capture signal
Input capture flag C
0 [Clearing condition]
After reading ICFC = 1, cleared by writing 0 to ICFC
1 [Setting condition]
Set by input capture signal
Input capture flag B
0 [Clearing condition]
After reading ICFB = 1, cleared by writing 0 to ICFB
1 [Setting condition]
When the value of FRC is transferred to ICRB by the input
capture signal
Input capture flag A
0 [Clearing condition]
After reading ICFA = 1, cleared by writing 0 to ICFA
1 [Setting condition]
When the value of FRC is transferred to ICRA by the input
capture signal

Note: * Only a write of 0 for flag clearing is possible.

426

FRCHFree-running counter H
Bit

H'F772

Timer X

FRCH7

FRCH6

FRCH5

FRCH4

FRCH3

FRCH2

FRCH1

FRCH0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Count value

FRCLFree-running counter L
Bit

H'F773

Timer X

FRCL7

FRCL6

FRCL5

FRCL4

FRCL3

FRCL2

FRCL1

FRCL0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Count value

OCRAHOutput compare register AH

Bit

H'F774
4

Timer X
1

OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

OCRBHOutput compare register BH

Bit

H'F774
4

Timer X
1

OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

427

OCRALOutput compare register AL

Bit

H'F775
4

Timer X
1

OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

OCRBLOutput compare register BL

Bit

H'F775
4

Timer X
1

OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

428

TCRXTimer control register X

Bit

H'F776

Timer X

IEDGA

IEDGB

IEDGC

IEDGD

BUFEA

BUFEB

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock select
0 0 Internal clock: /2
1 Internal clock: /8
1 0 Internal clock: /32
1 Internal clock: rising edge
Buffer enable B
0 ICRD is not used as a buffer register for ICRB
1 ICRD is used as a buffer register for OCRB
Buffer enable A
0 ICRC is not used as a buffer register for ICRA
1 ICRC is used as a buffer register for OCRA
Input edge select D
0 Rising edge of input D is captured
1 Falling edge of input D is captured
Input edge select C
0 Rising edge of input C is captured
1 Falling edge of input C is captured
Input edge select B
0 Rising edge of input B is captured
1 Falling edge of input B is captured
Input edge select A
0 Rising edge of input A is captured
1 Falling edge of input A is captured

429

TOCRTimer Output compare control register

Bit

H'F777

Timer X

OCRS

OEA

OEB

OLVLA

OLVLB

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

Output level B
0 Low level
1 High level
Output level A
0 Low level
1 High level
Output enable B
0 Output compare B output is disabled
1 Output compare B output is enabled
Output enable A
0 Output compare A output is disabled
1 Output compare A output is enabled
Output compare register select
0 OCRA is selected
1 OCRB is selected

430

ICRAHInput capture register AH

Bit

H'F778
5

Timer X
1

ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0

Initial value

Read/Write

ICRALInput capture register AL

Bit

ICRAL7 ICRAL6

H'F779
5

ICRAL5 ICRAL4 ICRAL3 ICRAL2

Timer X
1

ICRAL1 ICRAL0

Initial value

Read/Write

ICRBHInput capture register BH

Bit

H'F77A
5

Timer X
1

ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0

Initial value

Read/Write

ICRBLInput capture register BL

Bit

ICRBL7 ICRBL6

H'F77B
5

ICRBL5 ICRBL4 ICRBL3 ICRBL2

Timer X
1

ICRBL1 ICRBL0

Initial value

Read/Write

431

FLMCRFlash memory control register

Bit

H'FF80

Flash memory
(Flash memory version only)

VPP

EV

PV

Initial value

Read/Write

R/W

R/W

R/W

R/W

Program mode
0 Exit from program mode
1 Transition to program mode
Erase mode
0 Exit from erase mode
1 Transition to erase mode
Program-verify mode
0 Exit from program-verify mode
1 Transition to program-verify mode
Erase-verify mode
0 Exit from erase-verify mode
1 Transition to erase-verify mode
Programming power
0 12 V is not applied to the FVPP pin
1 12 V is applied to the FVPP pin

432

EBR1Erase block register 1

Bit

H'FF82

Flash memory
(Flash memory version only)

LB3

LB2

LB1

LB0

Initial value

Read/Write

R/W

R/W

R/W

R/W

Large block 3 to 0
0 Not selected
1 Selected

EBR2Erase block register 2

Bit

H'FF83

Flash memory
(Flash memory version only)

SB7

SB6

SB5

SB4

SB3

SB2

SB1

SB0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Small block 7 to 0
0 Not selected
1 Selected

433

ICRCHInput capture register CH

Bit

H'F77C
5

Timer X
1

ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0

Initial value

Read/Write

ICRCLInput capture register CL

Bit

H'F77D
5

Timer X
1

ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0

Initial value

Read/Write

ICRDHInput capture register DH

Bit

H'F77E
5

Timer X
1

ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0

Initial value

Read/Write

ICRDLInput capture register DL

Bit

H'F77F
5

Timer X
1

ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0

Initial value

Read/Write

434

SCR1Serial control register 1

Bit

H'FFA0

SCI1

SNC1

SNC0

MRKON

LTCH

CKS3

CKS2

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock select (CKS2 to CKS0)

Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1

Serial Clock Cycle

Synchronous
Prescaler
Division
= 5 MHz
= 2.5 MHz
/1024
204.8 s
409.6 s
/256
51.2 s
102.4 s
12.8 s
25.6 s
/64
6.4 s
12.8 s
/32
3.2 s
6.4 s
/16
1.6 s
3.2 s
/8
0.8 s
1.6 s
/4

0.8 s
/2

Clock source select (CKS3)

0 Clock source is prescaler S, and pin SCK 1 is output pin
1 Clock source is external clock, and pin SCK 1 is input pin
LATCH TAIL select
0 HOLD TAIL is output
1 LATCH TAIL is output
TAIL MARK control
0 TAIL MARK is not output (synchronous mode)
1 TAIL MARK is output (SSB mode)
Operation mode select
0 0 8-bit synchronous transfer mode
1 16-bit synchronous transfer mode
1 0 Continuous clock output mode
1 Reserved

435

SCSR1Serial control/status register

Bit

H'FFA1

SCI1

SOL

ORER

MTRF

STF

Initial value

Read/Write

R/W

R/(W)*

R/W

Start flag
0 Read
Write
1 Read
Write

Indicates that transfer is stopped

Invalid
Indicates transfer in progress
Starts a transfer operation

TAIL MARK transmit flag

0 Idle state and 8- or -16-bit data transfer in progress
1 TAIL MARK transmission in progress
Overrun error flag
0 [Clearing condition]
After reading 1, cleared by writing 0
1 [Setting condition]
Set if a clock pulse is input after transfer
is complete, when an external clock is used
Extended data bit
0 Read SO1 pin output level is low
Write SO1 pin output level changes to low
1 Read SO1 pin output level is high
Write SO1 pin output level changes to high
Note: * Only a write of 0 for flag clearing is possible.

436

SDRUSerial data register U

Bit
Initial value
Read/Write

H'FFA2

SCI1

SDRU7

SDRU6

SDRU5

SDRU4

SDRU3

SDRU2

SDRU1

SDRU0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Stores transmit and receive data

8-bit transfer mode: Not used
16-bit transfer mode: Upper 8 bits of data

SDRLSerial data register L

Bit
Initial value
Read/Write

H'FFA3

SCI1

SDRL7

SDRL6

SDRL5

SDRL4

SDRL3

SDRL2

SDRL1

SDRL0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Stores transmit and receive data

8-bit transfer mode: 8-bit data
16-bit transfer mode: Lower 8 bits of data

437

SMRSerial mode register

Bit

H'FFA8

SCI3

COM

CHR

PE

PM

STOP

MP

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock select
0 0 clock
1 /4 clock
1 0 /16 clock
1 /64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data
1 7-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode

438

BRRBit rate register

Bit

H'FFA9

SCI3

BRR7

BRR6

BRR5

BRR4

BRR3

BRR2

BRR1

BRR0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

439

SCR3Serial control register 3

Bit

H'FFAA

SCI3

TIE

RIE

TE

RE

MPIE

TEIE

CKE1

CKE0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock enable
Bit 0
Bit 1
CKE1 CKE0
0
0
1
1

0
1

Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous

Description
Clock Source
SCK 3 Pin Function
Internal clock
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Reserved (Do not specify this combination)
External clock
Clock input
External clock
Serial clock input
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)

Transmit end interrupt enable

0
1

Transmit end interrupt request (TEI) disabled

Transmit end interrupt request (TEI) enabled

Multiprocessor interrupt enable

0

Multiprocessor interrupt request disabled (normal receive operation)

[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1

Multiprocessor interrupt request enabled

The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.

Receive enable
0

Receive operation disabled (RXD pin is I/O port)

Receive operation enabled (RXD pin is receive data pin)

Transmit enable
0

Transmit operation disabled (TXD pin is transmit data pin)*1

Transmit operation enabled (TXD pin is transmit data pin)*1

Note: 1. When bit TXD is set to 1 in PMR7

Receive interrupt enable
0

Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled

Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled

Transmit interrupt enable

0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled

440

TDRTransmit data register

Bit

H'FFAB

SCI3

TDR7

TDR6

TDR5

TDR4

TDR3

TDR2

TDR1

TDR0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Data for transfer to TSR

441

SSRSerial status register

Bit

SCI3

TDRE

RDRF

OER

FER

PER

TEND

MPBR

MPBT

R/W

Initial value

Read/Write

H'FFAC

R/(W)

0
*

R/(W)

R/(W)

0
*

R/(W)

R/(W)

Multiprocessor bit transfer

0

A 0 multiprocessor bit is transmitted

A 1 multiprocessor bit is transmitted

Multiprocessor bit receive

0

Data in which the multiprocessor bit is 0 has been received

Data in which the multiprocessor bit is 1 has been received

Transmit end
0

Transmission in progress
[Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction

Transmission ended
[Setting conditions]

When bit TE in serial control register 3 (SCR3) is cleared to 0

When bit TDRE is set to 1 when the last bit of a transmit character is sent

Parity error
0

Reception in progress or completed normally

[Clearing conditions] After reading PER = 1, cleared by writing 0 to PER

A parity error has occurred during reception

[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)

Framing error
0

Reception in progress or completed normally

[Clearing conditions] After reading FER = 1, cleared by writing 0 to FER

A framing error has occurred during reception

[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0

Overrun error
0

Reception in progress or completed

[Clearing conditions] After reading OER = 1, cleared by writing 0 to OER

An overrun error has occurred during reception

[Setting conditions] When the next serial reception is completed with RDRF set to 1

Receive data register full

0

There is no receive data in RDR

[Clearing conditions] After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction

There is receive data in RDR

[Setting conditions] When reception ends normally and receive data is transferred from RSR to RDR

Transmit data register empty

0

Transmit data written in TDR has not been transferred to TSR

[Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction

Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions] When bit TE in serial control register 3 (SCR3) is cleared to 0
When data is transferred from TDR to TSR

Note: * Only a write of 0 for flag clearing is possible.

442

RDRReceive data register

Bit

H'FFAD

SCI3

RDR7

RDR6

RDR5

RDR4

RDR3

RDR2

RDR1

RDR0

Initial value

Read/Write

TMATimer mode register A

Bit

H'FFB0

Timer A

TMA7

TMA6

TMA5

TMA3

TMA2

TMA1

TMA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock output select

0 0 0 /32
1 /16
1 0 /8
1 /4
1 0 0 W /32
1 W /16
1 0 W /8
1 W /4

Internal clock select

Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
/8192
0
PSS
1
PSS
/4096
/2048
PSS
1
0
/512
PSS
1
1
0
0
/256
PSS
1
/128
PSS
/32
1
0
PSS
/8
1
PSS
0
0
0
1s
1
PSW
1
0.5 s
PSW
0.25 s
1
0
PSW
0.03125 s
1
PSW
1
0
0
PSW and TCA are reset
1
1
0
1

Function
Interval
timer

Time
base

443

TCATimer counter A
Bit

H'FFB1

Timer A

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

Initial value

Read/Write

Count value

TMB1Timer mode register B1

Bit

H'FFB2

Timer B1

TMB17

TMB12

TMB11

TMB10

Initial value

Read/Write

R/W

R/W

R/W

R/W

Auto-reload function select

0 Interval timer function selected
1 Auto-reload function selected

444

Clock select
0 0 0 Internal clock: /8192
1 Internal clock: /2048
1 0 Internal clock: /512
1 Internal clock: /256
1 0 0 Internal clock: /64
1 Internal clock: /16
1 0 Internal clock: /4
1 External event (TMIB): Rising or falling edge

TCB1Timer counter B1
Bit

H'FFB3

Timer B1

TCB17

TCB16

TCB15

TCB14

TCB13

TCB12

TCB11

TCB10

Initial value

Read/Write

Count value

TLB1Timer load register B1

Bit

H'FFB3

Timer B1

TLB17

TLB16

TLB15

TLB14

TLB13

TLB12

TLB11

TLB10

Initial value

Read/Write

Reload value

445

TCRV0Timer control register V0

Bit

H'FFB8

Timer V

CMIEB

CMIEA

OVIE

CCLR1

CCLR0

CKS2

CKS1

CKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Clock select
TCRV0
TCRV1
Bit 2 Bit 1 Bit 0 Bit 0
Description
CKS2 CKS1 CKS0 ICKS0
Clock input disabled
0
0
0
0
Internal clock: /4, falling edge
1
1
Internal clock: /8, falling edge
1
0
0
Internal clock: /16, falling edge
1
Internal clock: /32, falling edge
1
0
Internal clock: /64, falling edge
1
Internal clock: /128, falling edge
1
0
0
Clock input disabled
1
External clock: rising edge
1
0
External clock: falling edge
1
External clock: rising and falling edges

Counter clear 1 and 0

0 Clearing is disabled
Cleared by compare match A
1 Cleared by compare match B
Cleared by rising edge of external reset input
Timer overflow interrupt enable
0 Interrupt request (OVI) from OVF disabled
1 Interrupt request (OVI) from OVF enabled
Compare match interrupt enable A
0 Interrupt request (CMIA) from CMFA disabled
1 Interrupt request (CMIA) from CMFA enabled
Compare match interrupt enable B
0 Interrupt request (CMIB) from CMFB disabled
1 Interrupt request (CMIB) from CMFB enabled

446

TCSRVTimer control/status register V

Bit

H'FFB9

Timer V

CMFB

CMFA

OVF

OS3

OS2

OS1

OS0

Initial value

Read/Write

R/(W)*

R/(W)*

R/(W)*

R/W

R/W

R/W

R/W

Output select
0 0 No change at compare match A
1 0 output at compare match A
1 0 1 output at compare match A
1 Output toggles at compare match A
Output select
0 0 No change at compare match B
1 0 output at compare match B
1 0 1 output at compare match B
1 Output toggles at compare match B
Timer overflow flag
0 [Clearing condition]
After reading OVF = 1, cleared by writing 0 to OVF
1 [Setting condition]
Set when TCNTV overflows from H'FF to H'00
Compare match flag A
0 [Clearing condition]
After reading CMFA = 1, cleared by writing 0 to CMFA
1 [Setting condition]
Set when the TCNTV value matches the TCORA value
Compare match flag B
0 [Clearing condition]
After reading CMFB = 1, cleared by writing 0 to CMFB
1

[Setting condition]
Set when the TCNTV value matches the TCORB value

Note: * Only a write of 0 for flag clearing is possible.

447

TCORATime constant register A

Bit

H'FFBA
5

Timer V
1

TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCORBTime constant register B

Bit

H'FFBB
5

Timer V
1

TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TCNTVTimer counter V
Bit

H'FFBC
6

Timer V
1

TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

448

TCRV1Timer control register V1

Bit

H'FFBD

Timer V

TVEG1

TVEG0

TRGE

ICKS0

Initial value

Read/Write

R/W

R/W

R/W

R/W

Internal clock select

Selects the TCNTV clock source, with bits
CKS2 to CKS0 in TCRV0

TRGV input enable

0 TCNTV counting is not triggered by input at the TRGV pin, and
does not stop when TCNTV is cleared by compare match
1 TCNTV counting is triggered by input at the TRGV pin, and
stops when TCNTV is cleared by compare match

TRGV input edge select

0 0 TRGV trigger input is disabled
1 Rising edge is selected
1 0 Falling edge is selected
1 Rising and falling edges are both selected

449

TCSRWTimer control/status register W

Bit
Initial value
Read/Write

H'FFBE

Watchdog timer

B6WI

TCWE

B4WI

TCSRWE

B2WI

WDON

B0WI

WRST

R/(W)*

R/(W)*

R/(W) *

R/(W) *

Watchdog timer reset

0 [Clearing conditions]
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-protected
Watchdog timer on
0 Watchdog timer operation is disabled
1 Watchdog timer operation is enabled
Bit 2 write inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-protected
Timer control/status register W write enable
0 Data cannot be written to TCSRW bits 2 and 0
1 Data can be written to TCSRW bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1 Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
450

TCWTimer counter W
Bit

H'FFBF

Watchdog timer

TCW7

TCW6

TCW5

TCW4

TCW3

TCW2

TCW1

TCW0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Count value

451

AMRA/D mode register

Bit

H'FFC4

A/D converter

CKS

TRGE

CH3

CH2

CH1

CH0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

Channel select
Bit 3 Bit 2 Bit 1
CH3 CH2 CH1
0
0
*
1
0

0
0

*
0
1
0
1
0
1
0
1
0
1

1
1

0
1

1
1

0
1

Bit 0
CH0

Analog Input Channel

No channel selected
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
Reserved
Reserved
Reserved
Reserved

External trigger select

0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Clock select
Bit 7
CKS Conversion Period
0
62/
1
31/

Conversion Time
= 2 MHz = 5 MHz
31 s
15.5 s

12.4 s
*1

Notes: * Dont care

1. Operation is not guaranteed if the conversion time is less than 12.4 s.
Set bit 7 for a value of at least 12.4 s.

452

ADRRA/D result register

Bit
Initial value
Read/Write

H'FFC5

A/D converter

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R

A/D conversion result

ADSRA/D start register

Bit

H'FFC6

A/D converter

ADSF

Initial value

Read/Write

R/W

A/D status flag

0 Read Indicates completion of A/D conversion
Write Stops A/D conversion
1 Read Indicates A/D conversion in progress
Write Starts A/D conversion

453

PWCRPWM control register

Bit

H'FFD0

14-bit PWM

PWCR0

Initial value

Read/Write

Clock select
0 The input clock is /2 (t* = 2/). The conversion period is 16,384/,
with a minimum modulation width of 1/.
1 The input clock is /4 (t* = 4/). The conversion period is 32,768/,
with a minimum modulation width of 2/.

Note: * t: Period of PWM input clock

PWDRUPWM data register U

Bit

H'FFD1

14-bit PWM

Initial value

Read/Write

PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0

Upper 6 bits of data for generating PWM waveform

PWDRLPWM data register L

Bit

7
PWDRL7

H'FFD2
5

PWDRL6 PWDRL5

PWDRL4 PWDRL3 PWDRL2

14-bit PWM
1

PWDRL1 PWDRL0

Initial value

Read/Write

Lower 8 bits of data for generating PWM waveform

454

PDR1Port data register 1

Bit

H'FFD4

I/O ports

P17

P16

P15

P14

P10

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

PDR2Port data register 2

Bit

H'FFD5

I/O ports

P22

P21

P20

Initial value

Read/Write

R/W

R/W

R/W

PDR3Port data register 3

Bit

H'FFD6

I/O ports

P32

P31

P30

Initial value

Read/Write

R/W

R/W

R/W

PDR5Port data register 5

Bit

H'FFD8

I/O ports

P5 7

P56

P55

P54

P53

P52

P51

P50

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PDR6Port data register 6

Bit

H'FFD9

I/O ports

P6 7

P66

P65

P64

P63

P62

P61

P60

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

455

PDR7Port data register 7

Bit

H'FFDA

I/O ports

P7 7

P76

P75

P74

P73

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

PDR8Port data register 8

Bit

H'FFDB

I/O ports

P8 7

P86

P85

P84

P83

P82

P81

P80

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PDR9Port data register 9

Bit

H'FFDC

P94

P93

P92

P91

P90

R/W

R/W

R/W

R/W

Initial value

Read/Write

R/W

PDRBPort data register B

Bit

I/O ports

H'FFDD

I/O ports

PB 7

PB 6

PB 5

PB 4

PB 3

PB 2

PB 1

PB 0

Initial value
Read/Write

PCR1Port control register 1

Bit

H'FFE4

I/O ports

PCR17

PCR16

PCR15

PCR14

PCR10

Initial value

Read/Write

Port 1 input/output select

0 Input pin
1 Output pin

456

PCR2Port control register 2

Bit

H'FFE5

I/O ports

PCR22

PCR21

PCR20

Initial value

Read/Write

Port 2 input/output select

0 Input pin
1 Output pin

PCR3Port control register 3

Bit

H'FFE6

I/O ports

PCR32

PCR31

PCR30

Initial value

Read/Write

Port 3 input/output select

0 Input pin
1 Output pin

PCR5Port control register 5

Bit

H'FFE8

I/O ports

PCR57

PCR56

PCR55

PCR54

PCR53

PCR52

PCR51

PCR50

Initial value

Read/Write

Port 5 input/output select

0 Input pin
1 Output pin

457

PCR6Port control register 6

Bit

H'FFE9

I/O ports

PCR6 7

PCR6 6

PCR6 5

PCR6 4

PCR6 3

PCR6 2

PCR6 1

PCR6 0

Initial value

Read/Write

Port 6 input/output select

0 Input pin
1 Output pin

PCR7Port control register 7

Bit

H'FFEA

I/O ports

PCR77

PCR76

PCR75

PCR74

PCR73

Initial value

Read/Write

Port 7 input/output select

0 Input pin
1 Output pin

PCR8Port control register 8

Bit

H'FFEB

I/O ports

PCR87

PCR86

PCR85

PCR84

PCR83

PCR82

PCR81

PCR80

Initial value

Read/Write

Port 8 input/output select

0 Input pin
1 Output pin

458

PCR9Port control register 9

Bit

H'FFEC

PCR9 4

Initial value

Read/Write

I/O ports
1

PCR91

PCR90

PCR9 3 PCR92

Port 9 input/output select

0 Input pin
1 Output pin

PUCR1Port pull-up control register 1

Bit

H'FFED
4

PUCR17 PUCR16 PUCR15 PUCR14

I/O ports

PUCR10

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

PUCR3Port pull-up control register 3

Bit

H'FFEE

I/O ports

Initial value

Read/Write

R/W

R/W

R/W

PUCR5Port pull-up control register 5

Bit

PUCR32 PUCR31 PUCR30

H'FFEF
4

I/O ports
1

PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

459

SYSCR1System control register 1

Bit

H'FFF0

System control

SSBY

STS2

STS1

STS0

LSON

MA1

MA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Active (medium-speed)
mode clock select
0 0 osc /16
1 osc /32
1 0 osc /64
1 osc /128
Low speed on flag
0 The CPU operates on the system clock ()
1 The CPU operates on the subclock (SUB )
Standby timer select 2 to 0
0 0 0 Wait time = 8,192 states
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 * * Wait time = 131,072 states
Software standby
0 When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode

Note: * Dont care

460

SYSCR2System control register 2

Bit

H'FFF1

System control

NESEL

DTON

MSON

SA1

SA0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

Subactive mode clock select

Medium speed on flag

0 0 W /8
1 W /4
1 * W /2

0 Operates in active (high-speed) mode after exit from standby, watch, or sleep
mode
Operates in sleep (high-speed) mode if a SLEEP instruction is executed in
active mode
1 Operates in active (medium-speed) mode after exit from standby, watch,
or sleep mode
Operates in sleep (medium-speed) mode if a SLEEP instruction is executed
in active mode
Direct transfer on flag
0 When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise elimination sampling frequency select
0 Sampling rate is OSC /16
1 Sampling rate is OSC /4
Note: * Dont care

461

IEGR1Interrupt edge select register 1

Bit

H'FFF2

System control

IEG3

IEG2

IEG1

IEG0

Initial value

Read/Write

R/W

R/W

R/W

R/W

IRQ0 edge select

0 Falling edge of IRQ0 pin input is detected
1 Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0 Falling edge of IRQ1 pin input is detected
1 Rising edge of IRQ1 pin input is detected
IRQ2 edge select
0 Falling edge of IRQ2 pin input is detected
1 Rising edge of IRQ2 pin input is detected
IRQ3 edge select
0 Falling edge of IRQ3 pin input is detected
1 Rising edge of IRQ3 pin input is detected

462

IEGR2Interrupt edge select register 2

Bit

H'FFF3
4

System control
1

INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

INT4 to INT0 edge select

0 Falling edge of INTn pin input is detected
1 Rising edge of INTn pin input is detected
(n = 4 to 0)
INT5 edge select
0 Falling edge of INT5 and ADTRG pin input is detected
1 Rising edge of INT5 and ADTRG pin input is detected
INT6 edge select
0 Falling edge of INT6 and TMIB pin input is detected
1 Rising edge of INT6 and TMIB pin input is detected
INT7 edge select
0 Falling edge of INT7 and TMIY pin input is detected
1 Rising edge of INT7 and TMIY pin input is detected

463

IENR1Interrupt enable register 1

Bit

H'FFF4

System control

IENTB1

IENTA

IEN3

IEN2

IEN1

IEN0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

IRQ3 to IRQ0 interrupt enable

0 Disables IRQ3 to IRQ0 interrupt requests
1 Enables IRQ3 to IRQ0 interrupt requests
Timer A interrupt enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
Timer B1 interrupt enable
0 Disables timer B1 interrupt requests
1 Enables timer B1 interrupt requests

464

IENR2Interrupt enable register 2

Bit

H'FFF5

System control

IENDT

IENAD

IENS1

Initial value

Read/Write

R/W

R/W

R/W

SCI1 interrupt enable

0 Disables SCI1 interrupt requests
1 Enables SCI1 interrupt requests
A/D converter interrupt enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct transfer interrupt enable
0 Disables direct transfer interrupt requests
1 Enables direct transfer interrupt requests

IENR3Interrupt enable register 3

Bit

H'FFF6

System control

INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

INT7 to INT0 interrupt enable

0 Disables INT7 to INT0 interrupt requests
1 Enables INT7 to INT0 interrupt requests

465

IRR1Interrupt request register 1

Bit

H'FFF7

System control

IRRTB1

IRRTA

IRRI3

IRRI2

IRRI1

IRRI0

Initial value

Read/Write

R/W *

R/W *

R/W *

R/W *

R/W *

R/W *

IRQ3 to IRQ0 interrupt request flag

0 [Clearing condition]
When IRRIn = 1, it is cleared by writing 0
1 [Setting condition]
When pin IRQn is set for interrupt input and the designated signal
edge is input
(n = 3 to 0)
Timer A interrupt request flag
0 [Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1 [Setting condition]
When timer counter A overflows from H'FF to H'00
Timer B1 interrupt request flag
0 [Clearing condition]
When IRRTB1 = 1, it is cleared by writing 0
1 [Setting condition]
When timer counter B1 overflows from H'FF to H'00

Note: * Only a write of 0 for flag clearing is possible.

466

IRR2Interrupt request register 2

Bit

H'FFF8

System control

IRRDT

IRRAD

IRRS1

Initial value

Read/Write

R/W *

R/W *

R/W *

SCI1 interrupt request flag

0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When an SCI1 transfer is completed

A/D converter interrupt request flag

0 [Clearing condition]
When IRRAD = 1, it is cleared by writing 0
1 [Setting condition]
When A/D conversion is completed and ADSF is cleared to 0 in ADSR

Direct transfer interrupt request flag

0 [Clearing condition]
When IRRDT = 1, it is cleared by writing 0
1 [Setting condition]
A SLEEP instruction is executed when DTON = 1 and a direct transfer is made
Note: * Only a write of 0 for flag clearing is possible.

467

IRR3Interrupt request register 3

Bit

H'FFF9

System control

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

Initial value

Read/Write

R/W *

R/W *

R/W *

R/W

R/W *

R/W *

R/W *

R/W *

INT7 to INT0 interrupt request flag

0 [Clearing condition]
When INTFn = 1, it is cleared by writing 0
1 [Setting condition]
When the designated signal edge is input at pin INTn
(n = 7 to 0)
Note: * Only a write of 0 for flag clearing is possible.

468

PMR1Port mode register 1

Bit

H'FFFC

I/O ports

IRQ3

IRQ2

IRQ1

PWM

TMOW

Initial value

Read/Write

R/W

R/W

R/W

R/W

R/W

P10/TMOW pin function switch

0 Functions as P10 I/O pin
1 Functions as TMOW output pin
P14/PWM pin function switch
0 Functions as P14 I/O pin
1 Functions as PWM output pin
P15/IRQ1 pin function switch
0 Functions as P15 I/O pin
1 Functions as IRQ1 input pin
P16/IRQ2 pin function switch
0 Functions as P16 I/O pin
1 Functions as IRQ2 input pin
P17/IRQ3 pin function switch
0 Functions as P17 I/O pin
1 Functions as IRQ3/TRGV input pin

469

PMR3Port mode register 3

Bit

H'FFFD

I/O ports

SO1

SI1

SCK1

Initial value

Read/Write

R/W

R/W

R/W

P30/SCK1 pin function switch

0 Functions as P30 I/O pin
1 Functions as SCK1 I/O pin
P31/SI1 pin function switch
0 Functions as P31 I/O pin
1 Functions as SI1 input pin
P32/SO1 pin function switch
0 Functions as P32 I/O pin
1 Functions as SO1 output pin

PMR7Port mode register 7

Bit

H'FFFF

I/O ports

TXD

POF1

Initial value

Read/Write

R/W

R/W

P32/SO1 pin PMOS control

0 CMOS output
1 NMOS open-drain output
P22/TXD pin function switch (TXD)
0 Functions as P22 I/O pin
1 Functions as TXD output pin
470

Appendix C I/O Port Block Diagrams

C.1

Block Diagrams of Port 1

SBY
RES
(low level
during reset
and in standby
mode)

PUCR1n

VCC
VCC

PMR1n

PDR1n

P1n

VSS

Internal
data bus

PCR1n

IRQn4

PDR1:
PCR1:
PMR1:
PUCR1:

Port data register 1

Port control register 1
Port mode register 1
Port pull-up control register 1

n = 7 or 6

Figure C.1 (a) Port 1 Block Diagram (Pins P1 7 and P16)

471

SBY
(low level during
reset and in
standby mode)

RES

PUCR15
VCC
VCC

PMR15

PDR15

P15

Internal
data bus

PCR15

VSS

IRQ1

PDR1:
PCR1:
PMR1:
PUCR1:

Port data register 1

Port control register 1
Port mode register 1
Port pull-up control register 1

Figure C.1 (b) Port 1 Block Diagram (Pin P15)

472

PWM
module

RES
SBY
(low level during
reset and in
standby mode)

PWM

PUCR14
VCC
VCC

PMR14

PDR14

P14

PCR14

VSS

PDR1:
PCR1:
PMR1:
PUCR1:

Internal
data bus

Port data register 1

Port control register 1
Port mode register 1
Port pull-up control register 1

Figure C.1 (c) Port 1 Block Diagram (Pin P14)

473

Timer A
module

RES
SBY
(low level during
reset and in
standby mode)

TMOW

PUCR10
VCC
VCC

PMR10

PDR10

P10

PCR10

VSS

PDR1:
PCR1:
PMR1:
PUCR1:

Port data register 1

Port control register 1
Port mode register 1
Port pull-up control register 1

Figure C.1 (d) Port 1 Block Diagram (Pin P10)

474

Internal
data bus

C.2

Block Diagrams of Port 2

SBY

PMR72
SCI3
module

VCC

TXD

P22

PDR22

PCR22

VSS

PDR2:
PCR2:
PMR7:

Internal
data bus

Port data register 2

Port control register 2
Port mode register 7

Figure C.2 (a) Port 2 Block Diagram (Pin P2 2)

475

SBY

SCI3
module

VCC

RE
RXD

P21

PDR21

PCR21

VSS

PDR2:
PCR2:

Port data register 2

Port control register 2

Figure C.2 (b) Port 2 Block Diagram (Pin P21)

476

Internal
data bus

SBY
SCI3
module
SCKIE
SCKOE

VCC

SCKO
SCKI
P20

PDR20

PCR20

VSS

PDR2:
PCR2:

Internal
data bus

Port data register 2

Port control register 2

Figure C.2 (c) Port 2 Block Diagram (Pin P20)

477

C.3

Block Diagrams of Port 3

SCI1
module

RES
SBY
(low level during
reset and in
standby mode)

SO1
PMR70

PUCR32
VCC
VCC

PMR32

PDR32

P32

PCR32

VSS

PDR3:
PCR3:
PMR3:
PMR7:
PUCR3:

Port data register 3

Port control register 3
Port mode register 3
Port mode register 7
Port pull-up control register 3

Figure C.3 (a) Port 3 Block Diagram (Pin P3 2)

478

Internal
data bus

SBY
(low level
during reset
and in standby
mode)

RES

PUCR31

VCC
VCC

PMR31

PDR31

P31

Internal
data bus

PCR31

VSS

SCI1
module
SI1

PDR3:
PCR3:
PMR3:
PUCR3:

Port data register 3

Port control register 3
Port mode register 3
Port pull-up control register 3

Figure C.3 (b) Port 3 Block Diagram (Pin P31)

479

SCI1
module

RES
SBY
(low level during
reset and in
standby mode)

CKS3
SCK0
SCK1
PUCR30

VCC
VCC

PDR30

P30

PCR30

VSS

PDR3:
PCR3:
PMR3:
PUCR3:

Port data register 3

Port control register 3
Port mode register 3
Port pull-up control register 3

Figure C.3 (c) Port 3 Block Diagram (Pin P30)

480

Internal data bus

PMR30

C.4

Block Diagrams of Port 5

SBY
(low level
during reset
and in standby
mode)

RES

PUCR5n

VCC

PDR5n

P5n

VSS

PCR5n

Internal data bus

VCC

INT
module
INTn

PDR5: Port data register 5

PCR5: Port control register 5
PUCR5: Port pull-up control register 5
n = 7, 4 to 0

Figure C.4 (a) Port 5 Block Diagram (Pins P5 7 and P54 to P50)

481

SBY
(low level
during reset
and in standby
mode)

Timer B1
module

PUCR56

VCC
TMIB

PDR56

P56

PCR56

VSS

Internal data bus

VCC

INT
module
INT6
PDR5: Port data register 5
PCR5: Port control register 5
PUCR5: Port pull-up control register 5

Figure C.4 (b) Port 5 Block Diagram (Pin P56)

482

SBY
(low level
during reset
and in standby
mode)

RES
A/D
module

PUCR55

VCC
ADTRG

PDR55

P55

PCR55

VSS

Internal data bus

VCC

INT
module
INT5
PDR5: Port data register 5
PCR5: Port control register 5
PUCR5: Port pull-up control register 5

Figure C.4 (c) Port 5 Block Diagram (Pin P55)

483

C.5

Block Diagram of Port 6

SBY
(low level during reset
and in standby mode)

VCC

P6n

PDR6n

PCR6n

VSS

PDR6:
PCR6:

Port data register 6

Port control register 6

n = 7 to 0

Figure C.5 Port 6 Block Diagram (Pins P67 to P60)

484

Internal
data bus

C.6

Block Diagrams of Port 7

SBY
(low level during reset
and in standby mode)

VCC

PDR7n

P7n

VSS

Internal
data bus

PCR7n

PDR7: Port data register 7

PCR7: Port control register 7
n = 7 or 3

Figure C.6 (a) Port 7 Block Diagram (Pins P7 7 and P73)

485

SBY
(low level during reset
and in standby mode)
Timer V
module
VCC

0S3
to
0S0
TMOV
PDR76

P76

PCR76

VSS

PDR7: Port data register 7

PCR7: Port control register 7

Figure C.6 (b) Port 7 Block Diagram (Pin P76)

486

Internal
data bus

SBY
(low level during reset
and in standby mode)

VCC

PDR75

P75

Internal
data bus

PCR75

VSS

Timer V
module
TMCIV

PDR7: Port data register 7

PCR7: Port control register 7

Figure C.6 (c) Port 7 Block Diagram (Pin P75)

487

SBY
(low level during reset
and in standby mode)

VCC

PDR74

P74

Internal
data bus

PCR74

VSS

Timer V
module
TMRIV

PDR7: Port data register 7

PCR7: Port control register 7

Figure C.6 (d) Port 7 Block Diagram (Pin P74)

488

C.7

Block Diagrams of Port 8

SBY
(low level during reset
and in standby mode)

VCC

PDR87

P87

Internal
data bus

PCR87

VSS

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (a) Port 8 Block Diagram (Pin P8 7)

489

SBY
(low level during reset
and in standby mode)

VCC

PDR86

P86

Internal
data bus

PCR86

VSS

Timer X
module
FTID

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (b) Port 8 Block Diagram (Pin P86)

490

SBY
(low level during reset
and in standby mode)

VCC

PDR85

P85

Internal
data bus

PCR85

VSS

Timer X
module
FTIC

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (c) Port 8 Block Diagram (Pin P85)

491

SBY
(low level during reset
and in standby mode)

VCC

PDR84

P84

Internal
data bus

PCR84

VSS

Timer X
module
FTIB

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (d) Port 8 Block Diagram (Pin P84)

492

SBY
(low level during reset
and in standby mode)

VCC

PDR83

P83

Internal
data bus

PCR83

VSS

Timer X
module
FTIA

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (e) Port 8 Block Diagram (Pin P83)

493

SBY
(low level during reset
and in standby mode)

Timer X
module

VCC

OEB
FTOB
PDR82

P82

PCR82

VSS

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (f) Port 8 Block Diagram (Pin P82)

494

Internal
data bus

SBY
(low level during reset
and in standby mode)

Timer X
module

VCC

OEA
FTOA
PDR81

P81

PCR81

VSS

Internal
data bus

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (g) Port 8 Block Diagram (Pin P8 1)

495

SBY
(low level during reset
and in standby mode)

VCC

PDR80

P80

Internal
data bus

PCR80

VSS

Timer X
module
FTCI

PDR8: Port data register 8

PCR8: Port control register 8

Figure C.7 (h) Port 8 Block Diagram (Pin P80)

496

C.8

Block Diagram of Port 9

SBY
(low level during reset
and in standby mode)

VCC

PDR9n

P9n

VSS

Internal
data bus

PCR9n

PDR9: Port data register 9

PCR9: Port control register 9
n = 4 to 0

Figure C.8 Port 9 Block Diagram (Pins P94 to P90)

497

C.9

Block Diagram of Port B

Internal
data bus

PBn

A/D module
DEC

AMR3 to AMR0

VIN

n = 7 to 0

Figure C.9 Port B Block Diagram (Pins PB7 to PB0)

498

Appendix D Port States in the Different Processing States

Table D.1
Port

Port States Overview

Reset

Sleep

Subsleep Standby

Watch

Subactive Active

Retained
P17 to P1 4, High
impedance
P10

Retained

High
Retained
impedance*

Functions

Functions

P22 to P2 0

High
Retained
impedance

Retained

High
Retained
impedance

Functions

Functions

P32 to P3 0

High
Retained
impedance

Retained

High
Retained
impedance*

Functions

Functions

P57 to P5 0

High
Retained
impedance

Retained

High
Retained
impedance*

Functions

Functions

P67 to P6 0

High
Retained
impedance

Retained

High
Retained
impedance

Functions

Functions

P77 to P7 3

High
Retained
impedance

Retained

High
Retained
impedance

Functions

Functions

P87 to P8 0

High
Retained
impedance

Retained

High
Retained
impedance

Functions

Functions

P94 to P9 0

High
Retained
impedance

Retained

High
Retained
impedance

Functions

Functions

PB7 to PB 0 High
High
High
High
High
High
High
impedance impedance impedance impedance impedance impedance impedance
Note: * High level output when MOS pull-up is in on state.

499

Appendix E Product Code Lineup

Table E.1

Product Lineup

Product Type
H8/3644

Product Code

ZTATTM
version

F-ZTAT
version

TM

Mask ROM
version

H8/3643

FLASH

Mask ROM
version

H8/3642

FLASH

Mark Code

Package
(Hitachi Package Code)

Standard HD6473644H
products HD6473644P

HD6473644H

64-pin QFP (FP-64A)

HD6473644P

64-pin SDIP (DP-64S)

HD6473644W

HD6473644W

80-pin TQFP (TFP-80C)

HD64F3644H

HD64F3644H

64-pin QFP (FP-64A)

HD64F3644P

HD64F3644P

64-pin SDIP (DP-64S)

HD64F3644W

HD64F3644W

80-pin TQFP (TFP-80C)

HD6433644H

HD6433644(***)H 64-pin QFP (FP-64A)

HD6433644P

HD6433644(***)P 64-pin SDIP (DP-64S)

HD6433644W

HD6433644(***)W 80-pin TQFP (TFP-80C)

Standard HD64F3643H
products HD64F3643P

HD64F3643H

64-pin QFP (FP-64A)

HD64F3643P

64-pin SDIP (DP-64S)

HD64F3643W

HD64F3643W

80-pin TQFP (TFP-80C)

HD6433643H

HD6433643(***)H 64-pin QFP (FP-64A)

HD6433643P

HD6433643(***)P 64-pin SDIP (DP-64S)

HD6433643W

HD6433643(***)W 80-pin TQFP (TFP-80C)

Standard HD64F3642AH HD64F3642AH

products HD64F3642AP HD64F3642AP
HD64F3642AW HD64F3642AW

Mask ROM
version

H8/3641

Mask ROM
version

Mask ROM
version

80-pin TQFP (TFP-80C)

HD6433642(***)H 64-pin QFP (FP-64A)

HD6433642P

HD6433642(***)P 64-pin SDIP (DP-64S)

HD6433642W

HD6433642(***)W 80-pin TQFP (TFP-80C)

Standard HD6433641H
products HD6433641P

Standard HD6433640H
products HD6433640P
HD6433640W

HD6433641(***)H 64-pin QFP (FP-64A)

HD6433641(***)P 64-pin SDIP (DP-64S)
HD6433641(***)W 80-pin TQFP (TFP-80C)
HD6433640(***)H 64-pin QFP (FP-64A)
HD6433640(***)P 64-pin SDIP (DP-64S)
HD6433640(***)W 80-pin TQFP (TFP-80C)

Note: For mask ROM versions, (***) is the ROM code.

500

64-pin SDIP (DP-64S)

HD6433642H

HD6433641W
H8/3640

64-pin QFP (FP-64A)

Appendix F Package Dimensions

Dimensional drawings of H8/3644 packages FP-64A, DP-64S and TFP-80C are shown in figures
F.1 to F.3 below.
Unit: mm

17.2 0.3
14

33

48

32
0.8

17.2 0.3

49

64

17
1

0.10

*0.17 0.05
0.15 0.04

3.05 Max

1.0

2.70

0.15 M

0.10 +0.15
0.10

*0.37 0.08
0.35 0.06

16

1.6
0 8
0.8 0.3

*Dimension including the plating thickness

Base material dimension

Figure F.1 FP-64A Package Dimensions

501

Unit: mm

33
17.0
18.6 Max

64

57.6
58.5 Max

32

1.0

1.78 0.25

0.48 0.10

0.51 Min

1.46 Max

2.54 Min 5.08 Max

19.05

+ 0.11

0.25 0.05
0 15

Figure F.2 DP-64S Package Dimensions

502

14.0 0.2

Unit: mm

12
60

41
40

80

21

0.5

14.0 0.2

61

0.10
*Dimension including the plating thickness
Base material dimension

0.10 0.10

1.25

1.00

0.10 M

*0.17 0.05
0.15 0.04

20
1.20 Max

1
*0.22 0.05
0.20 0.04

1.0
0 8
0.5 0.1

Figure F.3 TFP-80C Package Dimensions

Note: In case of inconsistencies arising within figures, dimensional drawings listed in the
Hitachi Semiconductor Packages Manual take precedence and are considered correct.

503

H8/3644 Series, H8/3644F-ZTAT,

H8/3643 F-ZTAT, H8/3642 AF-ZTAT,
Hardware Manual
Publication Date: 1st Edition, September 1996
4th Edition, August 1998
Published by:
Electronic Devices Sales & Marketing Group
Hitachi, Ltd.
Edited by:
Technical Documentation Group
UL Media Co., Ltd.
Copyright Hitachi, Ltd., 1996. All rights reserved. Printed in Japan.

This datasheet has been downloaded from:

www.DatasheetCatalog.com
Datasheets for electronic components.