9.0.

MICROPIPELINES
TWO CONCEPTUAL FRAMEWORKS
In the clocked logic conceptual framework, registers of flip flops
operating from common clock separate stages of processing logic
The clocked logic conceptual framework is widely used
because it offers a simple way to design computing equipment,
because it is widely taught and understood
because parts that operate with clock are widely available , and
because system noise has died away by the time the clock event
occurs.

Transition signalling conceptual framework offers the opportunity

to build up complex systems by hierarchical composition from
simpler pieces, we attain a flexibility to compose systems from
small parts previously designed and tested.

TRANSITION SIGNALLING
Rising and falling transitions on signalling wires have the same
meaning. They are called events.

Two Equivalent Transitions

Because the absolute state of a transition control signal is
unimportant, there is no need to return it to some neutral state
between events. By avoiding such returns to a neutral or state,
transition signalling saves the time and energy costs of the return
transition.
Transition signalling circuits must be symmetric with respect to
high or low states of control signals. The symmetry of transition
signalling provides appealing simplicity in complementary metal
oxide (CMOS) circuits because it fits well with the symmetry of
the complementary transistors from which CMOS circuits are
built.

THE TWO-PHASE BOUNDED DATA CONVENTION

A Bundled Data Interface:

Request

SENDER

Acknowledge

RECEIVER

DATA

In addition to any number of data wires, an interface following the

two-phase bundled data convention has two signalling wires here
called request and acknowledge. The sender puts valid data on
the data wires and then produces an event on its control wire
request, to indicate that valid data are available. The receiver
takes the data and then produces an event on the acknowledge wire
to indicate that the data have been accepted. The request and
acknowledge wires are sometimes given other names.
The three events, data change, request event, acknowledge event,
always follow in cyclic order. Successive cycles may take different
amounts of time.

The Two-phase Bundled Data Convention (Interface Protocol)

2

Request

Acknowledge
3
1

Data
One Cycle
Senders
Action

Next Cycle
Receivers
Action

The three events per cycle in the two-phase bundled convention

occur cyclically in the sequence shown. They are:
1. During the senders active phase, shown with solid arrows, the
sender may change the data at will.
2. After the sender has established correct data values, it ends its
active phase by producing the request event to indicate that
valid data are available. During the receivers active phase,
shown with dotted arrows, the sender must hold the data
constant.
3. After the receiver no longer needs this data values, it ends its
active phase by producing the acknowledge event. Either phase
may last for as much or as little time as its controlling unit
decrees. Note that request and acknowledge events alternate.

Non-overlapping Clocks

C1

C2
1
Data

One Cycle

Next Cycle

Conventional non-overlapping clocks, C1 and C2, require 5 events

per cycle. They are:
1. Data change
2. C1 rises
3. C1 falls
4. C2 rises
5. C2 falls
This non-overlapping clock protocol we can compare with twophase bundled data protocol (three events per cycle).

A Dynamic Muller C-Element

X
C
X

Y
Z

In CMOS the Muller C-element has a particularly simple dynamic

implementation that uses the electrical capacitance of an internal
node as the storage element. Transistors to initialize the Muller Celement during master clear are not shown.

EVENT LOGIC
Modules of 10 to 100 transistors can perform useful logic functions
on events. Note the similarity of these functions to the basic
structures used in programming.
Control circuits for transition signalling are built out of modules
that form various logic combinations of events.
OR element

The exclusive OR circuit (conventional logic gate) acts as the OR

element for events. When either input of an XOR circuit changes
state, its output also changes state. Thus an event received on
either the first OR the second input of XOR will produce an output
event.

AND element

C
Muller C-element provide the AND function for events.
When both inputs are in the same logical state, the Muller
C-elements state and its output are copies of that state. When the
two inputs differ, the Muller C-element uses internal storage to
retain its previous state and hold its output unchanged. Thus only
after an event takes place on both of its inputs will a Muller
C-element produce an event at its output.
Such elements are sometimes called RENDEVOUS elements,
because they act only after all input events have arrived.

Muller C-elements contain storage to hold a previous state on some

input conditions. When inverters are included in input or output
wires, as indicated by the bubbles in these figures, the actions are
as listed.

C
If inputs match in state THEN copy it for output ELSE hold
previous state.

C
If inputs match in state THEN invert it for output ELSE hold
previous state.

C
If inputs differ in state THEN copy upper for output ELSE hold
previous state.

TOGGLE element

TOGGLE

*
TOGGLE steers events to its output alternately starting starting
with the dot.
The TOGGLE circuit produces events alternately on its two
outputs in response to events at its input; the first event after some
master clear signal and every other subsequent event pass through
it to the output the dot.

SELECT element

SELECT
true

false

SELECT steers events according to the Boolean value of its input

with diamond. It serves for testing the Boolean condition in
conditional expressions. The Boolean value must be available
before the incoming event that it steers.

CALL element
R1
D1
R

CALL
D
D2
R2

CALL remembers which client, R1 or R2, called the procedure R,

and after the procedure is done, D returns a matching done event
on D1 or D2.
The memory in the CALL element serves the role of subroutine
return address. The CALL element operates properly only if each
call completes before a subsequent call occurs.
ARBITER element
R1

G1
D1

ARBITER
R2

D2
G2

ARBITER grants service, G1 or G2, to only one input request, R1

or R2, at a time, delaying subsequent grants until after the
matching done event, D1 or D2.
Like a semaphore in programming, it delays subsequent grants
after receiving an event on the done wire corresponding to an
earlier so that only one grant at a time is ever outstanding.
An ARBITER can be connected directly to a CALL element to
permit two entirely independent processes to call on a single
shared procedure.

CONTROL FOR MICROPIPELINES

With data paths omitted, the control circuit for a micropipeline is a
string of Muller C-elements. In this figure four identical stages are
presented and alternate stages have been drawn upside down. At
input and output of each stage there are request, R(n), and
acknowledge, A(n), signals. Inverters in the acknowledge paths are
represented by bubbles at one input of each Muller C-element.
Notice that each loop in this circuit contains exactly one inversion,
the bubble, and is therefore an oscillator. The Muller C-element
retard the oscillation in each loop to coordinate it with actions of
adjacent loops.
R(in)

A(1)

R(2)

A(3)

R(out)

DELAY

DELAY

C
A(in) DELAY R(1)

A(2)

DELAY

R(3)

DIRECTION OF DATA FLOW

A(out)

At each interface between stages the request and acknowledge

signals and the data values follow exactly the two-phase bundled
data conversion.

A(n-1)

DELAY

R(n)

C
R(n-1)

A(n)

Let us focus on the state of each Muller C-element relative to

predecessor and successor Muller C-elements. Remembering the
behavior of Muller C-element with one inverted input, we can
easily see that each stage follows a very simple stage state rule:
IF predecessor and successor differ in state
THEN copy predecessors state
ELSE hold present state.
This stage state rule makes the control system stable both when all
the stages are in the same state and when alternate stages are in
opposite states. The condition in which all control elements are in
the same state corresponds to an empty pipeline, and the condition
in which alternate stages in opposite states correspond to a filled
pipeline

Circuit for Switch Symbol

+
C

Z
C
X

Z
The double throw switch symbol at the bottom of this drawing
represents the transistor circuit shown inside the dotted line. When
the control wire, C, is low, the output terminal, Z, is controlled by
the Y input, as shown. When the control wire is high, the switch
flips to the X input. The output of this form of switch is controlled
by its selected input, but inverted in value. Other implementations
of such a switch using pass transistors are also possible.

Event- Controlled Storage Elements

IN

Out

Capture

Pass

An event-controlled storage element responds to events on its two

control wires, called capture and pass in this drawing.
After master clear the switches will in the position shown, making
a direct connection without loops between input and output, a state
in which the storage element is said to be transparent.

Cd

C
REGISTER

Pd

Storage elements are formed into registers just as are flip-flops by

connecting their capture and pass control wires in parallel. The
register symbol includes control outputs, Cd, and Pd, which are
amplified, and thus necessarily delayed, versions of the control
input signals, C and P, Cd and Pd, named for capture done and
pass done, deliver output events after the register has done its
action.