LNA Design

Using UMS Foundry Design Kit

Alain Michel, Ansoft France
Tony Donisi, Ansoft USA

Presentaton #10
 Agenda
w LNA Design
w Introduction
w FET Characteristics
w Input Match
w Output Match
w Layout Considerations
w Final Results
w Design kit Description
w Building Design Kit in Ansoft Designer
w Layout stationary file (Layers definition)
w Component creation
w Symbols, Layout, Electrical and Components creation
w Conclusion
 LNA Design

UsingUMS
Using UMSPH25
PH25Design
DesignKit
Kit
Thiscircuit
This circuitwas
wasdesigned
designedby
byCNES
CNES
 Introduction
w It is difficult to obtain a good noise match
with a good input match
w Broad frequency range
w “optimal” noise match typically mismatches the
input
w Balancing the amplifier degrades noise figure
w Γopt is the “optimum noise matching point of
an LNA
w This match gives optimal noise figure, or nopt
w Design approach
w Choose FET topology/Process Such that Γopt is
close to 50Ω

LNADesign
LNA Design
 FET Characteristics

Process PH25 Low Noise PH15 Low Noise HP07 Power PPH25 Power PPH15 Power HB20P Power HB20L L-Band BES

0.6dB/13dB @10GHz 0.5dB/14dB@10GHz

Noise / Gain
2dB/8dB @40GHz 1.9dB/6dB@60GHz

Power 250mW/mm 300mW/mm 500mW/mm 700mW/mm 600mW/mm 3500mW/mm 2000mW/mm@3V

Gate length 0.25µm 0.15µm 0.7µm 0.25µm 0.15µm 2µm 3µm 1µm

Active layer MBE MBE Implanted MBE MBE Epitaxy Epitaxy MBE

IDS (gm max) IDS 200mA/mm 300mA/mm

200mA/mm 500mA/mm 220mA/mm 550mA/mm 450mA/mm 0.3mA/µm² 0.3mA/µm²
SAT/IC HBT 450mA/mm 600mA/mm

>-5V
VBDS / VBCE >5V >4V >14V >12V >8V >16V >15V
(Anode/Cathode)

Cut off freq. 90GHz 110GHz 15GHz 50GHz 75GHz 25GHz 25GHz 3THz

Data source UMS

w Two process dedicated to Low Noise application

w The bias conditions are chosen following the
foundry recommendation: IDSS/x
w The topology of the FET is chosen for Γopt close to
50Ohm

LNADesign
LNA Design
 Input Match:
FET Topology
w Start with linear S and noise parameters
w Choose foundry’s recommended Low-Noise
topology
w Plot Γopt
w Add series feedback
w Slightly degrades noise
w Allows “tuning” of Γopt

LNADesign
LNA Design
 Γopt Versus FET Topology:
Simulation

LNADesign
LNA Design
 Γopt versus FET Topology:
Results
ΓΓopt at 40Ghz
opt at 40Ghz for
for
4x30um FET
4x30um FET

LNADesign
LNA Design
 Noise Match:
Adding Series Feedback

LNADesign
LNA Design
 Gopt & Stabilization:
Tuning Source Inductance

LNADesign
LNA Design
 Noise Figure Variation
With Series Inductance

This 3D
This 3D plot
plot has
has aa
“minimum” along
“minimum” along the
the
inductance axis
inductance axis with
with
respect to
respect to frequency.
frequency.
This indicates
This indicates that
that
there is
there is an
an inductance
inductance
that will
that will minimize
minimize thethe
50Ω noise
50Ω noise figure.
figure.

LNADesign
LNA Design
 Input Match: Smith Tool

LNADesign
LNA Design
 Input Match: Smith Tool

LNADesign
LNA Design
 Output Match: Smith Tool

LNADesign
LNA Design
 Input and output Matched

LNADesign
LNA Design
 Insertion of Capacitance
To Attenuate Low Frequency Gain

LNADesign
LNA Design
 From Ideal to Real
w Step by step replacement of ideal elements
w Tuning
w Optimization
w TRL
w Replace ideal capacitors, Inductors and
vias
w Use elements from design kit
w Optimize layout
w Absorb parasitics
w Build parameterized field solver sub-circuit
w Planar EM Co-simulation

LNADesign
LNA Design
 Final Schematic

LNADesign
LNA Design
 Electromagnetic Elements:
Solver On Demand

LNADesign
LNA Design
 Electromagnetic Elements:
Solver On Demand

LNADesign
LNA Design
 Final Layout

LNADesign
LNA Design
 Final Results S21, NF & FMIN

LNADesign
LNA Design
 Final Results S11 & S22

LNADesign
LNA Design
 Final Results: K

LNADesign
LNA Design
 Tolerance Analysis

LNADesign
LNA Design
 Tolerance Analysis Results
Gain & Noise Figure

LNADesign
LNA Design
 Tolerance Analysis Results
Return Loss & Stability

LNADesign
LNA Design
 Design kit Description
Mandatory Foundry Data
For Design Kit Creation:

w Electrical model documentation

w Model topologies
w Equations
w Relationship with layout
w Layout design rules
w Layer definitions
w Layout cell geometries
w Design rules

DesignKit
Design KitDescription
Description
 Electrical model
Model Topology
Model Topology (MIM
(MIM Capacitor)
Capacitor)

Equations
2) main capacitance

The main capacitance is described by capacitance C in series with a resistance Rs:

Relation
SEL = L * WEL (surface of the top electrode)
C(pF) = coef1 * SEL (mm2)
Rs(W)= (coef2 + coef3 * Lai(mm)) / WN1(mm) with layout
3/ air-bridge output

The output circuit is the equivalent circuit of air-bridge

- Lo (pH) = coef4 - coef5 * ln(WB(mm))

- Ro (W) = coef6 * 1/WB(mm)
- Co (fF) = coef7 + coef8 * WB(mm)

DesignKit
Design KitDescription
Description
 Layout Design Rules
Layer
Layer Layout Cell
Layout Cell Geometries
Geometries
Definitions
Definitions

Design Rules
Design Rules

DesignKit
Design KitDescription
Description
 Building Design Kit in
Ansoft Designer

DesignKit
Design KitImplementation
Implementation
 Technology File:
Layer Definitions

DesignKit
Design KitImplementation
Implementation
 Component Creation
w A component consists of :
w Symbol
w Layout cell
w Electrical model

Ansoft Designer
Ansoft Designer provides
provides anan
Editor that
Editor that will
will help
help toto create
create
each part
each part and
and link
link them
them
together.
together.

DesignKit
Design KitImplementation
Implementation
 Symbol Creation

DesignKit
Design KitImplementation
Implementation
 Layout Cell Creation

DesignKit
Design KitImplementation
Implementation
 Layout Cell Creation:
Drawing

Boolean
Boolean
Functions
Functions
Add,
Add,
Subtract,
Subtract,
Union, etc.
Union, etc.

DesignKit
Design KitImplementation
Implementation
 Layout Cell Creation:
Fixed or Scripted

DesignKit
Design KitImplementation
Implementation
 Electrical Model Creation
Interpretive
Interpretive
UDM’s
UDM’s

Parameterized
Parameterized
Subcircuits
Subcircuits

Netlist Fragments
Netlist Fragments “C” Coded
“C” Coded UDM’s
UDM’s
DesignKit
Design KitImplementation
Implementation
 Conclusion
w Ansoft Designer offers powerful facilities to
build component and libraries
w Building Design Kit is fast and easy
w LNA design using Designer features:
w Tuning

w Parametric Analysis

w Optimization

w Smith tool

w Parameterized field solver sub-circuit