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HW2

This document contains 8 problems related to digital logic design. The problems cover topics like logic gates, Boolean algebra, transistor-level circuit design, and power/energy calculations. Students are asked to determine logic levels for an inverter, identify logic gates from input/output characteristics, sketch transistor-level circuits, use Boolean reductions, and calculate activity factors and switching power. The document provides figures and context to accompany each multi-part problem. Solutions are due by 11:59pm on the following Monday and should be submitted in PDF format on Blackboard.

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213 views4 pages

HW2

This document contains 8 problems related to digital logic design. The problems cover topics like logic gates, Boolean algebra, transistor-level circuit design, and power/energy calculations. Students are asked to determine logic levels for an inverter, identify logic gates from input/output characteristics, sketch transistor-level circuits, use Boolean reductions, and calculate activity factors and switching power. The document provides figures and context to accompany each multi-part problem. Solutions are due by 11:59pm on the following Monday and should be submitted in PDF format on Blackboard.

Uploaded by

maunghtaik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CSE320DesignandSynthesisofDigitalHardwareFall2015

Homework2
Topics
Logicgates
Power
Booleanalgebra

Problem1:(5points)

IsitpossibletoassignlogiclevelssothatadevicewiththetransfercharacteristicsshowninFigure
1.44wouldserveasaninverter?Ifso,whataretheinputandoutputlowandhighlevels(VIL,VOL,
VIH,andVOH)andnoisemargins(NMLandNMH)?Ifnot,explainwhynot.

Fig.1.44DCtransfercharacteristics

Problem2:(10points)
Figure1.48showstheinput/outputcharacteristicofan2inputlogicgateintermsof(Unit:V).
TheinputsareAandBandtheoutputisY.

(a)Whatkindoflogicgateisthis?
(b)Whataretheapproximatehighandlowlogiclevels(VDD=3V)?
Hint:Asbothinputsmustfollowthesamelogiclevels,findtheunitygainpointsforA=B.
SchoolofComputing,Informatics,andDecisionSystemsArizonaStateUniversity

CSE320DesignandSynthesisofDigitalHardwareFall2015

Problem3:(15points)
Sketch a transistorlevel circuit for the following CMOS gates. Use a minimum number of
transistors.
(a)fourinputNANDgate
(b)threeinputORANDINVERTgate(producesaFALSEoutputifCisTRUEandAorBisTRUE.
OtherwiseitproducesaTRUEoutput.)
(c)threeinputANDORgate(producesaTRUEoutputifbothAandBareTRUE,orifCisTRUE.)

Problem4:(15points)
Implement the following threeinput gates using only pseudonMOS logic gates. Your gates
receivethreeinputs,A,B,andC.Useaminimumnumberoftransistors.
(a)threeinputNORgate
(b)threeinputNANDgate
(c)threeinputANDgate

Problem5:(5points)
UsingDeMorganequivalentgatesandbubblepushingmethods,redrawthecircuitinFigure2.83
sothatyoucanfindtheBooleanequationbyinspection.WritetheBooleanequation.

Problem6:(5points)
FindaminimalBooleanequationforthefunctioninFigure2.85.Remembertotakeadvantageof
thedontcareentries.

SchoolofComputing,Informatics,andDecisionSystemsArizonaStateUniversity

CSE320DesignandSynthesisofDigitalHardwareFall2015
Problem7:(10points)
SketchacircuitforthefunctionfromProblem7.Doesyourcircuithaveanypotentialglitches
whenoneoftheinputschanges?Ifnot,explainwhynot.Ifso,showhowtomodifythecircuitto
eliminatetheglitches.
Hint:TherearetwopossibleoptionswhenreducingthelogicfunctioninFigure2.85through
Kmap.Oneofthemhastheglitchproblem.

Problem8Finding(5points)
Figure 2 shows the logical symbol (and functional picture) of an AndOrInvert gate that
implements
.
1 ,
1 , and
Estimate the activity factor, , for the output , if
1
1
4
2
1 .
1
3

B
C

Figure1

Problem9PowerandEnergy

C
A
B

CF

CY

Figure2

9A.Whatlogicfunctionisimplementedbythiscircuit(inputs:A,B,C;output:F)?
9B.Assume the probability of logic 1 for inputs: p(A=1)=0.3, p(B=1)=0.25, p(C=1)=0.3,
capacitancesCY=10fF,CF=40fF,frequencyf=200MHz,VDD=1V,thresholdvoltageVTN=0.2V
andVTP=0.3V.CalculatetheaverageswitchingpowerPswofthecircuit(inputCisafullswing
signal).
9C.Calculatetheheatenergydissipationforonecycle(charge+discharge)associatedwithCy
andCF.
Hint:WatchouttheactualvoltageswingwhenNMOSpasses1orPMOSpassesa0for
switchingenergycalculation.

SchoolofComputing,Informatics,andDecisionSystemsArizonaStateUniversity

CSE320DesignandSynthesisofDigitalHardwareFall2015
DueDate
11:59pmonthenextMonday.

Instructionsonsubmission
SubmityoursolutioninPDFformatonBlackboard.

SchoolofComputing,Informatics,andDecisionSystemsArizonaStateUniversity

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